1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/slab.h> 14 15 #include "clk-gate.h" 16 #include "clk-mtk.h" 17 #include "clk-mux.h" 18 #include "clk-pll.h" 19 20 #include <dt-bindings/clock/mt8192-clk.h> 21 #include <dt-bindings/reset/mt8192-resets.h> 22 23 static DEFINE_SPINLOCK(mt8192_clk_lock); 24 25 static const struct mtk_fixed_clk top_fixed_clks[] = { 26 FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000), 27 }; 28 29 static const struct mtk_fixed_factor top_divs[] = { 30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0), 31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0), 32 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0), 33 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0), 34 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0), 35 FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0), 36 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0), 37 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0), 38 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0), 39 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0), 40 FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0), 41 FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0), 42 FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0), 43 FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0), 44 FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0), 45 FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0), 46 FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0), 47 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0), 48 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0), 49 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0), 50 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0), 51 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0), 52 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0), 53 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0), 54 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0), 55 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0), 56 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0), 57 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0), 58 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0), 59 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0), 60 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0), 61 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0), 62 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 63 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 64 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 65 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 66 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 67 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 68 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 69 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 70 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 71 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 72 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 73 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 74 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 75 FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2), 76 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 77 FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9), 78 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2), 79 FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1), 80 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 81 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), 82 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 83 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 84 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 85 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 86 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 87 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 88 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2), 89 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4), 90 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8), 91 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), 92 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16), 93 FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), 94 FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), 95 FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1), 96 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0), 97 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0), 98 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0), 99 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0), 100 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0), 101 FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0), 102 }; 103 104 static const char * const axi_parents[] = { 105 "clk26m", 106 "mainpll_d4_d4", 107 "mainpll_d7_d2", 108 "mainpll_d4_d2", 109 "mainpll_d5_d2", 110 "mainpll_d6_d2", 111 "osc_d4" 112 }; 113 114 static const char * const spm_parents[] = { 115 "clk26m", 116 "osc_d10", 117 "mainpll_d7_d4", 118 "clk32k" 119 }; 120 121 static const char * const scp_parents[] = { 122 "clk26m", 123 "univpll_d5", 124 "mainpll_d6_d2", 125 "mainpll_d6", 126 "univpll_d6", 127 "mainpll_d4_d2", 128 "mainpll_d5_d2", 129 "univpll_d4_d2" 130 }; 131 132 static const char * const bus_aximem_parents[] = { 133 "clk26m", 134 "mainpll_d7_d2", 135 "mainpll_d4_d2", 136 "mainpll_d5_d2", 137 "mainpll_d6" 138 }; 139 140 static const char * const disp_parents[] = { 141 "clk26m", 142 "univpll_d6_d2", 143 "mainpll_d5_d2", 144 "mmpll_d6_d2", 145 "univpll_d5_d2", 146 "univpll_d4_d2", 147 "mmpll_d7", 148 "univpll_d6", 149 "mainpll_d4", 150 "mmpll_d5_d2" 151 }; 152 153 static const char * const mdp_parents[] = { 154 "clk26m", 155 "mainpll_d5_d2", 156 "mmpll_d6_d2", 157 "mainpll_d4_d2", 158 "mmpll_d4_d2", 159 "mainpll_d6", 160 "univpll_d6", 161 "mainpll_d4", 162 "tvdpll_ck", 163 "univpll_d4", 164 "mmpll_d5_d2" 165 }; 166 167 static const char * const img_parents[] = { 168 "clk26m", 169 "univpll_d4", 170 "tvdpll_ck", 171 "mainpll_d4", 172 "univpll_d5", 173 "mmpll_d6", 174 "univpll_d6", 175 "mainpll_d6", 176 "mmpll_d4_d2", 177 "mainpll_d4_d2", 178 "mmpll_d6_d2", 179 "mmpll_d5_d2" 180 }; 181 182 static const char * const ipe_parents[] = { 183 "clk26m", 184 "mainpll_d4", 185 "mmpll_d6", 186 "univpll_d6", 187 "mainpll_d6", 188 "univpll_d4_d2", 189 "mainpll_d4_d2", 190 "mmpll_d6_d2", 191 "mmpll_d5_d2" 192 }; 193 194 static const char * const dpe_parents[] = { 195 "clk26m", 196 "mainpll_d4", 197 "mmpll_d6", 198 "univpll_d6", 199 "mainpll_d6", 200 "univpll_d4_d2", 201 "univpll_d5_d2", 202 "mmpll_d6_d2" 203 }; 204 205 static const char * const cam_parents[] = { 206 "clk26m", 207 "mainpll_d4", 208 "mmpll_d6", 209 "univpll_d4", 210 "univpll_d5", 211 "univpll_d6", 212 "mmpll_d7", 213 "univpll_d4_d2", 214 "mainpll_d4_d2", 215 "univpll_d6_d2" 216 }; 217 218 static const char * const ccu_parents[] = { 219 "clk26m", 220 "mainpll_d4", 221 "mmpll_d6", 222 "mainpll_d6", 223 "mmpll_d7", 224 "univpll_d4_d2", 225 "mmpll_d6_d2", 226 "mmpll_d5_d2", 227 "univpll_d5", 228 "univpll_d6_d2" 229 }; 230 231 static const char * const dsp7_parents[] = { 232 "clk26m", 233 "mainpll_d4_d2", 234 "mainpll_d6", 235 "mmpll_d6", 236 "univpll_d5", 237 "mmpll_d5", 238 "univpll_d4", 239 "mmpll_d4" 240 }; 241 242 static const char * const mfg_ref_parents[] = { 243 "clk26m", 244 "clk26m", 245 "univpll_d6", 246 "mainpll_d5_d2" 247 }; 248 249 static const char * const mfg_pll_parents[] = { 250 "mfg_ref_sel", 251 "mfgpll" 252 }; 253 254 static const char * const camtg_parents[] = { 255 "clk26m", 256 "univpll_192m_d8", 257 "univpll_d6_d8", 258 "univpll_192m_d4", 259 "univpll_d6_d16", 260 "csw_f26m_d2", 261 "univpll_192m_d16", 262 "univpll_192m_d32" 263 }; 264 265 static const char * const uart_parents[] = { 266 "clk26m", 267 "univpll_d6_d8" 268 }; 269 270 static const char * const spi_parents[] = { 271 "clk26m", 272 "mainpll_d5_d4", 273 "mainpll_d6_d4", 274 "msdcpll_d4" 275 }; 276 277 static const char * const msdc50_0_h_parents[] = { 278 "clk26m", 279 "mainpll_d4_d2", 280 "mainpll_d6_d2" 281 }; 282 283 static const char * const msdc50_0_parents[] = { 284 "clk26m", 285 "msdcpll_ck", 286 "msdcpll_d2", 287 "univpll_d4_d4", 288 "mainpll_d6_d2", 289 "univpll_d4_d2" 290 }; 291 292 static const char * const msdc30_parents[] = { 293 "clk26m", 294 "univpll_d6_d2", 295 "mainpll_d6_d2", 296 "mainpll_d7_d2", 297 "msdcpll_d2" 298 }; 299 300 static const char * const audio_parents[] = { 301 "clk26m", 302 "mainpll_d5_d8", 303 "mainpll_d7_d8", 304 "mainpll_d4_d16" 305 }; 306 307 static const char * const aud_intbus_parents[] = { 308 "clk26m", 309 "mainpll_d4_d4", 310 "mainpll_d7_d4" 311 }; 312 313 static const char * const pwrap_ulposc_parents[] = { 314 "osc_d10", 315 "clk26m", 316 "osc_d4", 317 "osc_d8", 318 "osc_d16" 319 }; 320 321 static const char * const atb_parents[] = { 322 "clk26m", 323 "mainpll_d4_d2", 324 "mainpll_d5_d2" 325 }; 326 327 static const char * const dpi_parents[] = { 328 "clk26m", 329 "tvdpll_d2", 330 "tvdpll_d4", 331 "tvdpll_d8", 332 "tvdpll_d16" 333 }; 334 335 static const char * const scam_parents[] = { 336 "clk26m", 337 "mainpll_d5_d4" 338 }; 339 340 static const char * const disp_pwm_parents[] = { 341 "clk26m", 342 "univpll_d6_d4", 343 "osc_d2", 344 "osc_d4", 345 "osc_d16" 346 }; 347 348 static const char * const usb_top_parents[] = { 349 "clk26m", 350 "univpll_d5_d4", 351 "univpll_d6_d4", 352 "univpll_d5_d2" 353 }; 354 355 static const char * const ssusb_xhci_parents[] = { 356 "clk26m", 357 "univpll_d5_d4", 358 "univpll_d6_d4", 359 "univpll_d5_d2" 360 }; 361 362 static const char * const i2c_parents[] = { 363 "clk26m", 364 "mainpll_d4_d8", 365 "univpll_d5_d4" 366 }; 367 368 static const char * const seninf_parents[] = { 369 "clk26m", 370 "univpll_d4_d4", 371 "univpll_d6_d2", 372 "univpll_d4_d2", 373 "univpll_d7", 374 "univpll_d6", 375 "mmpll_d6", 376 "univpll_d5" 377 }; 378 379 static const char * const tl_parents[] = { 380 "clk26m", 381 "univpll_192m_d2", 382 "mainpll_d6_d4" 383 }; 384 385 static const char * const dxcc_parents[] = { 386 "clk26m", 387 "mainpll_d4_d2", 388 "mainpll_d4_d4", 389 "mainpll_d4_d8" 390 }; 391 392 static const char * const aud_engen1_parents[] = { 393 "clk26m", 394 "apll1_d2", 395 "apll1_d4", 396 "apll1_d8" 397 }; 398 399 static const char * const aud_engen2_parents[] = { 400 "clk26m", 401 "apll2_d2", 402 "apll2_d4", 403 "apll2_d8" 404 }; 405 406 static const char * const aes_ufsfde_parents[] = { 407 "clk26m", 408 "mainpll_d4", 409 "mainpll_d4_d2", 410 "mainpll_d6", 411 "mainpll_d4_d4", 412 "univpll_d4_d2", 413 "univpll_d6" 414 }; 415 416 static const char * const ufs_parents[] = { 417 "clk26m", 418 "mainpll_d4_d4", 419 "mainpll_d4_d8", 420 "univpll_d4_d4", 421 "mainpll_d6_d2", 422 "mainpll_d5_d2", 423 "msdcpll_d2" 424 }; 425 426 static const char * const aud_1_parents[] = { 427 "clk26m", 428 "apll1_ck" 429 }; 430 431 static const char * const aud_2_parents[] = { 432 "clk26m", 433 "apll2_ck" 434 }; 435 436 static const char * const adsp_parents[] = { 437 "clk26m", 438 "mainpll_d6", 439 "mainpll_d5_d2", 440 "univpll_d4_d4", 441 "univpll_d4", 442 "univpll_d6", 443 "ulposc", 444 "adsppll_ck" 445 }; 446 447 static const char * const dpmaif_main_parents[] = { 448 "clk26m", 449 "univpll_d4_d4", 450 "mainpll_d6", 451 "mainpll_d4_d2", 452 "univpll_d4_d2" 453 }; 454 455 static const char * const venc_parents[] = { 456 "clk26m", 457 "mmpll_d7", 458 "mainpll_d6", 459 "univpll_d4_d2", 460 "mainpll_d4_d2", 461 "univpll_d6", 462 "mmpll_d6", 463 "mainpll_d5_d2", 464 "mainpll_d6_d2", 465 "mmpll_d9", 466 "univpll_d4_d4", 467 "mainpll_d4", 468 "univpll_d4", 469 "univpll_d5", 470 "univpll_d5_d2", 471 "mainpll_d5" 472 }; 473 474 static const char * const vdec_parents[] = { 475 "clk26m", 476 "univpll_192m_d2", 477 "univpll_d5_d4", 478 "mainpll_d5", 479 "mainpll_d5_d2", 480 "mmpll_d6_d2", 481 "univpll_d5_d2", 482 "mainpll_d4_d2", 483 "univpll_d4_d2", 484 "univpll_d7", 485 "mmpll_d7", 486 "mmpll_d6", 487 "univpll_d5", 488 "mainpll_d4", 489 "univpll_d4", 490 "univpll_d6" 491 }; 492 493 static const char * const camtm_parents[] = { 494 "clk26m", 495 "univpll_d7", 496 "univpll_d6_d2", 497 "univpll_d4_d2" 498 }; 499 500 static const char * const pwm_parents[] = { 501 "clk26m", 502 "univpll_d4_d8" 503 }; 504 505 static const char * const audio_h_parents[] = { 506 "clk26m", 507 "univpll_d7", 508 "apll1_ck", 509 "apll2_ck" 510 }; 511 512 static const char * const spmi_mst_parents[] = { 513 "clk26m", 514 "csw_f26m_d2", 515 "osc_d8", 516 "osc_d10", 517 "osc_d16", 518 "osc_d20", 519 "clk32k" 520 }; 521 522 static const char * const aes_msdcfde_parents[] = { 523 "clk26m", 524 "mainpll_d4_d2", 525 "mainpll_d6", 526 "mainpll_d4_d4", 527 "univpll_d4_d2", 528 "univpll_d6" 529 }; 530 531 static const char * const sflash_parents[] = { 532 "clk26m", 533 "mainpll_d7_d8", 534 "univpll_d6_d8", 535 "univpll_d5_d8" 536 }; 537 538 static const char * const apll_i2s_m_parents[] = { 539 "aud_1_sel", 540 "aud_2_sel" 541 }; 542 543 /* 544 * CRITICAL CLOCK: 545 * axi_sel is the main bus clock of whole SOC. 546 * spm_sel is the clock of the always-on co-processor. 547 * bus_aximem_sel is clock of the bus that access emi. 548 */ 549 static const struct mtk_mux top_mtk_muxes[] = { 550 /* CLK_CFG_0 */ 551 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", 552 axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0, 553 CLK_IS_CRITICAL), 554 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", 555 spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1, 556 CLK_IS_CRITICAL), 557 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", 558 scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2), 559 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel", 560 bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3, 561 CLK_IS_CRITICAL), 562 /* CLK_CFG_1 */ 563 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel", 564 disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4), 565 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel", 566 mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5), 567 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel", 568 img_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6), 569 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel", 570 img_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7), 571 /* CLK_CFG_2 */ 572 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel", 573 ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8), 574 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel", 575 dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9), 576 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel", 577 cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10), 578 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel", 579 ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11), 580 /* CLK_CFG_4 */ 581 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel", 582 dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16), 583 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", 584 mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18), 585 MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", 586 mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1), 587 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", 588 camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19), 589 /* CLK_CFG_5 */ 590 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel", 591 camtg_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20), 592 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", 593 camtg_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21), 594 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel", 595 camtg_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22), 596 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel", 597 camtg_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23), 598 /* CLK_CFG_6 */ 599 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel", 600 camtg_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24), 601 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", 602 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25), 603 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", 604 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26), 605 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", 606 msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27), 607 /* CLK_CFG_7 */ 608 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 609 msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28), 610 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 611 msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29), 612 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", 613 msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30), 614 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", 615 audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0), 616 /* CLK_CFG_8 */ 617 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 618 aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1), 619 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel", 620 pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2), 621 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", 622 atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3), 623 /* CLK_CFG_9 */ 624 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel", 625 dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5), 626 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel", 627 scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6), 628 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 629 disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7), 630 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel", 631 usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8), 632 /* CLK_CFG_10 */ 633 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 634 ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9), 635 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", 636 i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10), 637 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", 638 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11), 639 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel", 640 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12), 641 /* CLK_CFG_11 */ 642 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel", 643 seninf_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13), 644 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel", 645 seninf_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14), 646 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel", 647 tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15), 648 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", 649 dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16), 650 /* CLK_CFG_12 */ 651 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 652 aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17), 653 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 654 aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18), 655 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel", 656 aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19), 657 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel", 658 ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20), 659 /* CLK_CFG_13 */ 660 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", 661 aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21), 662 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", 663 aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22), 664 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel", 665 adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23), 666 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel", 667 dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24), 668 /* CLK_CFG_14 */ 669 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel", 670 venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25), 671 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", 672 vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26), 673 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", 674 camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27), 675 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", 676 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28), 677 /* CLK_CFG_15 */ 678 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel", 679 audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29), 680 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel", 681 spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30), 682 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel", 683 aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1), 684 /* CLK_CFG_16 */ 685 MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel", 686 sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3), 687 }; 688 689 static struct mtk_composite top_muxes[] = { 690 /* CLK_AUDDIV_0 */ 691 MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s_m_parents, 0x320, 16, 1), 692 MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s_m_parents, 0x320, 17, 1), 693 MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s_m_parents, 0x320, 18, 1), 694 MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s_m_parents, 0x320, 19, 1), 695 MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s_m_parents, 0x320, 20, 1), 696 MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s_m_parents, 0x320, 21, 1), 697 MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s_m_parents, 0x320, 22, 1), 698 MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s_m_parents, 0x320, 23, 1), 699 MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s_m_parents, 0x320, 24, 1), 700 MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s_m_parents, 0x320, 25, 1), 701 /* APLL_DIV */ 702 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0), 703 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8), 704 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16), 705 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24), 706 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0), 707 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8), 708 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16), 709 DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24), 710 DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0), 711 DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8), 712 DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16), 713 }; 714 715 static const struct mtk_gate_regs apmixed_cg_regs = { 716 .set_ofs = 0x14, 717 .clr_ofs = 0x14, 718 .sta_ofs = 0x14, 719 }; 720 721 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 722 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 723 724 static const struct mtk_gate apmixed_clks[] = { 725 GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), 726 }; 727 728 static const struct mtk_gate_regs infra0_cg_regs = { 729 .set_ofs = 0x80, 730 .clr_ofs = 0x84, 731 .sta_ofs = 0x90, 732 }; 733 734 static const struct mtk_gate_regs infra1_cg_regs = { 735 .set_ofs = 0x88, 736 .clr_ofs = 0x8c, 737 .sta_ofs = 0x94, 738 }; 739 740 static const struct mtk_gate_regs infra2_cg_regs = { 741 .set_ofs = 0xa4, 742 .clr_ofs = 0xa8, 743 .sta_ofs = 0xac, 744 }; 745 746 static const struct mtk_gate_regs infra3_cg_regs = { 747 .set_ofs = 0xc0, 748 .clr_ofs = 0xc4, 749 .sta_ofs = 0xc8, 750 }; 751 752 static const struct mtk_gate_regs infra4_cg_regs = { 753 .set_ofs = 0xd0, 754 .clr_ofs = 0xd4, 755 .sta_ofs = 0xd8, 756 }; 757 758 static const struct mtk_gate_regs infra5_cg_regs = { 759 .set_ofs = 0xe0, 760 .clr_ofs = 0xe4, 761 .sta_ofs = 0xe8, 762 }; 763 764 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 765 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 766 767 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \ 768 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \ 769 &mtk_clk_gate_ops_setclr, _flag) 770 771 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 772 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) 773 774 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 775 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 776 777 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \ 778 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \ 779 &mtk_clk_gate_ops_setclr, _flag) 780 781 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 782 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) 783 784 #define GATE_INFRA4(_id, _name, _parent, _shift) \ 785 GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 786 787 #define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \ 788 GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \ 789 &mtk_clk_gate_ops_setclr, _flag) 790 791 #define GATE_INFRA5(_id, _name, _parent, _shift) \ 792 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0) 793 794 /* 795 * CRITICAL CLOCK: 796 * infra_133m and infra_66m are main peripheral bus clocks of SOC. 797 * infra_device_apc and infra_device_apc_sync are for device access permission control module. 798 */ 799 static const struct mtk_gate infra_clks[] = { 800 /* INFRA0 */ 801 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0), 802 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1), 803 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2), 804 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3), 805 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4), 806 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5), 807 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 808 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8), 809 GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9), 810 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 811 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), 812 GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12), 813 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), 814 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), 815 GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15), 816 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16), 817 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17), 818 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18), 819 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19), 820 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), 821 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 822 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 823 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 824 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 825 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), 826 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28), 827 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 828 /* INFRA1 */ 829 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), 830 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2), 831 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4), 832 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5), 833 GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6), 834 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 835 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 836 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10), 837 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 838 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), 839 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), 840 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14), 841 GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15), 842 GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16), 843 GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17), 844 GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18), 845 GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19), 846 GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL), 847 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 848 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), 849 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 850 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 851 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), 852 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), 853 GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29), 854 GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30), 855 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31), 856 /* INFRA2 */ 857 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0), 858 GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1), 859 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2), 860 GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3), 861 GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4), 862 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5), 863 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), 864 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), 865 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), 866 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), 867 GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11), 868 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12), 869 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13), 870 GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14), 871 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), 872 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), 873 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), 874 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), 875 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), 876 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), 877 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), 878 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), 879 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), 880 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), 881 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27), 882 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28), 883 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29), 884 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30), 885 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31), 886 /* INFRA3 */ 887 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), 888 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), 889 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), 890 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), 891 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), 892 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7), 893 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8), 894 GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9), 895 GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10), 896 GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11), 897 GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14), 898 GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15), 899 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), 900 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), 901 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), 902 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), 903 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20), 904 GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21), 905 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), 906 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), 907 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), 908 GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25, 909 CLK_IS_CRITICAL), 910 GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26), 911 GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27), 912 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28), 913 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29), 914 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30), 915 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31), 916 /* INFRA4 */ 917 GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31), 918 /* INFRA5 */ 919 GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL), 920 GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL), 921 GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2), 922 GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3), 923 GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4), 924 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5), 925 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6), 926 GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30), 927 GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31), 928 }; 929 930 static const struct mtk_gate_regs peri_cg_regs = { 931 .set_ofs = 0x20c, 932 .clr_ofs = 0x20c, 933 .sta_ofs = 0x20c, 934 }; 935 936 #define GATE_PERI(_id, _name, _parent, _shift) \ 937 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 938 939 static const struct mtk_gate peri_clks[] = { 940 GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31), 941 }; 942 943 static const struct mtk_gate_regs top_cg_regs = { 944 .set_ofs = 0x150, 945 .clr_ofs = 0x150, 946 .sta_ofs = 0x150, 947 }; 948 949 #define GATE_TOP(_id, _name, _parent, _shift) \ 950 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 951 952 static const struct mtk_gate top_clks[] = { 953 GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24), 954 GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), 955 }; 956 957 static u16 infra_ao_rst_ofs[] = { 958 INFRA_RST0_SET_OFFSET, 959 INFRA_RST1_SET_OFFSET, 960 INFRA_RST2_SET_OFFSET, 961 INFRA_RST3_SET_OFFSET, 962 INFRA_RST4_SET_OFFSET, 963 }; 964 965 static u16 infra_ao_idx_map[] = { 966 [MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, 967 [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15, 968 [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, 969 [MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1, 970 [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12, 971 }; 972 973 static const struct mtk_clk_rst_desc clk_rst_desc = { 974 .version = MTK_RST_SET_CLR, 975 .rst_bank_ofs = infra_ao_rst_ofs, 976 .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), 977 .rst_idx_map = infra_ao_idx_map, 978 .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), 979 }; 980 981 #define MT8192_PLL_FMAX (3800UL * MHZ) 982 #define MT8192_PLL_FMIN (1500UL * MHZ) 983 #define MT8192_INTEGER_BITS 8 984 985 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 986 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 987 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 988 _pcw_reg, _pcw_shift, _pcw_chg_reg, \ 989 _en_reg, _pll_en_bit) { \ 990 .id = _id, \ 991 .name = _name, \ 992 .reg = _reg, \ 993 .pwr_reg = _pwr_reg, \ 994 .en_mask = _en_mask, \ 995 .flags = _flags, \ 996 .rst_bar_mask = _rst_bar_mask, \ 997 .fmax = MT8192_PLL_FMAX, \ 998 .fmin = MT8192_PLL_FMIN, \ 999 .pcwbits = _pcwbits, \ 1000 .pcwibits = MT8192_INTEGER_BITS, \ 1001 .pd_reg = _pd_reg, \ 1002 .pd_shift = _pd_shift, \ 1003 .tuner_reg = _tuner_reg, \ 1004 .tuner_en_reg = _tuner_en_reg, \ 1005 .tuner_en_bit = _tuner_en_bit, \ 1006 .pcw_reg = _pcw_reg, \ 1007 .pcw_shift = _pcw_shift, \ 1008 .pcw_chg_reg = _pcw_chg_reg, \ 1009 .en_reg = _en_reg, \ 1010 .pll_en_bit = _pll_en_bit, \ 1011 } 1012 1013 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1014 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1015 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1016 _pcw_reg, _pcw_shift) \ 1017 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1018 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1019 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1020 _pcw_reg, _pcw_shift, 0, 0, 0) 1021 1022 static const struct mtk_pll_data plls[] = { 1023 PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000, 1024 HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), 1025 PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000, 1026 HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), 1027 PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, 1028 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), 1029 PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000, 1030 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), 1031 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000, 1032 HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), 1033 PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000, 1034 HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), 1035 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000, 1036 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), 1037 PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000, 1038 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), 1039 PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000, 1040 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), 1041 PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, 1042 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), 1043 }; 1044 1045 /* Register mux notifier for MFG mux */ 1046 static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) 1047 { 1048 struct mtk_mux_nb *mfg_mux_nb; 1049 int i; 1050 1051 mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); 1052 if (!mfg_mux_nb) 1053 return -ENOMEM; 1054 1055 for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++) 1056 if (top_mtk_muxes[i].id == CLK_TOP_MFG_PLL_SEL) 1057 break; 1058 if (i == ARRAY_SIZE(top_mtk_muxes)) 1059 return -EINVAL; 1060 1061 mfg_mux_nb->ops = top_mtk_muxes[i].ops; 1062 mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */ 1063 1064 return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); 1065 } 1066 1067 static int clk_mt8192_apmixed_probe(struct platform_device *pdev) 1068 { 1069 struct clk_hw_onecell_data *clk_data; 1070 struct device_node *node = pdev->dev.of_node; 1071 int r; 1072 1073 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1074 if (!clk_data) 1075 return -ENOMEM; 1076 1077 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1078 r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, 1079 ARRAY_SIZE(apmixed_clks), clk_data); 1080 if (r) 1081 goto free_clk_data; 1082 1083 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1084 if (r) 1085 goto unregister_gates; 1086 1087 return r; 1088 1089 unregister_gates: 1090 mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); 1091 free_clk_data: 1092 mtk_free_clk_data(clk_data); 1093 return r; 1094 } 1095 1096 static const struct of_device_id of_match_clk_mt8192[] = { 1097 { 1098 .compatible = "mediatek,mt8192-apmixedsys", 1099 .data = clk_mt8192_apmixed_probe, 1100 }, { 1101 /* sentinel */ 1102 } 1103 }; 1104 1105 static int clk_mt8192_probe(struct platform_device *pdev) 1106 { 1107 int (*clk_probe)(struct platform_device *pdev); 1108 int r; 1109 1110 clk_probe = of_device_get_match_data(&pdev->dev); 1111 if (!clk_probe) 1112 return -EINVAL; 1113 1114 r = clk_probe(pdev); 1115 if (r) 1116 dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); 1117 1118 return r; 1119 } 1120 1121 static const struct mtk_clk_desc infra_desc = { 1122 .clks = infra_clks, 1123 .num_clks = ARRAY_SIZE(infra_clks), 1124 .rst_desc = &clk_rst_desc, 1125 }; 1126 1127 static const struct mtk_clk_desc peri_desc = { 1128 .clks = peri_clks, 1129 .num_clks = ARRAY_SIZE(peri_clks), 1130 }; 1131 1132 static const struct mtk_clk_desc topck_desc = { 1133 .fixed_clks = top_fixed_clks, 1134 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 1135 .factor_clks = top_divs, 1136 .num_factor_clks = ARRAY_SIZE(top_divs), 1137 .mux_clks = top_mtk_muxes, 1138 .num_mux_clks = ARRAY_SIZE(top_mtk_muxes), 1139 .composite_clks = top_muxes, 1140 .num_composite_clks = ARRAY_SIZE(top_muxes), 1141 .clks = top_clks, 1142 .num_clks = ARRAY_SIZE(top_clks), 1143 .clk_lock = &mt8192_clk_lock, 1144 .clk_notifier_func = clk_mt8192_reg_mfg_mux_notifier, 1145 .mfg_clk_idx = CLK_TOP_MFG_PLL_SEL, 1146 }; 1147 1148 static const struct of_device_id of_match_clk_mt8192_simple[] = { 1149 { .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc }, 1150 { .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc }, 1151 { .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc }, 1152 { /* sentinel */ } 1153 }; 1154 1155 static struct platform_driver clk_mt8192_simple_drv = { 1156 .probe = mtk_clk_simple_probe, 1157 .remove = mtk_clk_simple_remove, 1158 .driver = { 1159 .name = "clk-mt8192-simple", 1160 .of_match_table = of_match_clk_mt8192_simple, 1161 }, 1162 }; 1163 1164 static struct platform_driver clk_mt8192_drv = { 1165 .probe = clk_mt8192_probe, 1166 .driver = { 1167 .name = "clk-mt8192", 1168 .of_match_table = of_match_clk_mt8192, 1169 }, 1170 }; 1171 1172 static int __init clk_mt8192_init(void) 1173 { 1174 int ret = platform_driver_register(&clk_mt8192_drv); 1175 1176 if (ret) 1177 return ret; 1178 return platform_driver_register(&clk_mt8192_simple_drv); 1179 } 1180 1181 arch_initcall(clk_mt8192_init); 1182