125f3d97eSChun-Jie Chen // SPDX-License-Identifier: GPL-2.0-only 225f3d97eSChun-Jie Chen // 325f3d97eSChun-Jie Chen // Copyright (c) 2021 MediaTek Inc. 425f3d97eSChun-Jie Chen // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 525f3d97eSChun-Jie Chen 625f3d97eSChun-Jie Chen #include <linux/clk-provider.h> 7*a96cbb14SRob Herring #include <linux/mod_devicetable.h> 825f3d97eSChun-Jie Chen #include <linux/platform_device.h> 925f3d97eSChun-Jie Chen 1025f3d97eSChun-Jie Chen #include "clk-mtk.h" 1125f3d97eSChun-Jie Chen #include "clk-gate.h" 1225f3d97eSChun-Jie Chen 1325f3d97eSChun-Jie Chen #include <dt-bindings/clock/mt8192-clk.h> 1425f3d97eSChun-Jie Chen 1525f3d97eSChun-Jie Chen static const struct mtk_gate_regs vdec0_cg_regs = { 1625f3d97eSChun-Jie Chen .set_ofs = 0x0, 1725f3d97eSChun-Jie Chen .clr_ofs = 0x4, 1825f3d97eSChun-Jie Chen .sta_ofs = 0x0, 1925f3d97eSChun-Jie Chen }; 2025f3d97eSChun-Jie Chen 2125f3d97eSChun-Jie Chen static const struct mtk_gate_regs vdec1_cg_regs = { 2225f3d97eSChun-Jie Chen .set_ofs = 0x200, 2325f3d97eSChun-Jie Chen .clr_ofs = 0x204, 2425f3d97eSChun-Jie Chen .sta_ofs = 0x200, 2525f3d97eSChun-Jie Chen }; 2625f3d97eSChun-Jie Chen 2725f3d97eSChun-Jie Chen static const struct mtk_gate_regs vdec2_cg_regs = { 2825f3d97eSChun-Jie Chen .set_ofs = 0x8, 2925f3d97eSChun-Jie Chen .clr_ofs = 0xc, 3025f3d97eSChun-Jie Chen .sta_ofs = 0x8, 3125f3d97eSChun-Jie Chen }; 3225f3d97eSChun-Jie Chen 3325f3d97eSChun-Jie Chen #define GATE_VDEC0(_id, _name, _parent, _shift) \ 3425f3d97eSChun-Jie Chen GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 3525f3d97eSChun-Jie Chen 3625f3d97eSChun-Jie Chen #define GATE_VDEC1(_id, _name, _parent, _shift) \ 3725f3d97eSChun-Jie Chen GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 3825f3d97eSChun-Jie Chen 3925f3d97eSChun-Jie Chen #define GATE_VDEC2(_id, _name, _parent, _shift) \ 4025f3d97eSChun-Jie Chen GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 4125f3d97eSChun-Jie Chen 4225f3d97eSChun-Jie Chen static const struct mtk_gate vdec_clks[] = { 4325f3d97eSChun-Jie Chen /* VDEC0 */ 4425f3d97eSChun-Jie Chen GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0), 4525f3d97eSChun-Jie Chen GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4), 4625f3d97eSChun-Jie Chen /* VDEC1 */ 4725f3d97eSChun-Jie Chen GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0), 4825f3d97eSChun-Jie Chen GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4), 4925f3d97eSChun-Jie Chen /* VDEC2 */ 5025f3d97eSChun-Jie Chen GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0), 5125f3d97eSChun-Jie Chen }; 5225f3d97eSChun-Jie Chen 5325f3d97eSChun-Jie Chen static const struct mtk_gate vdec_soc_clks[] = { 5425f3d97eSChun-Jie Chen /* VDEC_SOC0 */ 5525f3d97eSChun-Jie Chen GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0), 5625f3d97eSChun-Jie Chen GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4), 5725f3d97eSChun-Jie Chen /* VDEC_SOC1 */ 5825f3d97eSChun-Jie Chen GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0), 5925f3d97eSChun-Jie Chen GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4), 6025f3d97eSChun-Jie Chen /* VDEC_SOC2 */ 6125f3d97eSChun-Jie Chen GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0), 6225f3d97eSChun-Jie Chen }; 6325f3d97eSChun-Jie Chen 6425f3d97eSChun-Jie Chen static const struct mtk_clk_desc vdec_desc = { 6525f3d97eSChun-Jie Chen .clks = vdec_clks, 6625f3d97eSChun-Jie Chen .num_clks = ARRAY_SIZE(vdec_clks), 6725f3d97eSChun-Jie Chen }; 6825f3d97eSChun-Jie Chen 6925f3d97eSChun-Jie Chen static const struct mtk_clk_desc vdec_soc_desc = { 7025f3d97eSChun-Jie Chen .clks = vdec_soc_clks, 7125f3d97eSChun-Jie Chen .num_clks = ARRAY_SIZE(vdec_soc_clks), 7225f3d97eSChun-Jie Chen }; 7325f3d97eSChun-Jie Chen 7425f3d97eSChun-Jie Chen static const struct of_device_id of_match_clk_mt8192_vdec[] = { 7525f3d97eSChun-Jie Chen { 7625f3d97eSChun-Jie Chen .compatible = "mediatek,mt8192-vdecsys", 7725f3d97eSChun-Jie Chen .data = &vdec_desc, 7825f3d97eSChun-Jie Chen }, { 7925f3d97eSChun-Jie Chen .compatible = "mediatek,mt8192-vdecsys_soc", 8025f3d97eSChun-Jie Chen .data = &vdec_soc_desc, 8125f3d97eSChun-Jie Chen }, { 8225f3d97eSChun-Jie Chen /* sentinel */ 8325f3d97eSChun-Jie Chen } 8425f3d97eSChun-Jie Chen }; 8565c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_vdec); 8625f3d97eSChun-Jie Chen 8725f3d97eSChun-Jie Chen static struct platform_driver clk_mt8192_vdec_drv = { 8825f3d97eSChun-Jie Chen .probe = mtk_clk_simple_probe, 8961ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 9025f3d97eSChun-Jie Chen .driver = { 9125f3d97eSChun-Jie Chen .name = "clk-mt8192-vdec", 9225f3d97eSChun-Jie Chen .of_match_table = of_match_clk_mt8192_vdec, 9325f3d97eSChun-Jie Chen }, 9425f3d97eSChun-Jie Chen }; 95164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt8192_vdec_drv); 96a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 97