1*b565d41fSChun-Jie Chen // SPDX-License-Identifier: GPL-2.0-only 2*b565d41fSChun-Jie Chen // 3*b565d41fSChun-Jie Chen // Copyright (c) 2021 MediaTek Inc. 4*b565d41fSChun-Jie Chen // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5*b565d41fSChun-Jie Chen 6*b565d41fSChun-Jie Chen #include <linux/clk-provider.h> 7*b565d41fSChun-Jie Chen #include <linux/of_device.h> 8*b565d41fSChun-Jie Chen #include <linux/platform_device.h> 9*b565d41fSChun-Jie Chen 10*b565d41fSChun-Jie Chen #include "clk-mtk.h" 11*b565d41fSChun-Jie Chen #include "clk-gate.h" 12*b565d41fSChun-Jie Chen 13*b565d41fSChun-Jie Chen #include <dt-bindings/clock/mt8192-clk.h> 14*b565d41fSChun-Jie Chen 15*b565d41fSChun-Jie Chen static const struct mtk_gate_regs mdp0_cg_regs = { 16*b565d41fSChun-Jie Chen .set_ofs = 0x104, 17*b565d41fSChun-Jie Chen .clr_ofs = 0x108, 18*b565d41fSChun-Jie Chen .sta_ofs = 0x100, 19*b565d41fSChun-Jie Chen }; 20*b565d41fSChun-Jie Chen 21*b565d41fSChun-Jie Chen static const struct mtk_gate_regs mdp1_cg_regs = { 22*b565d41fSChun-Jie Chen .set_ofs = 0x124, 23*b565d41fSChun-Jie Chen .clr_ofs = 0x128, 24*b565d41fSChun-Jie Chen .sta_ofs = 0x120, 25*b565d41fSChun-Jie Chen }; 26*b565d41fSChun-Jie Chen 27*b565d41fSChun-Jie Chen #define GATE_MDP0(_id, _name, _parent, _shift) \ 28*b565d41fSChun-Jie Chen GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 29*b565d41fSChun-Jie Chen 30*b565d41fSChun-Jie Chen #define GATE_MDP1(_id, _name, _parent, _shift) \ 31*b565d41fSChun-Jie Chen GATE_MTK(_id, _name, _parent, &mdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 32*b565d41fSChun-Jie Chen 33*b565d41fSChun-Jie Chen static const struct mtk_gate mdp_clks[] = { 34*b565d41fSChun-Jie Chen /* MDP0 */ 35*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_RDMA0, "mdp_mdp_rdma0", "mdp_sel", 0), 36*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_TDSHP0, "mdp_mdp_tdshp0", "mdp_sel", 1), 37*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "mdp_sel", 2), 38*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "mdp_sel", 3), 39*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_RDMA1, "mdp_mdp_rdma1", "mdp_sel", 4), 40*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_TDSHP1, "mdp_mdp_tdshp1", "mdp_sel", 5), 41*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp_sel", 6), 42*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp_sel", 7), 43*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_WROT0, "mdp_mdp_wrot0", "mdp_sel", 8), 44*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_RSZ0, "mdp_mdp_rsz0", "mdp_sel", 9), 45*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_HDR0, "mdp_mdp_hdr0", "mdp_sel", 10), 46*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mdp_mutex0", "mdp_sel", 11), 47*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_WROT1, "mdp_mdp_wrot1", "mdp_sel", 12), 48*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_RSZ1, "mdp_mdp_rsz1", "mdp_sel", 13), 49*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_HDR1, "mdp_mdp_hdr1", "mdp_sel", 14), 50*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0", "mdp_sel", 15), 51*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_AAL0, "mdp_mdp_aal0", "mdp_sel", 16), 52*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_AAL1, "mdp_mdp_aal1", "mdp_sel", 17), 53*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_COLOR0, "mdp_mdp_color0", "mdp_sel", 18), 54*b565d41fSChun-Jie Chen GATE_MDP0(CLK_MDP_COLOR1, "mdp_mdp_color1", "mdp_sel", 19), 55*b565d41fSChun-Jie Chen /* MDP1 */ 56*b565d41fSChun-Jie Chen GATE_MDP1(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_relay0_async0", "mdp_sel", 0), 57*b565d41fSChun-Jie Chen GATE_MDP1(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_relay1_async1", "mdp_sel", 8), 58*b565d41fSChun-Jie Chen }; 59*b565d41fSChun-Jie Chen 60*b565d41fSChun-Jie Chen static const struct mtk_clk_desc mdp_desc = { 61*b565d41fSChun-Jie Chen .clks = mdp_clks, 62*b565d41fSChun-Jie Chen .num_clks = ARRAY_SIZE(mdp_clks), 63*b565d41fSChun-Jie Chen }; 64*b565d41fSChun-Jie Chen 65*b565d41fSChun-Jie Chen static const struct of_device_id of_match_clk_mt8192_mdp[] = { 66*b565d41fSChun-Jie Chen { 67*b565d41fSChun-Jie Chen .compatible = "mediatek,mt8192-mdpsys", 68*b565d41fSChun-Jie Chen .data = &mdp_desc, 69*b565d41fSChun-Jie Chen }, { 70*b565d41fSChun-Jie Chen /* sentinel */ 71*b565d41fSChun-Jie Chen } 72*b565d41fSChun-Jie Chen }; 73*b565d41fSChun-Jie Chen 74*b565d41fSChun-Jie Chen static struct platform_driver clk_mt8192_mdp_drv = { 75*b565d41fSChun-Jie Chen .probe = mtk_clk_simple_probe, 76*b565d41fSChun-Jie Chen .driver = { 77*b565d41fSChun-Jie Chen .name = "clk-mt8192-mdp", 78*b565d41fSChun-Jie Chen .of_match_table = of_match_clk_mt8192_mdp, 79*b565d41fSChun-Jie Chen }, 80*b565d41fSChun-Jie Chen }; 81*b565d41fSChun-Jie Chen 82*b565d41fSChun-Jie Chen builtin_platform_driver(clk_mt8192_mdp_drv); 83