1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk-provider.h> 7 #include <linux/of_platform.h> 8 #include <linux/platform_device.h> 9 10 #include "clk-mtk.h" 11 #include "clk-gate.h" 12 13 #include <dt-bindings/clock/mt8192-clk.h> 14 15 static const struct mtk_gate_regs aud0_cg_regs = { 16 .set_ofs = 0x0, 17 .clr_ofs = 0x0, 18 .sta_ofs = 0x0, 19 }; 20 21 static const struct mtk_gate_regs aud1_cg_regs = { 22 .set_ofs = 0x4, 23 .clr_ofs = 0x4, 24 .sta_ofs = 0x4, 25 }; 26 27 static const struct mtk_gate_regs aud2_cg_regs = { 28 .set_ofs = 0x8, 29 .clr_ofs = 0x8, 30 .sta_ofs = 0x8, 31 }; 32 33 #define GATE_AUD0(_id, _name, _parent, _shift) \ 34 GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 35 36 #define GATE_AUD1(_id, _name, _parent, _shift) \ 37 GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 38 39 #define GATE_AUD2(_id, _name, _parent, _shift) \ 40 GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 41 42 static const struct mtk_gate aud_clks[] = { 43 /* AUD0 */ 44 GATE_AUD0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2), 45 GATE_AUD0(CLK_AUD_22M, "aud_22m", "aud_engen1_sel", 8), 46 GATE_AUD0(CLK_AUD_24M, "aud_24m", "aud_engen2_sel", 9), 47 GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "aud_engen2_sel", 18), 48 GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "aud_engen1_sel", 19), 49 GATE_AUD0(CLK_AUD_TDM, "aud_tdm", "aud_1_sel", 20), 50 GATE_AUD0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24), 51 GATE_AUD0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25), 52 GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "audio_sel", 26), 53 GATE_AUD0(CLK_AUD_TML, "aud_tml", "audio_sel", 27), 54 GATE_AUD0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28), 55 /* AUD1 */ 56 GATE_AUD1(CLK_AUD_I2S1_B, "aud_i2s1_b", "audio_sel", 4), 57 GATE_AUD1(CLK_AUD_I2S2_B, "aud_i2s2_b", "audio_sel", 5), 58 GATE_AUD1(CLK_AUD_I2S3_B, "aud_i2s3_b", "audio_sel", 6), 59 GATE_AUD1(CLK_AUD_I2S4_B, "aud_i2s4_b", "audio_sel", 7), 60 GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "audio_sel", 12), 61 GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "audio_sel", 13), 62 GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "audio_sel", 14), 63 GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 15), 64 GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 16), 65 GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "audio_h_sel", 17), 66 GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "audio_sel", 20), 67 GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 21), 68 GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel", 28), 69 GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "audio_sel", 29), 70 GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "audio_sel", 30), 71 GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "audio_h_sel", 31), 72 /* AUD2 */ 73 GATE_AUD2(CLK_AUD_I2S5_B, "aud_i2s5_b", "audio_sel", 0), 74 GATE_AUD2(CLK_AUD_I2S6_B, "aud_i2s6_b", "audio_sel", 1), 75 GATE_AUD2(CLK_AUD_I2S7_B, "aud_i2s7_b", "audio_sel", 2), 76 GATE_AUD2(CLK_AUD_I2S8_B, "aud_i2s8_b", "audio_sel", 3), 77 GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4), 78 }; 79 80 static const struct mtk_clk_desc aud_desc = { 81 .clks = aud_clks, 82 .num_clks = ARRAY_SIZE(aud_clks), 83 }; 84 85 static int clk_mt8192_aud_probe(struct platform_device *pdev) 86 { 87 int r; 88 89 r = mtk_clk_simple_probe(pdev); 90 if (r) 91 return r; 92 93 r = devm_of_platform_populate(&pdev->dev); 94 if (r) 95 mtk_clk_simple_remove(pdev); 96 97 return r; 98 } 99 100 static int clk_mt8192_aud_remove(struct platform_device *pdev) 101 { 102 of_platform_depopulate(&pdev->dev); 103 return mtk_clk_simple_remove(pdev); 104 } 105 106 static const struct of_device_id of_match_clk_mt8192_aud[] = { 107 { .compatible = "mediatek,mt8192-audsys", .data = &aud_desc }, 108 { /* sentinel */ } 109 }; 110 MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_aud); 111 112 static struct platform_driver clk_mt8192_aud_drv = { 113 .probe = clk_mt8192_aud_probe, 114 .remove = clk_mt8192_aud_remove, 115 .driver = { 116 .name = "clk-mt8192-aud", 117 .of_match_table = of_match_clk_mt8192_aud, 118 }, 119 }; 120 module_platform_driver(clk_mt8192_aud_drv); 121 MODULE_LICENSE("GPL"); 122