1*f61e8348SChun-Jie Chen // SPDX-License-Identifier: GPL-2.0-only 2*f61e8348SChun-Jie Chen // 3*f61e8348SChun-Jie Chen // Copyright (c) 2021 MediaTek Inc. 4*f61e8348SChun-Jie Chen // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5*f61e8348SChun-Jie Chen 6*f61e8348SChun-Jie Chen #include <linux/clk-provider.h> 7*f61e8348SChun-Jie Chen #include <linux/of_platform.h> 8*f61e8348SChun-Jie Chen #include <linux/platform_device.h> 9*f61e8348SChun-Jie Chen 10*f61e8348SChun-Jie Chen #include "clk-mtk.h" 11*f61e8348SChun-Jie Chen #include "clk-gate.h" 12*f61e8348SChun-Jie Chen 13*f61e8348SChun-Jie Chen #include <dt-bindings/clock/mt8192-clk.h> 14*f61e8348SChun-Jie Chen 15*f61e8348SChun-Jie Chen static const struct mtk_gate_regs aud0_cg_regs = { 16*f61e8348SChun-Jie Chen .set_ofs = 0x0, 17*f61e8348SChun-Jie Chen .clr_ofs = 0x0, 18*f61e8348SChun-Jie Chen .sta_ofs = 0x0, 19*f61e8348SChun-Jie Chen }; 20*f61e8348SChun-Jie Chen 21*f61e8348SChun-Jie Chen static const struct mtk_gate_regs aud1_cg_regs = { 22*f61e8348SChun-Jie Chen .set_ofs = 0x4, 23*f61e8348SChun-Jie Chen .clr_ofs = 0x4, 24*f61e8348SChun-Jie Chen .sta_ofs = 0x4, 25*f61e8348SChun-Jie Chen }; 26*f61e8348SChun-Jie Chen 27*f61e8348SChun-Jie Chen static const struct mtk_gate_regs aud2_cg_regs = { 28*f61e8348SChun-Jie Chen .set_ofs = 0x8, 29*f61e8348SChun-Jie Chen .clr_ofs = 0x8, 30*f61e8348SChun-Jie Chen .sta_ofs = 0x8, 31*f61e8348SChun-Jie Chen }; 32*f61e8348SChun-Jie Chen 33*f61e8348SChun-Jie Chen #define GATE_AUD0(_id, _name, _parent, _shift) \ 34*f61e8348SChun-Jie Chen GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 35*f61e8348SChun-Jie Chen 36*f61e8348SChun-Jie Chen #define GATE_AUD1(_id, _name, _parent, _shift) \ 37*f61e8348SChun-Jie Chen GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 38*f61e8348SChun-Jie Chen 39*f61e8348SChun-Jie Chen #define GATE_AUD2(_id, _name, _parent, _shift) \ 40*f61e8348SChun-Jie Chen GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 41*f61e8348SChun-Jie Chen 42*f61e8348SChun-Jie Chen static const struct mtk_gate aud_clks[] = { 43*f61e8348SChun-Jie Chen /* AUD0 */ 44*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2), 45*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_22M, "aud_22m", "aud_engen1_sel", 8), 46*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_24M, "aud_24m", "aud_engen2_sel", 9), 47*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "aud_engen2_sel", 18), 48*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "aud_engen1_sel", 19), 49*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_TDM, "aud_tdm", "aud_1_sel", 20), 50*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24), 51*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25), 52*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "audio_sel", 26), 53*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_TML, "aud_tml", "audio_sel", 27), 54*f61e8348SChun-Jie Chen GATE_AUD0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28), 55*f61e8348SChun-Jie Chen /* AUD1 */ 56*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_I2S1_B, "aud_i2s1_b", "audio_sel", 4), 57*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_I2S2_B, "aud_i2s2_b", "audio_sel", 5), 58*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_I2S3_B, "aud_i2s3_b", "audio_sel", 6), 59*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_I2S4_B, "aud_i2s4_b", "audio_sel", 7), 60*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "audio_sel", 12), 61*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "audio_sel", 13), 62*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "audio_sel", 14), 63*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 15), 64*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 16), 65*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "audio_h_sel", 17), 66*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "audio_sel", 20), 67*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 21), 68*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel", 28), 69*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "audio_sel", 29), 70*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "audio_sel", 30), 71*f61e8348SChun-Jie Chen GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "audio_h_sel", 31), 72*f61e8348SChun-Jie Chen /* AUD2 */ 73*f61e8348SChun-Jie Chen GATE_AUD2(CLK_AUD_I2S5_B, "aud_i2s5_b", "audio_sel", 0), 74*f61e8348SChun-Jie Chen GATE_AUD2(CLK_AUD_I2S6_B, "aud_i2s6_b", "audio_sel", 1), 75*f61e8348SChun-Jie Chen GATE_AUD2(CLK_AUD_I2S7_B, "aud_i2s7_b", "audio_sel", 2), 76*f61e8348SChun-Jie Chen GATE_AUD2(CLK_AUD_I2S8_B, "aud_i2s8_b", "audio_sel", 3), 77*f61e8348SChun-Jie Chen GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4), 78*f61e8348SChun-Jie Chen }; 79*f61e8348SChun-Jie Chen 80*f61e8348SChun-Jie Chen static int clk_mt8192_aud_probe(struct platform_device *pdev) 81*f61e8348SChun-Jie Chen { 82*f61e8348SChun-Jie Chen struct clk_onecell_data *clk_data; 83*f61e8348SChun-Jie Chen struct device_node *node = pdev->dev.of_node; 84*f61e8348SChun-Jie Chen int r; 85*f61e8348SChun-Jie Chen 86*f61e8348SChun-Jie Chen clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); 87*f61e8348SChun-Jie Chen if (!clk_data) 88*f61e8348SChun-Jie Chen return -ENOMEM; 89*f61e8348SChun-Jie Chen 90*f61e8348SChun-Jie Chen r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data); 91*f61e8348SChun-Jie Chen if (r) 92*f61e8348SChun-Jie Chen return r; 93*f61e8348SChun-Jie Chen 94*f61e8348SChun-Jie Chen r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 95*f61e8348SChun-Jie Chen if (r) 96*f61e8348SChun-Jie Chen return r; 97*f61e8348SChun-Jie Chen 98*f61e8348SChun-Jie Chen r = devm_of_platform_populate(&pdev->dev); 99*f61e8348SChun-Jie Chen if (r) 100*f61e8348SChun-Jie Chen of_clk_del_provider(node); 101*f61e8348SChun-Jie Chen 102*f61e8348SChun-Jie Chen return r; 103*f61e8348SChun-Jie Chen } 104*f61e8348SChun-Jie Chen 105*f61e8348SChun-Jie Chen static const struct of_device_id of_match_clk_mt8192_aud[] = { 106*f61e8348SChun-Jie Chen { .compatible = "mediatek,mt8192-audsys", }, 107*f61e8348SChun-Jie Chen {} 108*f61e8348SChun-Jie Chen }; 109*f61e8348SChun-Jie Chen 110*f61e8348SChun-Jie Chen static struct platform_driver clk_mt8192_aud_drv = { 111*f61e8348SChun-Jie Chen .probe = clk_mt8192_aud_probe, 112*f61e8348SChun-Jie Chen .driver = { 113*f61e8348SChun-Jie Chen .name = "clk-mt8192-aud", 114*f61e8348SChun-Jie Chen .of_match_table = of_match_clk_mt8192_aud, 115*f61e8348SChun-Jie Chen }, 116*f61e8348SChun-Jie Chen }; 117*f61e8348SChun-Jie Chen 118*f61e8348SChun-Jie Chen builtin_platform_driver(clk_mt8192_aud_drv); 119