1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 * Copyright (c) 2023 Collabora Ltd. 6 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 7 */ 8 9 #include <dt-bindings/clock/mt8192-clk.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include "clk-fhctl.h" 13 #include "clk-gate.h" 14 #include "clk-mtk.h" 15 #include "clk-pll.h" 16 #include "clk-pllfh.h" 17 18 static const struct mtk_gate_regs apmixed_cg_regs = { 19 .set_ofs = 0x14, 20 .clr_ofs = 0x14, 21 .sta_ofs = 0x14, 22 }; 23 24 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 25 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 26 27 static const struct mtk_gate apmixed_clks[] = { 28 GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), 29 }; 30 31 #define MT8192_PLL_FMAX (3800UL * MHZ) 32 #define MT8192_PLL_FMIN (1500UL * MHZ) 33 #define MT8192_INTEGER_BITS 8 34 35 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 36 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 37 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 38 _pcw_reg, _pcw_shift, _pcw_chg_reg, \ 39 _en_reg, _pll_en_bit) { \ 40 .id = _id, \ 41 .name = _name, \ 42 .reg = _reg, \ 43 .pwr_reg = _pwr_reg, \ 44 .en_mask = _en_mask, \ 45 .flags = _flags, \ 46 .rst_bar_mask = _rst_bar_mask, \ 47 .fmax = MT8192_PLL_FMAX, \ 48 .fmin = MT8192_PLL_FMIN, \ 49 .pcwbits = _pcwbits, \ 50 .pcwibits = MT8192_INTEGER_BITS, \ 51 .pd_reg = _pd_reg, \ 52 .pd_shift = _pd_shift, \ 53 .tuner_reg = _tuner_reg, \ 54 .tuner_en_reg = _tuner_en_reg, \ 55 .tuner_en_bit = _tuner_en_bit, \ 56 .pcw_reg = _pcw_reg, \ 57 .pcw_shift = _pcw_shift, \ 58 .pcw_chg_reg = _pcw_chg_reg, \ 59 .en_reg = _en_reg, \ 60 .pll_en_bit = _pll_en_bit, \ 61 } 62 63 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 64 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 65 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 66 _pcw_reg, _pcw_shift) \ 67 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 68 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 69 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 70 _pcw_reg, _pcw_shift, 0, 0, 0) 71 72 static const struct mtk_pll_data plls[] = { 73 PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000, 74 HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), 75 PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000, 76 HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), 77 PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, 78 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), 79 PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000, 80 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), 81 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000, 82 HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), 83 PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000, 84 HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), 85 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000, 86 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), 87 PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000, 88 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), 89 PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000, 90 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), 91 PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, 92 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), 93 }; 94 95 enum fh_pll_id { 96 FH_ARMPLL_LL, 97 FH_ARMPLL_BL0, 98 FH_ARMPLL_BL1, 99 FH_ARMPLL_BL2, 100 FH_ARMPLL_BL3, 101 FH_CCIPLL, 102 FH_MFGPLL, 103 FH_MEMPLL, 104 FH_MPLL, 105 FH_MMPLL, 106 FH_MAINPLL, 107 FH_MSDCPLL, 108 FH_ADSPPLL, 109 FH_APUPLL, 110 FH_TVDPLL, 111 FH_NR_FH, 112 }; 113 114 #define FH(_pllid, _fhid, _offset) { \ 115 .data = { \ 116 .pll_id = _pllid, \ 117 .fh_id = _fhid, \ 118 .fh_ver = FHCTL_PLLFH_V2, \ 119 .fhx_offset = _offset, \ 120 .dds_mask = GENMASK(21, 0), \ 121 .slope0_value = 0x6003c97, \ 122 .slope1_value = 0x6003c97, \ 123 .sfstrx_en = BIT(2), \ 124 .frddsx_en = BIT(1), \ 125 .fhctlx_en = BIT(0), \ 126 .tgl_org = BIT(31), \ 127 .dvfs_tri = BIT(31), \ 128 .pcwchg = BIT(31), \ 129 .dt_val = 0x0, \ 130 .df_val = 0x9, \ 131 .updnlmt_shft = 16, \ 132 .msk_frddsx_dys = GENMASK(23, 20), \ 133 .msk_frddsx_dts = GENMASK(19, 16), \ 134 }, \ 135 } 136 137 static struct mtk_pllfh_data pllfhs[] = { 138 FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), 139 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), 140 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), 141 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), 142 FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c), 143 FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154), 144 }; 145 146 static const struct of_device_id of_match_clk_mt8192_apmixed[] = { 147 { .compatible = "mediatek,mt8192-apmixedsys" }, 148 { /* sentinel */ } 149 }; 150 MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_apmixed); 151 152 static int clk_mt8192_apmixed_probe(struct platform_device *pdev) 153 { 154 struct clk_hw_onecell_data *clk_data; 155 struct device_node *node = pdev->dev.of_node; 156 const u8 *fhctl_node = "mediatek,mt8192-fhctl"; 157 int r; 158 159 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 160 if (!clk_data) 161 return -ENOMEM; 162 163 fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); 164 165 r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), 166 pllfhs, ARRAY_SIZE(pllfhs), clk_data); 167 if (r) 168 goto free_clk_data; 169 170 r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, 171 ARRAY_SIZE(apmixed_clks), clk_data); 172 if (r) 173 goto unregister_plls; 174 175 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 176 if (r) 177 goto unregister_gates; 178 179 return r; 180 181 unregister_gates: 182 mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); 183 unregister_plls: 184 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, 185 ARRAY_SIZE(pllfhs), clk_data); 186 free_clk_data: 187 mtk_free_clk_data(clk_data); 188 return r; 189 } 190 191 static void clk_mt8192_apmixed_remove(struct platform_device *pdev) 192 { 193 struct device_node *node = pdev->dev.of_node; 194 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); 195 196 of_clk_del_provider(node); 197 mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); 198 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, 199 ARRAY_SIZE(pllfhs), clk_data); 200 mtk_free_clk_data(clk_data); 201 } 202 203 static struct platform_driver clk_mt8192_apmixed_drv = { 204 .driver = { 205 .name = "clk-mt8192-apmixed", 206 .of_match_table = of_match_clk_mt8192_apmixed, 207 }, 208 .probe = clk_mt8192_apmixed_probe, 209 .remove_new = clk_mt8192_apmixed_remove, 210 }; 211 module_platform_driver(clk_mt8192_apmixed_drv); 212 MODULE_DESCRIPTION("MediaTek MT8192 apmixed clocks driver"); 213 MODULE_LICENSE("GPL"); 214