1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Garmin Chang <garmin.chang@mediatek.com> 5 */ 6 7 #include <dt-bindings/clock/mediatek,mt8188-clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/platform_device.h> 10 11 #include "clk-gate.h" 12 #include "clk-mtk.h" 13 14 static const struct mtk_gate_regs vpp0_0_cg_regs = { 15 .set_ofs = 0x24, 16 .clr_ofs = 0x28, 17 .sta_ofs = 0x20, 18 }; 19 20 static const struct mtk_gate_regs vpp0_1_cg_regs = { 21 .set_ofs = 0x30, 22 .clr_ofs = 0x34, 23 .sta_ofs = 0x2c, 24 }; 25 26 static const struct mtk_gate_regs vpp0_2_cg_regs = { 27 .set_ofs = 0x3c, 28 .clr_ofs = 0x40, 29 .sta_ofs = 0x38, 30 }; 31 32 #define GATE_VPP0_0(_id, _name, _parent, _shift) \ 33 GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 34 35 #define GATE_VPP0_1(_id, _name, _parent, _shift) \ 36 GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 37 38 #define GATE_VPP0_2(_id, _name, _parent, _shift) \ 39 GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 40 41 static const struct mtk_gate vpp0_clks[] = { 42 /* VPP0_0 */ 43 GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1), 44 GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2), 45 GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7), 46 GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8), 47 GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10), 48 GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11), 49 GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13), 50 GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay", "top_vpp", 14), 51 GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15), 52 GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16), 53 GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17), 54 GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18), 55 /* VPP0_1 */ 56 GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, "vpp0_smi_common_mmsram", "top_vpp", 0), 57 GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1), 58 GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2), 59 GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, "vpp0_gals_vencsys_mmsram", "top_vpp", 3), 60 GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM, 61 "vpp0_gals_vencsys_core1_mmsram", "top_vpp", 4), 62 GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, "vpp0_gals_infra_mmsram", "top_vpp", 5), 63 GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, "vpp0_gals_camsys_mmsram", "top_vpp", 6), 64 GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7), 65 GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8), 66 GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, "vpp0_smi_reorder_mmsram", "top_vpp", 9), 67 GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10), 68 GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11), 69 GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12), 70 GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13), 71 GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16), 72 GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17), 73 GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18), 74 GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19), 75 GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20), 76 GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, "vpp0_gals_vpp1_wpesys", "top_vpp", 21), 77 GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, 78 "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp", 22), 79 GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23), 80 GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24), 81 GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25), 82 GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26), 83 GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27), 84 GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma", "top_vpp", 28), 85 GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma", "top_vpp", 29), 86 GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp", 30), 87 /* VPP0_2 */ 88 GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0), 89 GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async", "top_wpe_vpp", 1), 90 GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2), 91 GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async", "top_wpe_vpp", 3), 92 }; 93 94 static const struct mtk_clk_desc vpp0_desc = { 95 .clks = vpp0_clks, 96 .num_clks = ARRAY_SIZE(vpp0_clks), 97 }; 98 99 static const struct platform_device_id clk_mt8188_vpp0_id_table[] = { 100 { .name = "clk-mt8188-vpp0", .driver_data = (kernel_ulong_t)&vpp0_desc }, 101 { /* sentinel */ } 102 }; 103 MODULE_DEVICE_TABLE(platform, clk_mt8188_vpp0_id_table); 104 105 static struct platform_driver clk_mt8188_vpp0_drv = { 106 .probe = mtk_clk_pdev_probe, 107 .remove = mtk_clk_pdev_remove, 108 .driver = { 109 .name = "clk-mt8188-vpp0", 110 }, 111 .id_table = clk_mt8188_vpp0_id_table, 112 }; 113 module_platform_driver(clk_mt8188_vpp0_drv); 114 MODULE_LICENSE("GPL"); 115