172753163SGarmin.Chang // SPDX-License-Identifier: GPL-2.0-only 272753163SGarmin.Chang /* 372753163SGarmin.Chang * Copyright (c) 2022 MediaTek Inc. 472753163SGarmin.Chang * Author: Garmin Chang <garmin.chang@mediatek.com> 572753163SGarmin.Chang */ 672753163SGarmin.Chang 772753163SGarmin.Chang #include <dt-bindings/clock/mediatek,mt8188-clk.h> 872753163SGarmin.Chang #include <linux/clk-provider.h> 972753163SGarmin.Chang #include <linux/platform_device.h> 1072753163SGarmin.Chang 1172753163SGarmin.Chang #include "clk-gate.h" 1272753163SGarmin.Chang #include "clk-mtk.h" 1372753163SGarmin.Chang 1472753163SGarmin.Chang static const struct mtk_gate_regs vdec0_cg_regs = { 1572753163SGarmin.Chang .set_ofs = 0x0, 1672753163SGarmin.Chang .clr_ofs = 0x4, 1772753163SGarmin.Chang .sta_ofs = 0x0, 1872753163SGarmin.Chang }; 1972753163SGarmin.Chang 2072753163SGarmin.Chang static const struct mtk_gate_regs vdec1_cg_regs = { 2172753163SGarmin.Chang .set_ofs = 0x200, 2272753163SGarmin.Chang .clr_ofs = 0x204, 2372753163SGarmin.Chang .sta_ofs = 0x200, 2472753163SGarmin.Chang }; 2572753163SGarmin.Chang 2672753163SGarmin.Chang static const struct mtk_gate_regs vdec2_cg_regs = { 2772753163SGarmin.Chang .set_ofs = 0x8, 2872753163SGarmin.Chang .clr_ofs = 0xc, 2972753163SGarmin.Chang .sta_ofs = 0x8, 3072753163SGarmin.Chang }; 3172753163SGarmin.Chang 3272753163SGarmin.Chang #define GATE_VDEC0(_id, _name, _parent, _shift) \ 3372753163SGarmin.Chang GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 3472753163SGarmin.Chang 3572753163SGarmin.Chang #define GATE_VDEC1(_id, _name, _parent, _shift) \ 3672753163SGarmin.Chang GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 3772753163SGarmin.Chang 3872753163SGarmin.Chang #define GATE_VDEC2(_id, _name, _parent, _shift) \ 3972753163SGarmin.Chang GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) 4072753163SGarmin.Chang 4172753163SGarmin.Chang static const struct mtk_gate vdec1_clks[] = { 4272753163SGarmin.Chang /* VDEC1_0 */ 4372753163SGarmin.Chang GATE_VDEC0(CLK_VDEC1_SOC_VDEC, "vdec1_soc_vdec", "top_vdec", 0), 4472753163SGarmin.Chang GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ACTIVE, "vdec1_soc_vdec_active", "top_vdec", 4), 4572753163SGarmin.Chang GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ENG, "vdec1_soc_vdec_eng", "top_vdec", 8), 4672753163SGarmin.Chang /* VDEC1_1 */ 4772753163SGarmin.Chang GATE_VDEC1(CLK_VDEC1_SOC_LAT, "vdec1_soc_lat", "top_vdec", 0), 4872753163SGarmin.Chang GATE_VDEC1(CLK_VDEC1_SOC_LAT_ACTIVE, "vdec1_soc_lat_active", "top_vdec", 4), 4972753163SGarmin.Chang GATE_VDEC1(CLK_VDEC1_SOC_LAT_ENG, "vdec1_soc_lat_eng", "top_vdec", 8), 5072753163SGarmin.Chang /* VDEC1_2 */ 5172753163SGarmin.Chang GATE_VDEC2(CLK_VDEC1_SOC_LARB1, "vdec1_soc_larb1", "top_vdec", 0), 5272753163SGarmin.Chang }; 5372753163SGarmin.Chang 5472753163SGarmin.Chang static const struct mtk_gate vdec2_clks[] = { 5572753163SGarmin.Chang /* VDEC2_0 */ 5672753163SGarmin.Chang GATE_VDEC0(CLK_VDEC2_VDEC, "vdec2_vdec", "top_vdec", 0), 5772753163SGarmin.Chang GATE_VDEC0(CLK_VDEC2_VDEC_ACTIVE, "vdec2_vdec_active", "top_vdec", 4), 5872753163SGarmin.Chang GATE_VDEC0(CLK_VDEC2_VDEC_ENG, "vdec2_vdec_eng", "top_vdec", 8), 5972753163SGarmin.Chang /* VDEC2_1 */ 6072753163SGarmin.Chang GATE_VDEC1(CLK_VDEC2_LAT, "vdec2_lat", "top_vdec", 0), 6172753163SGarmin.Chang /* VDEC2_2 */ 6272753163SGarmin.Chang GATE_VDEC2(CLK_VDEC2_LARB1, "vdec2_larb1", "top_vdec", 0), 6372753163SGarmin.Chang }; 6472753163SGarmin.Chang 6572753163SGarmin.Chang static const struct mtk_clk_desc vdec1_desc = { 6672753163SGarmin.Chang .clks = vdec1_clks, 6772753163SGarmin.Chang .num_clks = ARRAY_SIZE(vdec1_clks), 6872753163SGarmin.Chang }; 6972753163SGarmin.Chang 7072753163SGarmin.Chang static const struct mtk_clk_desc vdec2_desc = { 7172753163SGarmin.Chang .clks = vdec2_clks, 7272753163SGarmin.Chang .num_clks = ARRAY_SIZE(vdec2_clks), 7372753163SGarmin.Chang }; 7472753163SGarmin.Chang 7572753163SGarmin.Chang static const struct of_device_id of_match_clk_mt8188_vdec[] = { 7672753163SGarmin.Chang { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vdec1_desc }, 7772753163SGarmin.Chang { .compatible = "mediatek,mt8188-vdecsys", .data = &vdec2_desc }, 7872753163SGarmin.Chang { /* sentinel */ } 7972753163SGarmin.Chang }; 8072753163SGarmin.Chang MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_vdec); 8172753163SGarmin.Chang 8272753163SGarmin.Chang static struct platform_driver clk_mt8188_vdec_drv = { 8372753163SGarmin.Chang .probe = mtk_clk_simple_probe, 84*61ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 8572753163SGarmin.Chang .driver = { 8672753163SGarmin.Chang .name = "clk-mt8188-vdec", 8772753163SGarmin.Chang .of_match_table = of_match_clk_mt8188_vdec, 8872753163SGarmin.Chang }, 8972753163SGarmin.Chang }; 9072753163SGarmin.Chang 9172753163SGarmin.Chang module_platform_driver(clk_mt8188_vdec_drv); 9272753163SGarmin.Chang MODULE_LICENSE("GPL"); 93