1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Garmin Chang <garmin.chang@mediatek.com> 5 */ 6 7 #include <dt-bindings/clock/mediatek,mt8188-clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/platform_device.h> 10 11 #include "clk-gate.h" 12 #include "clk-mtk.h" 13 14 static const struct mtk_gate_regs infra_ao0_cg_regs = { 15 .set_ofs = 0x80, 16 .clr_ofs = 0x84, 17 .sta_ofs = 0x90, 18 }; 19 20 static const struct mtk_gate_regs infra_ao1_cg_regs = { 21 .set_ofs = 0x88, 22 .clr_ofs = 0x8c, 23 .sta_ofs = 0x94, 24 }; 25 26 static const struct mtk_gate_regs infra_ao2_cg_regs = { 27 .set_ofs = 0xa4, 28 .clr_ofs = 0xa8, 29 .sta_ofs = 0xac, 30 }; 31 32 static const struct mtk_gate_regs infra_ao3_cg_regs = { 33 .set_ofs = 0xc0, 34 .clr_ofs = 0xc4, 35 .sta_ofs = 0xc8, 36 }; 37 38 static const struct mtk_gate_regs infra_ao4_cg_regs = { 39 .set_ofs = 0xe0, 40 .clr_ofs = 0xe4, 41 .sta_ofs = 0xe8, 42 }; 43 44 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ 45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \ 46 &mtk_clk_gate_ops_setclr, _flag) 47 48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ 49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0) 50 51 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ 52 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \ 53 &mtk_clk_gate_ops_setclr, _flag) 54 55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ 56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0) 57 58 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ 59 GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 60 61 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ 62 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \ 63 &mtk_clk_gate_ops_setclr, _flag) 64 65 #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \ 66 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \ 67 &mtk_clk_gate_ops_setclr, _flag) 68 69 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ 70 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0) 71 72 #define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \ 73 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \ 74 &mtk_clk_gate_ops_setclr, _flag) 75 76 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ 77 GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0) 78 79 static const struct mtk_gate infra_ao_clks[] = { 80 /* INFRA_AO0 */ 81 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0), 82 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1), 83 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2), 84 GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3), 85 /* infra_ao_sej is main clock is for secure engine with JTAG support */ 86 GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL), 87 GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6), 88 GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8), 89 GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9), 90 GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10), 91 GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_h", "top_axi", 15), 92 GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16), 93 GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17), 94 GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18), 95 GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19), 96 GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21), 97 GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22), 98 GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23), 99 GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24), 100 GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25), 101 GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26), 102 GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27), 103 GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "pad_fpc_ck", 28), 104 GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29), 105 /* INFRA_AO1 */ 106 GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0), 107 GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1), 108 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2), 109 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4), 110 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, "infra_ao_msdc2", "top_axi", 5), 111 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 6), 112 /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */ 113 GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC, "infra_ao_dvfsrc", 114 "clk26m", 7, CLK_IS_CRITICAL), 115 GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9), 116 GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10), 117 GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11), 118 GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12), 119 GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, "infra_ao_cec_66m_hclk", "top_axi", 13), 120 GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15), 121 GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 16), 122 GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, "infra_ao_cec_66m_bclk", "top_axi", 17), 123 GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18), 124 /* infra_ao_dapc is for device access permission control module */ 125 GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_dapc", 126 "top_axi", 20, CLK_IS_CRITICAL), 127 GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, "infra_ao_ecc_66m_hclk", "top_axi", 23), 128 GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24), 129 GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25), 130 GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26), 131 GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29), 132 GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31), 133 /* INFRA_AO2 */ 134 GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0), 135 GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2), 136 GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3), 137 GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4), 138 GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6), 139 GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9), 140 GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10), 141 GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_FSSPM, "infra_ao_fsspm", 142 "top_sspm", 15, CLK_IS_CRITICAL), 143 GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM_BUS_HCLK, "infra_ao_sspm_hclk", 144 "top_axi", 17, CLK_IS_CRITICAL), 145 GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_BCLK, "infra_ao_apdma_bclk", "top_axi", 18), 146 GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25), 147 GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26), 148 GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27), 149 /* INFRA_AO3 */ 150 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0), 151 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1sf", "top_msdc50_0", 1), 152 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2sf", "top_msdc50_0", 2), 153 GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5), 154 GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7), 155 GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8), 156 GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, "infra_ao_msdc30_2", "top_msdc30_2", 9), 157 GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10), 158 GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15), 159 GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, "infra_ao_gcpu_66m_bclk", "top_axi", 16), 160 GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, "infra_ao_gcpu_133m_bclk", "top_axi", 17), 161 GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20), 162 GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24), 163 /* infra_ao_dapc_sync is for device access permission control module */ 164 GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_dapc_sync", 165 "top_axi", 25, CLK_IS_CRITICAL), 166 GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26), 167 /* INFRA_AO4 */ 168 /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */ 169 GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_MCLK_CK, "infra_ao_133m_mclk_set", 170 "top_axi", 0, CLK_IS_CRITICAL), 171 GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_MCLK_CK, "infra_ao_66m_mclk_set", 172 "top_axi", 1, CLK_IS_CRITICAL), 173 GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", 174 "pextp_pipe", 7), 175 GATE_INFRA_AO4(CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P, 176 "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), 177 }; 178 179 static const struct mtk_clk_desc infra_ao_desc = { 180 .clks = infra_ao_clks, 181 .num_clks = ARRAY_SIZE(infra_ao_clks), 182 }; 183 184 static const struct of_device_id of_match_clk_mt8188_infra_ao[] = { 185 { .compatible = "mediatek,mt8188-infracfg-ao", .data = &infra_ao_desc }, 186 { /* sentinel */ } 187 }; 188 MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_infra_ao); 189 190 static struct platform_driver clk_mt8188_infra_ao_drv = { 191 .probe = mtk_clk_simple_probe, 192 .remove = mtk_clk_simple_remove, 193 .driver = { 194 .name = "clk-mt8188-infra_ao", 195 .of_match_table = of_match_clk_mt8188_infra_ao, 196 }, 197 }; 198 module_platform_driver(clk_mt8188_infra_ao_drv); 199 MODULE_LICENSE("GPL"); 200