1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2022 MediaTek Inc.
4  * Author: Garmin Chang <garmin.chang@mediatek.com>
5  */
6 
7 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/platform_device.h>
10 
11 #include "clk-gate.h"
12 #include "clk-mtk.h"
13 #include "clk-pll.h"
14 
15 static const struct mtk_gate_regs apmixed_cg_regs = {
16 	.set_ofs = 0x8,
17 	.clr_ofs = 0x8,
18 	.sta_ofs = 0x8,
19 };
20 
21 #define GATE_APMIXED(_id, _name, _parent, _shift)			\
22 	GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
23 
24 static const struct mtk_gate apmixed_clks[] = {
25 	GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M_EN, "pll_ssusb26m_en", "clk26m", 1),
26 };
27 
28 #define MT8188_PLL_FMAX		(3800UL * MHZ)
29 #define MT8188_PLL_FMIN		(1500UL * MHZ)
30 #define MT8188_INTEGER_BITS	8
31 
32 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
33 	    _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,		\
34 	    _tuner_reg, _tuner_en_reg, _tuner_en_bit,			\
35 	    _pcw_reg, _pcw_shift, _pcw_chg_reg,				\
36 	    _en_reg, _pll_en_bit) {					\
37 		.id = _id,						\
38 		.name = _name,						\
39 		.reg = _reg,						\
40 		.pwr_reg = _pwr_reg,					\
41 		.en_mask = _en_mask,					\
42 		.flags = _flags,					\
43 		.rst_bar_mask = _rst_bar_mask,				\
44 		.fmax = MT8188_PLL_FMAX,				\
45 		.fmin = MT8188_PLL_FMIN,				\
46 		.pcwbits = _pcwbits,					\
47 		.pcwibits = MT8188_INTEGER_BITS,			\
48 		.pd_reg = _pd_reg,					\
49 		.pd_shift = _pd_shift,					\
50 		.tuner_reg = _tuner_reg,				\
51 		.tuner_en_reg = _tuner_en_reg,				\
52 		.tuner_en_bit = _tuner_en_bit,				\
53 		.pcw_reg = _pcw_reg,					\
54 		.pcw_shift = _pcw_shift,				\
55 		.pcw_chg_reg = _pcw_chg_reg,				\
56 		.en_reg = _en_reg,					\
57 		.pll_en_bit = _pll_en_bit,				\
58 	}
59 
60 static const struct mtk_pll_data plls[] = {
61 	PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
62 	    0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
63 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
64 	    0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
65 	PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
66 	    0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
67 	PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
68 	    0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9),
69 	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
70 	    HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548, 0, 0, 0, 9),
71 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000,
72 	    HAVE_RST_BAR, BIT(23), 22, 0x0460, 24, 0, 0, 0, 0x0460, 0, 0, 0, 9),
73 	PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
74 	    0, 0, 22, 0x0558, 24, 0, 0, 0, 0x0558, 0, 0, 0, 9),
75 	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510, 0xff000000,
76 	    HAVE_RST_BAR, BIT(23), 22, 0x0508, 24, 0, 0, 0, 0x0508, 0, 0, 0, 9),
77 	PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0,
78 	    0, 0, 22, 0x0430, 24, 0, 0, 0, 0x0430, 0, 0, 0, 9),
79 	PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0,
80 	    0, 0, 32, 0x0308, 24, 0x0034, 0x0000, 12, 0x030C, 0, 0, 0, 9),
81 	PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
82 	    0, 0, 32, 0x031C, 24, 0x0038, 0x0000, 13, 0x0320, 0, 0, 0, 9),
83 	PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0,
84 	    0, 0, 32, 0x0330, 24, 0x003C, 0x0000, 14, 0x0334, 0, 0, 0, 9),
85 	PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0,
86 	    0, 0, 32, 0x0408, 24, 0x0040, 0x0000, 15, 0x040C, 0, 0, 0, 9),
87 	PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0,
88 	    0, 0, 32, 0x041C, 24, 0x0044, 0x0000, 16, 0x0420, 0, 0, 0, 9),
89 	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x034C, 0,
90 	    0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),
91 };
92 
93 static const struct of_device_id of_match_clk_mt8188_apmixed[] = {
94 	{ .compatible = "mediatek,mt8188-apmixedsys" },
95 	{ /* sentinel */ }
96 };
97 MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_apmixed);
98 
99 static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
100 {
101 	struct clk_hw_onecell_data *clk_data;
102 	struct device_node *node = pdev->dev.of_node;
103 	int r;
104 
105 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
106 	if (!clk_data)
107 		return -ENOMEM;
108 
109 	r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
110 	if (r)
111 		goto free_apmixed_data;
112 
113 	r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
114 				   ARRAY_SIZE(apmixed_clks), clk_data);
115 	if (r)
116 		goto unregister_plls;
117 
118 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
119 	if (r)
120 		goto unregister_gates;
121 
122 	platform_set_drvdata(pdev, clk_data);
123 
124 	return 0;
125 
126 unregister_gates:
127 	mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
128 unregister_plls:
129 	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
130 free_apmixed_data:
131 	mtk_free_clk_data(clk_data);
132 	return r;
133 }
134 
135 static void clk_mt8188_apmixed_remove(struct platform_device *pdev)
136 {
137 	struct device_node *node = pdev->dev.of_node;
138 	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
139 
140 	of_clk_del_provider(node);
141 	mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
142 	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
143 	mtk_free_clk_data(clk_data);
144 }
145 
146 static struct platform_driver clk_mt8188_apmixed_drv = {
147 	.probe = clk_mt8188_apmixed_probe,
148 	.remove_new = clk_mt8188_apmixed_remove,
149 	.driver = {
150 		.name = "clk-mt8188-apmixed",
151 		.of_match_table = of_match_clk_mt8188_apmixed,
152 	},
153 };
154 module_platform_driver(clk_mt8188_apmixed_drv);
155 MODULE_LICENSE("GPL");
156