1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright (c) 2022 MediaTek Inc.
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5 
6 #include <linux/clk-provider.h>
7 #include <linux/platform_device.h>
8 #include <dt-bindings/clock/mt8186-clk.h>
9 
10 #include "clk-gate.h"
11 #include "clk-mtk.h"
12 
13 static const struct mtk_gate_regs ipe_cg_regs = {
14 	.set_ofs = 0x4,
15 	.clr_ofs = 0x8,
16 	.sta_ofs = 0x0,
17 };
18 
19 #define GATE_IPE(_id, _name, _parent, _shift)			\
20 	GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
21 
22 static const struct mtk_gate ipe_clks[] = {
23 	GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "top_ipe", 0),
24 	GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "top_ipe", 1),
25 	GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "top_ipe", 2),
26 	GATE_IPE(CLK_IPE_FD, "ipe_fd", "top_ipe", 3),
27 	GATE_IPE(CLK_IPE_FE, "ipe_fe", "top_ipe", 4),
28 	GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "top_ipe", 5),
29 	GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 6),
30 	GATE_IPE(CLK_IPE_GALS_IPE, "ipe_gals_ipe", "top_img1", 8),
31 };
32 
33 static const struct mtk_clk_desc ipe_desc = {
34 	.clks = ipe_clks,
35 	.num_clks = ARRAY_SIZE(ipe_clks),
36 };
37 
38 static const struct of_device_id of_match_clk_mt8186_ipe[] = {
39 	{
40 		.compatible = "mediatek,mt8186-ipesys",
41 		.data = &ipe_desc,
42 	}, {
43 		/* sentinel */
44 	}
45 };
46 
47 static struct platform_driver clk_mt8186_ipe_drv = {
48 	.probe = mtk_clk_simple_probe,
49 	.remove = mtk_clk_simple_remove,
50 	.driver = {
51 		.name = "clk-mt8186-ipe",
52 		.of_match_table = of_match_clk_mt8186_ipe,
53 	},
54 };
55 builtin_platform_driver(clk_mt8186_ipe_drv);
56