1*66cd0b4bSChun-Jie Chen // SPDX-License-Identifier: GPL-2.0-only 2*66cd0b4bSChun-Jie Chen // 3*66cd0b4bSChun-Jie Chen // Copyright (c) 2022 MediaTek Inc. 4*66cd0b4bSChun-Jie Chen // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5*66cd0b4bSChun-Jie Chen 6*66cd0b4bSChun-Jie Chen #include <linux/clk-provider.h> 7*66cd0b4bSChun-Jie Chen #include <linux/platform_device.h> 8*66cd0b4bSChun-Jie Chen #include <dt-bindings/clock/mt8186-clk.h> 9*66cd0b4bSChun-Jie Chen 10*66cd0b4bSChun-Jie Chen #include "clk-gate.h" 11*66cd0b4bSChun-Jie Chen #include "clk-mtk.h" 12*66cd0b4bSChun-Jie Chen 13*66cd0b4bSChun-Jie Chen static const struct mtk_gate_regs imp_iic_wrap_cg_regs = { 14*66cd0b4bSChun-Jie Chen .set_ofs = 0xe08, 15*66cd0b4bSChun-Jie Chen .clr_ofs = 0xe04, 16*66cd0b4bSChun-Jie Chen .sta_ofs = 0xe00, 17*66cd0b4bSChun-Jie Chen }; 18*66cd0b4bSChun-Jie Chen 19*66cd0b4bSChun-Jie Chen #define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \ 20*66cd0b4bSChun-Jie Chen GATE_MTK(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 21*66cd0b4bSChun-Jie Chen 22*66cd0b4bSChun-Jie Chen static const struct mtk_gate imp_iic_wrap_clks[] = { 23*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0, 24*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c0", "infra_ao_i2c_ap", 0), 25*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1, 26*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c1", "infra_ao_i2c_ap", 1), 27*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2, 28*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c2", "infra_ao_i2c_ap", 2), 29*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3, 30*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c3", "infra_ao_i2c_ap", 3), 31*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4, 32*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c4", "infra_ao_i2c_ap", 4), 33*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5, 34*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c5", "infra_ao_i2c_ap", 5), 35*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6, 36*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c6", "infra_ao_i2c_ap", 6), 37*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7, 38*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c7", "infra_ao_i2c_ap", 7), 39*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8, 40*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c8", "infra_ao_i2c_ap", 8), 41*66cd0b4bSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9, 42*66cd0b4bSChun-Jie Chen "imp_iic_wrap_ap_clock_i2c9", "infra_ao_i2c_ap", 9), 43*66cd0b4bSChun-Jie Chen }; 44*66cd0b4bSChun-Jie Chen 45*66cd0b4bSChun-Jie Chen static const struct mtk_clk_desc imp_iic_wrap_desc = { 46*66cd0b4bSChun-Jie Chen .clks = imp_iic_wrap_clks, 47*66cd0b4bSChun-Jie Chen .num_clks = ARRAY_SIZE(imp_iic_wrap_clks), 48*66cd0b4bSChun-Jie Chen }; 49*66cd0b4bSChun-Jie Chen 50*66cd0b4bSChun-Jie Chen static const struct of_device_id of_match_clk_mt8186_imp_iic_wrap[] = { 51*66cd0b4bSChun-Jie Chen { 52*66cd0b4bSChun-Jie Chen .compatible = "mediatek,mt8186-imp_iic_wrap", 53*66cd0b4bSChun-Jie Chen .data = &imp_iic_wrap_desc, 54*66cd0b4bSChun-Jie Chen }, { 55*66cd0b4bSChun-Jie Chen /* sentinel */ 56*66cd0b4bSChun-Jie Chen } 57*66cd0b4bSChun-Jie Chen }; 58*66cd0b4bSChun-Jie Chen 59*66cd0b4bSChun-Jie Chen static struct platform_driver clk_mt8186_imp_iic_wrap_drv = { 60*66cd0b4bSChun-Jie Chen .probe = mtk_clk_simple_probe, 61*66cd0b4bSChun-Jie Chen .remove = mtk_clk_simple_remove, 62*66cd0b4bSChun-Jie Chen .driver = { 63*66cd0b4bSChun-Jie Chen .name = "clk-mt8186-imp_iic_wrap", 64*66cd0b4bSChun-Jie Chen .of_match_table = of_match_clk_mt8186_imp_iic_wrap, 65*66cd0b4bSChun-Jie Chen }, 66*66cd0b4bSChun-Jie Chen }; 67*66cd0b4bSChun-Jie Chen builtin_platform_driver(clk_mt8186_imp_iic_wrap_drv); 68