1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2022 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk-provider.h> 7 #include <linux/platform_device.h> 8 #include <dt-bindings/clock/mt8186-clk.h> 9 10 #include "clk-mtk.h" 11 #include "clk-pll.h" 12 #include "clk-pllfh.h" 13 14 #define MT8186_PLL_FMAX (3800UL * MHZ) 15 #define MT8186_PLL_FMIN (1500UL * MHZ) 16 #define MT8186_INTEGER_BITS (8) 17 18 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 19 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 20 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 21 _pcw_reg) { \ 22 .id = _id, \ 23 .name = _name, \ 24 .reg = _reg, \ 25 .pwr_reg = _pwr_reg, \ 26 .en_mask = _en_mask, \ 27 .flags = _flags, \ 28 .rst_bar_mask = _rst_bar_mask, \ 29 .fmax = MT8186_PLL_FMAX, \ 30 .fmin = MT8186_PLL_FMIN, \ 31 .pcwbits = _pcwbits, \ 32 .pcwibits = MT8186_INTEGER_BITS, \ 33 .pd_reg = _pd_reg, \ 34 .pd_shift = _pd_shift, \ 35 .tuner_reg = _tuner_reg, \ 36 .tuner_en_reg = _tuner_en_reg, \ 37 .tuner_en_bit = _tuner_en_bit, \ 38 .pcw_reg = _pcw_reg, \ 39 .pcw_shift = 0, \ 40 .pcw_chg_reg = 0, \ 41 .en_reg = 0, \ 42 .pll_en_bit = 0, \ 43 } 44 45 static const struct mtk_pll_data plls[] = { 46 /* 47 * armpll_ll/armpll_bl/ccipll are main clock source of AP MCU, 48 * should not be closed in Linux world. 49 */ 50 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0204, 0x0210, 0, 51 PLL_AO, 0, 22, 0x0208, 24, 0, 0, 0, 0x0208), 52 PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0214, 0x0220, 0, 53 PLL_AO, 0, 22, 0x0218, 24, 0, 0, 0, 0x0218), 54 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0, 55 PLL_AO, 0, 22, 0x0228, 24, 0, 0, 0, 0x0228), 56 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000, 57 HAVE_RST_BAR, BIT(23), 22, 0x0248, 24, 0, 0, 0, 0x0248), 58 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0324, 0x0330, 0xff000000, 59 HAVE_RST_BAR, BIT(23), 22, 0x0328, 24, 0, 0, 0, 0x0328), 60 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0, 61 0, 0, 22, 0x0390, 24, 0, 0, 0, 0x0390), 62 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0, 63 0, 0, 22, 0x0258, 24, 0, 0, 0, 0x0258), 64 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0, 65 0, 0, 22, 0x0360, 24, 0, 0, 0, 0x0360), 66 PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0, 67 0, 0, 22, 0x0370, 24, 0, 0, 0, 0x0370), 68 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0, 69 0, 0, 22, 0x0308, 24, 0, 0, 0, 0x0308), 70 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0, 71 0, 0, 22, 0x0318, 24, 0, 0, 0, 0x0318), 72 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0, 73 0, 0, 22, 0x0268, 24, 0, 0, 0, 0x0268), 74 PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0, 75 0, 0, 32, 0x0338, 24, 0x0040, 0x000C, 0, 0x033C), 76 PLL(CLK_APMIXED_APLL2, "apll2", 0x0348, 0x0358, 0, 77 0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350), 78 }; 79 80 enum fh_pll_id { 81 FH_ARMPLL_LL, 82 FH_ARMPLL_BL, 83 FH_CCIPLL, 84 FH_MAINPLL, 85 FH_MMPLL, 86 FH_TVDPLL, 87 FH_RESERVE6, 88 FH_ADSPPLL, 89 FH_MFGPLL, 90 FH_NNAPLL, 91 FH_NNA2PLL, 92 FH_MSDCPLL, 93 FH_RESERVE12, 94 FH_NR_FH, 95 }; 96 97 #define FH(_pllid, _fhid, _offset) { \ 98 .data = { \ 99 .pll_id = _pllid, \ 100 .fh_id = _fhid, \ 101 .fhx_offset = _offset, \ 102 .dds_mask = GENMASK(21, 0), \ 103 .slope0_value = 0x6003c97, \ 104 .slope1_value = 0x6003c97, \ 105 .sfstrx_en = BIT(2), \ 106 .frddsx_en = BIT(1), \ 107 .fhctlx_en = BIT(0), \ 108 .tgl_org = BIT(31), \ 109 .dvfs_tri = BIT(31), \ 110 .pcwchg = BIT(31), \ 111 .dt_val = 0x0, \ 112 .df_val = 0x9, \ 113 .updnlmt_shft = 16, \ 114 .msk_frddsx_dys = GENMASK(23, 20), \ 115 .msk_frddsx_dts = GENMASK(19, 16), \ 116 }, \ 117 } 118 119 static struct mtk_pllfh_data pllfhs[] = { 120 FH(CLK_APMIXED_ARMPLL_LL, FH_ARMPLL_LL, 0x003C), 121 FH(CLK_APMIXED_ARMPLL_BL, FH_ARMPLL_BL, 0x0050), 122 FH(CLK_APMIXED_CCIPLL, FH_CCIPLL, 0x0064), 123 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x0078), 124 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x008C), 125 FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x00A0), 126 FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x00C8), 127 FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0x00DC), 128 FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x00F0), 129 FH(CLK_APMIXED_NNA2PLL, FH_NNA2PLL, 0x0104), 130 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118), 131 }; 132 133 static const struct of_device_id of_match_clk_mt8186_apmixed[] = { 134 { .compatible = "mediatek,mt8186-apmixedsys", }, 135 {} 136 }; 137 138 static int clk_mt8186_apmixed_probe(struct platform_device *pdev) 139 { 140 struct clk_hw_onecell_data *clk_data; 141 struct device_node *node = pdev->dev.of_node; 142 const u8 *fhctl_node = "mediatek,mt8186-fhctl"; 143 int r; 144 145 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 146 if (!clk_data) 147 return -ENOMEM; 148 149 fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); 150 151 r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), 152 pllfhs, ARRAY_SIZE(pllfhs), clk_data); 153 if (r) 154 goto free_apmixed_data; 155 156 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 157 if (r) 158 goto unregister_plls; 159 160 platform_set_drvdata(pdev, clk_data); 161 162 return r; 163 164 unregister_plls: 165 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, 166 ARRAY_SIZE(pllfhs), clk_data); 167 free_apmixed_data: 168 mtk_free_clk_data(clk_data); 169 return r; 170 } 171 172 static int clk_mt8186_apmixed_remove(struct platform_device *pdev) 173 { 174 struct device_node *node = pdev->dev.of_node; 175 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); 176 177 of_clk_del_provider(node); 178 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, 179 ARRAY_SIZE(pllfhs), clk_data); 180 mtk_free_clk_data(clk_data); 181 182 return 0; 183 } 184 185 static struct platform_driver clk_mt8186_apmixed_drv = { 186 .probe = clk_mt8186_apmixed_probe, 187 .remove = clk_mt8186_apmixed_remove, 188 .driver = { 189 .name = "clk-mt8186-apmixed", 190 .of_match_table = of_match_clk_mt8186_apmixed, 191 }, 192 }; 193 builtin_platform_driver(clk_mt8186_apmixed_drv); 194