1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2022 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk-provider.h> 7 #include <linux/platform_device.h> 8 #include <dt-bindings/clock/mt8186-clk.h> 9 10 #include "clk-mtk.h" 11 #include "clk-pll.h" 12 13 #define MT8186_PLL_FMAX (3800UL * MHZ) 14 #define MT8186_PLL_FMIN (1500UL * MHZ) 15 #define MT8186_INTEGER_BITS (8) 16 17 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 18 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 19 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 20 _pcw_reg) { \ 21 .id = _id, \ 22 .name = _name, \ 23 .reg = _reg, \ 24 .pwr_reg = _pwr_reg, \ 25 .en_mask = _en_mask, \ 26 .flags = _flags, \ 27 .rst_bar_mask = _rst_bar_mask, \ 28 .fmax = MT8186_PLL_FMAX, \ 29 .fmin = MT8186_PLL_FMIN, \ 30 .pcwbits = _pcwbits, \ 31 .pcwibits = MT8186_INTEGER_BITS, \ 32 .pd_reg = _pd_reg, \ 33 .pd_shift = _pd_shift, \ 34 .tuner_reg = _tuner_reg, \ 35 .tuner_en_reg = _tuner_en_reg, \ 36 .tuner_en_bit = _tuner_en_bit, \ 37 .pcw_reg = _pcw_reg, \ 38 .pcw_shift = 0, \ 39 .pcw_chg_reg = 0, \ 40 .en_reg = 0, \ 41 .pll_en_bit = 0, \ 42 } 43 44 static const struct mtk_pll_data plls[] = { 45 /* 46 * armpll_ll/armpll_bl/ccipll are main clock source of AP MCU, 47 * should not be closed in Linux world. 48 */ 49 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0204, 0x0210, 0, 50 PLL_AO, 0, 22, 0x0208, 24, 0, 0, 0, 0x0208), 51 PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0214, 0x0220, 0, 52 PLL_AO, 0, 22, 0x0218, 24, 0, 0, 0, 0x0218), 53 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0, 54 PLL_AO, 0, 22, 0x0228, 24, 0, 0, 0, 0x0228), 55 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000, 56 HAVE_RST_BAR, BIT(23), 22, 0x0248, 24, 0, 0, 0, 0x0248), 57 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0324, 0x0330, 0xff000000, 58 HAVE_RST_BAR, BIT(23), 22, 0x0328, 24, 0, 0, 0, 0x0328), 59 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0, 60 0, 0, 22, 0x0390, 24, 0, 0, 0, 0x0390), 61 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0, 62 0, 0, 22, 0x0258, 24, 0, 0, 0, 0x0258), 63 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0, 64 0, 0, 22, 0x0360, 24, 0, 0, 0, 0x0360), 65 PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0, 66 0, 0, 22, 0x0370, 24, 0, 0, 0, 0x0370), 67 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0, 68 0, 0, 22, 0x0308, 24, 0, 0, 0, 0x0308), 69 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0, 70 0, 0, 22, 0x0318, 24, 0, 0, 0, 0x0318), 71 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0, 72 0, 0, 22, 0x0268, 24, 0, 0, 0, 0x0268), 73 PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0, 74 0, 0, 32, 0x0338, 24, 0x0040, 0x000C, 0, 0x033C), 75 PLL(CLK_APMIXED_APLL2, "apll2", 0x0348, 0x0358, 0, 76 0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350), 77 }; 78 79 static const struct of_device_id of_match_clk_mt8186_apmixed[] = { 80 { .compatible = "mediatek,mt8186-apmixedsys", }, 81 {} 82 }; 83 84 static int clk_mt8186_apmixed_probe(struct platform_device *pdev) 85 { 86 struct clk_hw_onecell_data *clk_data; 87 struct device_node *node = pdev->dev.of_node; 88 int r; 89 90 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 91 if (!clk_data) 92 return -ENOMEM; 93 94 r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 95 if (r) 96 goto free_apmixed_data; 97 98 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 99 if (r) 100 goto unregister_plls; 101 102 platform_set_drvdata(pdev, clk_data); 103 104 return r; 105 106 unregister_plls: 107 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); 108 free_apmixed_data: 109 mtk_free_clk_data(clk_data); 110 return r; 111 } 112 113 static int clk_mt8186_apmixed_remove(struct platform_device *pdev) 114 { 115 struct device_node *node = pdev->dev.of_node; 116 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); 117 118 of_clk_del_provider(node); 119 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); 120 mtk_free_clk_data(clk_data); 121 122 return 0; 123 } 124 125 static struct platform_driver clk_mt8186_apmixed_drv = { 126 .probe = clk_mt8186_apmixed_probe, 127 .remove = clk_mt8186_apmixed_remove, 128 .driver = { 129 .name = "clk-mt8186-apmixed", 130 .of_match_table = of_match_clk_mt8186_apmixed, 131 }, 132 }; 133 builtin_platform_driver(clk_mt8186_apmixed_drv); 134