1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 6 #include <linux/delay.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 14 #include "clk-mtk.h" 15 #include "clk-mux.h" 16 #include "clk-gate.h" 17 18 #include <dt-bindings/clock/mt8183-clk.h> 19 20 static DEFINE_SPINLOCK(mt8183_clk_lock); 21 22 static const struct mtk_fixed_clk top_fixed_clks[] = { 23 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 24 FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 25 FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 26 }; 27 28 static const struct mtk_fixed_factor top_divs[] = { 29 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 30 2), 31 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 32 2), 33 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 34 1), 35 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 36 2), 37 FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 38 2), 39 FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 40 4), 41 FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 42 8), 43 FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 44 16), 45 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 46 3), 47 FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 48 2), 49 FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 50 4), 51 FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 52 8), 53 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 54 5), 55 FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 56 2), 57 FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 58 4), 59 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 60 7), 61 FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 62 2), 63 FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 64 4), 65 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 66 1), 67 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 68 2), 69 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 70 2), 71 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 72 4), 73 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 74 8), 75 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 76 3), 77 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 78 2), 79 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 80 4), 81 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 82 8), 83 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 84 5), 85 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 86 2), 87 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 88 4), 89 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 90 8), 91 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 92 7), 93 FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 94 1), 95 FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 96 2), 97 FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 98 4), 99 FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 100 8), 101 FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 102 16), 103 FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 104 32), 105 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 106 1), 107 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 108 2), 109 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 110 4), 111 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 112 8), 113 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 114 1), 115 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 116 2), 117 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 118 4), 119 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 120 8), 121 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 122 1), 123 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 124 2), 125 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 126 4), 127 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 128 8), 129 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 130 16), 131 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 132 1), 133 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 134 4), 135 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 136 2), 137 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 138 4), 139 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 140 5), 141 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 142 2), 143 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 144 4), 145 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 146 6), 147 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 148 7), 149 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 150 1), 151 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 152 1), 153 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 154 2), 155 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 156 4), 157 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 158 8), 159 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 160 16), 161 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 162 1), 163 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 164 2), 165 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 166 4), 167 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 168 8), 169 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 170 16), 171 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 172 2), 173 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 174 16), 175 }; 176 177 static const char * const axi_parents[] = { 178 "clk26m", 179 "syspll_d2_d4", 180 "syspll_d7", 181 "osc_d4" 182 }; 183 184 static const char * const mm_parents[] = { 185 "clk26m", 186 "mmpll_d7", 187 "syspll_d3", 188 "univpll_d2_d2", 189 "syspll_d2_d2", 190 "syspll_d3_d2" 191 }; 192 193 static const char * const img_parents[] = { 194 "clk26m", 195 "mmpll_d6", 196 "univpll_d3", 197 "syspll_d3", 198 "univpll_d2_d2", 199 "syspll_d2_d2", 200 "univpll_d3_d2", 201 "syspll_d3_d2" 202 }; 203 204 static const char * const cam_parents[] = { 205 "clk26m", 206 "syspll_d2", 207 "mmpll_d6", 208 "syspll_d3", 209 "mmpll_d7", 210 "univpll_d3", 211 "univpll_d2_d2", 212 "syspll_d2_d2", 213 "syspll_d3_d2", 214 "univpll_d3_d2" 215 }; 216 217 static const char * const dsp_parents[] = { 218 "clk26m", 219 "mmpll_d6", 220 "mmpll_d7", 221 "univpll_d3", 222 "syspll_d3", 223 "univpll_d2_d2", 224 "syspll_d2_d2", 225 "univpll_d3_d2", 226 "syspll_d3_d2" 227 }; 228 229 static const char * const dsp1_parents[] = { 230 "clk26m", 231 "mmpll_d6", 232 "mmpll_d7", 233 "univpll_d3", 234 "syspll_d3", 235 "univpll_d2_d2", 236 "syspll_d2_d2", 237 "univpll_d3_d2", 238 "syspll_d3_d2" 239 }; 240 241 static const char * const dsp2_parents[] = { 242 "clk26m", 243 "mmpll_d6", 244 "mmpll_d7", 245 "univpll_d3", 246 "syspll_d3", 247 "univpll_d2_d2", 248 "syspll_d2_d2", 249 "univpll_d3_d2", 250 "syspll_d3_d2" 251 }; 252 253 static const char * const ipu_if_parents[] = { 254 "clk26m", 255 "mmpll_d6", 256 "mmpll_d7", 257 "univpll_d3", 258 "syspll_d3", 259 "univpll_d2_d2", 260 "syspll_d2_d2", 261 "univpll_d3_d2", 262 "syspll_d3_d2" 263 }; 264 265 static const char * const mfg_parents[] = { 266 "clk26m", 267 "mfgpll_ck", 268 "univpll_d3", 269 "syspll_d3" 270 }; 271 272 static const char * const f52m_mfg_parents[] = { 273 "clk26m", 274 "univpll_d3_d2", 275 "univpll_d3_d4", 276 "univpll_d3_d8" 277 }; 278 279 static const char * const camtg_parents[] = { 280 "clk26m", 281 "univ_192m_d8", 282 "univpll_d3_d8", 283 "univ_192m_d4", 284 "univpll_d3_d16", 285 "csw_f26m_ck_d2", 286 "univ_192m_d16", 287 "univ_192m_d32" 288 }; 289 290 static const char * const camtg2_parents[] = { 291 "clk26m", 292 "univ_192m_d8", 293 "univpll_d3_d8", 294 "univ_192m_d4", 295 "univpll_d3_d16", 296 "csw_f26m_ck_d2", 297 "univ_192m_d16", 298 "univ_192m_d32" 299 }; 300 301 static const char * const camtg3_parents[] = { 302 "clk26m", 303 "univ_192m_d8", 304 "univpll_d3_d8", 305 "univ_192m_d4", 306 "univpll_d3_d16", 307 "csw_f26m_ck_d2", 308 "univ_192m_d16", 309 "univ_192m_d32" 310 }; 311 312 static const char * const camtg4_parents[] = { 313 "clk26m", 314 "univ_192m_d8", 315 "univpll_d3_d8", 316 "univ_192m_d4", 317 "univpll_d3_d16", 318 "csw_f26m_ck_d2", 319 "univ_192m_d16", 320 "univ_192m_d32" 321 }; 322 323 static const char * const uart_parents[] = { 324 "clk26m", 325 "univpll_d3_d8" 326 }; 327 328 static const char * const spi_parents[] = { 329 "clk26m", 330 "syspll_d5_d2", 331 "syspll_d3_d4", 332 "msdcpll_d4" 333 }; 334 335 static const char * const msdc50_hclk_parents[] = { 336 "clk26m", 337 "syspll_d2_d2", 338 "syspll_d3_d2" 339 }; 340 341 static const char * const msdc50_0_parents[] = { 342 "clk26m", 343 "msdcpll_ck", 344 "msdcpll_d2", 345 "univpll_d2_d4", 346 "syspll_d3_d2", 347 "univpll_d2_d2" 348 }; 349 350 static const char * const msdc30_1_parents[] = { 351 "clk26m", 352 "univpll_d3_d2", 353 "syspll_d3_d2", 354 "syspll_d7", 355 "msdcpll_d2" 356 }; 357 358 static const char * const msdc30_2_parents[] = { 359 "clk26m", 360 "univpll_d3_d2", 361 "syspll_d3_d2", 362 "syspll_d7", 363 "msdcpll_d2" 364 }; 365 366 static const char * const audio_parents[] = { 367 "clk26m", 368 "syspll_d5_d4", 369 "syspll_d7_d4", 370 "syspll_d2_d16" 371 }; 372 373 static const char * const aud_intbus_parents[] = { 374 "clk26m", 375 "syspll_d2_d4", 376 "syspll_d7_d2" 377 }; 378 379 static const char * const pmicspi_parents[] = { 380 "clk26m", 381 "syspll_d2_d8", 382 "osc_d8" 383 }; 384 385 static const char * const fpwrap_ulposc_parents[] = { 386 "clk26m", 387 "osc_d16", 388 "osc_d4", 389 "osc_d8" 390 }; 391 392 static const char * const atb_parents[] = { 393 "clk26m", 394 "syspll_d2_d2", 395 "syspll_d5" 396 }; 397 398 static const char * const dpi0_parents[] = { 399 "clk26m", 400 "tvdpll_d2", 401 "tvdpll_d4", 402 "tvdpll_d8", 403 "tvdpll_d16", 404 "univpll_d5_d2", 405 "univpll_d3_d4", 406 "syspll_d3_d4", 407 "univpll_d3_d8" 408 }; 409 410 static const char * const scam_parents[] = { 411 "clk26m", 412 "syspll_d5_d2" 413 }; 414 415 static const char * const disppwm_parents[] = { 416 "clk26m", 417 "univpll_d3_d4", 418 "osc_d2", 419 "osc_d4", 420 "osc_d16" 421 }; 422 423 static const char * const usb_top_parents[] = { 424 "clk26m", 425 "univpll_d5_d4", 426 "univpll_d3_d4", 427 "univpll_d5_d2" 428 }; 429 430 431 static const char * const ssusb_top_xhci_parents[] = { 432 "clk26m", 433 "univpll_d5_d4", 434 "univpll_d3_d4", 435 "univpll_d5_d2" 436 }; 437 438 static const char * const spm_parents[] = { 439 "clk26m", 440 "syspll_d2_d8" 441 }; 442 443 static const char * const i2c_parents[] = { 444 "clk26m", 445 "syspll_d2_d8", 446 "univpll_d5_d2" 447 }; 448 449 static const char * const scp_parents[] = { 450 "clk26m", 451 "univpll_d2_d8", 452 "syspll_d5", 453 "syspll_d2_d2", 454 "univpll_d2_d2", 455 "syspll_d3", 456 "univpll_d3" 457 }; 458 459 static const char * const seninf_parents[] = { 460 "clk26m", 461 "univpll_d2_d2", 462 "univpll_d3_d2", 463 "univpll_d2_d4" 464 }; 465 466 static const char * const dxcc_parents[] = { 467 "clk26m", 468 "syspll_d2_d2", 469 "syspll_d2_d4", 470 "syspll_d2_d8" 471 }; 472 473 static const char * const aud_engen1_parents[] = { 474 "clk26m", 475 "apll1_d2", 476 "apll1_d4", 477 "apll1_d8" 478 }; 479 480 static const char * const aud_engen2_parents[] = { 481 "clk26m", 482 "apll2_d2", 483 "apll2_d4", 484 "apll2_d8" 485 }; 486 487 static const char * const faes_ufsfde_parents[] = { 488 "clk26m", 489 "syspll_d2", 490 "syspll_d2_d2", 491 "syspll_d3", 492 "syspll_d2_d4", 493 "univpll_d3" 494 }; 495 496 static const char * const fufs_parents[] = { 497 "clk26m", 498 "syspll_d2_d4", 499 "syspll_d2_d8", 500 "syspll_d2_d16" 501 }; 502 503 static const char * const aud_1_parents[] = { 504 "clk26m", 505 "apll1_ck" 506 }; 507 508 static const char * const aud_2_parents[] = { 509 "clk26m", 510 "apll2_ck" 511 }; 512 513 /* 514 * CRITICAL CLOCK: 515 * axi_sel is the main bus clock of whole SOC. 516 * spm_sel is the clock of the always-on co-processor. 517 */ 518 static const struct mtk_mux top_muxes[] = { 519 /* CLK_CFG_0 */ 520 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 521 axi_parents, 0x40, 522 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), 523 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 524 mm_parents, 0x40, 525 0x44, 0x48, 8, 3, 15, 0x004, 1), 526 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 527 img_parents, 0x40, 528 0x44, 0x48, 16, 3, 23, 0x004, 2), 529 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 530 cam_parents, 0x40, 531 0x44, 0x48, 24, 4, 31, 0x004, 3), 532 /* CLK_CFG_1 */ 533 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 534 dsp_parents, 0x50, 535 0x54, 0x58, 0, 4, 7, 0x004, 4), 536 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 537 dsp1_parents, 0x50, 538 0x54, 0x58, 8, 4, 15, 0x004, 5), 539 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 540 dsp2_parents, 0x50, 541 0x54, 0x58, 16, 4, 23, 0x004, 6), 542 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 543 ipu_if_parents, 0x50, 544 0x54, 0x58, 24, 4, 31, 0x004, 7), 545 /* CLK_CFG_2 */ 546 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 547 mfg_parents, 0x60, 548 0x64, 0x68, 0, 2, 7, 0x004, 8), 549 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 550 f52m_mfg_parents, 0x60, 551 0x64, 0x68, 8, 2, 15, 0x004, 9), 552 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 553 camtg_parents, 0x60, 554 0x64, 0x68, 16, 3, 23, 0x004, 10), 555 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 556 camtg2_parents, 0x60, 557 0x64, 0x68, 24, 3, 31, 0x004, 11), 558 /* CLK_CFG_3 */ 559 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 560 camtg3_parents, 0x70, 561 0x74, 0x78, 0, 3, 7, 0x004, 12), 562 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 563 camtg4_parents, 0x70, 564 0x74, 0x78, 8, 3, 15, 0x004, 13), 565 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 566 uart_parents, 0x70, 567 0x74, 0x78, 16, 1, 23, 0x004, 14), 568 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 569 spi_parents, 0x70, 570 0x74, 0x78, 24, 2, 31, 0x004, 15), 571 /* CLK_CFG_4 */ 572 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 573 msdc50_hclk_parents, 0x80, 574 0x84, 0x88, 0, 2, 7, 0x004, 16), 575 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 576 msdc50_0_parents, 0x80, 577 0x84, 0x88, 8, 3, 15, 0x004, 17), 578 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 579 msdc30_1_parents, 0x80, 580 0x84, 0x88, 16, 3, 23, 0x004, 18), 581 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 582 msdc30_2_parents, 0x80, 583 0x84, 0x88, 24, 3, 31, 0x004, 19), 584 /* CLK_CFG_5 */ 585 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 586 audio_parents, 0x90, 587 0x94, 0x98, 0, 2, 7, 0x004, 20), 588 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 589 aud_intbus_parents, 0x90, 590 0x94, 0x98, 8, 2, 15, 0x004, 21), 591 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 592 pmicspi_parents, 0x90, 593 0x94, 0x98, 16, 2, 23, 0x004, 22), 594 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 595 fpwrap_ulposc_parents, 0x90, 596 0x94, 0x98, 24, 2, 31, 0x004, 23), 597 /* CLK_CFG_6 */ 598 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 599 atb_parents, 0xa0, 600 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 601 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 602 dpi0_parents, 0xa0, 603 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 604 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 605 scam_parents, 0xa0, 606 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 607 /* CLK_CFG_7 */ 608 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 609 disppwm_parents, 0xb0, 610 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 611 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 612 usb_top_parents, 0xb0, 613 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 614 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 615 ssusb_top_xhci_parents, 0xb0, 616 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 617 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 618 spm_parents, 0xb0, 619 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), 620 /* CLK_CFG_8 */ 621 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 622 i2c_parents, 0xc0, 623 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 624 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 625 scp_parents, 0xc0, 626 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 627 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 628 seninf_parents, 0xc0, 629 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 630 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 631 dxcc_parents, 0xc0, 632 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 633 /* CLK_CFG_9 */ 634 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 635 aud_engen1_parents, 0xd0, 636 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 637 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 638 aud_engen2_parents, 0xd0, 639 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 640 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 641 faes_ufsfde_parents, 0xd0, 642 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 643 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 644 fufs_parents, 0xd0, 645 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 646 /* CLK_CFG_10 */ 647 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 648 aud_1_parents, 0xe0, 649 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 650 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 651 aud_2_parents, 0xe0, 652 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 653 }; 654 655 static const char * const apll_i2s0_parents[] = { 656 "aud_1_sel", 657 "aud_2_sel" 658 }; 659 660 static const char * const apll_i2s1_parents[] = { 661 "aud_1_sel", 662 "aud_2_sel" 663 }; 664 665 static const char * const apll_i2s2_parents[] = { 666 "aud_1_sel", 667 "aud_2_sel" 668 }; 669 670 static const char * const apll_i2s3_parents[] = { 671 "aud_1_sel", 672 "aud_2_sel" 673 }; 674 675 static const char * const apll_i2s4_parents[] = { 676 "aud_1_sel", 677 "aud_2_sel" 678 }; 679 680 static const char * const apll_i2s5_parents[] = { 681 "aud_1_sel", 682 "aud_2_sel" 683 }; 684 685 static struct mtk_composite top_aud_muxes[] = { 686 MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 687 0x320, 8, 1), 688 MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 689 0x320, 9, 1), 690 MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 691 0x320, 10, 1), 692 MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 693 0x320, 11, 1), 694 MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 695 0x320, 12, 1), 696 MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 697 0x328, 20, 1), 698 }; 699 700 static const char * const mcu_mp0_parents[] = { 701 "clk26m", 702 "armpll_ll", 703 "armpll_div_pll1", 704 "armpll_div_pll2" 705 }; 706 707 static const char * const mcu_mp2_parents[] = { 708 "clk26m", 709 "armpll_l", 710 "armpll_div_pll1", 711 "armpll_div_pll2" 712 }; 713 714 static const char * const mcu_bus_parents[] = { 715 "clk26m", 716 "ccipll", 717 "armpll_div_pll1", 718 "armpll_div_pll2" 719 }; 720 721 static struct mtk_composite mcu_muxes[] = { 722 /* mp0_pll_divider_cfg */ 723 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 724 /* mp2_pll_divider_cfg */ 725 MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 726 /* bus_pll_divider_cfg */ 727 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 728 }; 729 730 static struct mtk_composite top_aud_divs[] = { 731 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 732 0x320, 2, 0x324, 8, 0), 733 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 734 0x320, 3, 0x324, 8, 8), 735 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 736 0x320, 4, 0x324, 8, 16), 737 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 738 0x320, 5, 0x324, 8, 24), 739 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 740 0x320, 6, 0x328, 8, 0), 741 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 742 0x320, 7, 0x328, 8, 8), 743 }; 744 745 static const struct mtk_gate_regs top_cg_regs = { 746 .set_ofs = 0x104, 747 .clr_ofs = 0x104, 748 .sta_ofs = 0x104, 749 }; 750 751 #define GATE_TOP(_id, _name, _parent, _shift) \ 752 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 753 &mtk_clk_gate_ops_no_setclr_inv) 754 755 static const struct mtk_gate top_clks[] = { 756 /* TOP */ 757 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 758 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 759 }; 760 761 static const struct mtk_gate_regs infra0_cg_regs = { 762 .set_ofs = 0x80, 763 .clr_ofs = 0x84, 764 .sta_ofs = 0x90, 765 }; 766 767 static const struct mtk_gate_regs infra1_cg_regs = { 768 .set_ofs = 0x88, 769 .clr_ofs = 0x8c, 770 .sta_ofs = 0x94, 771 }; 772 773 static const struct mtk_gate_regs infra2_cg_regs = { 774 .set_ofs = 0xa4, 775 .clr_ofs = 0xa8, 776 .sta_ofs = 0xac, 777 }; 778 779 static const struct mtk_gate_regs infra3_cg_regs = { 780 .set_ofs = 0xc0, 781 .clr_ofs = 0xc4, 782 .sta_ofs = 0xc8, 783 }; 784 785 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 786 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 787 &mtk_clk_gate_ops_setclr) 788 789 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 790 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 791 &mtk_clk_gate_ops_setclr) 792 793 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 794 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 795 &mtk_clk_gate_ops_setclr) 796 797 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 798 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 799 &mtk_clk_gate_ops_setclr) 800 801 static const struct mtk_gate infra_clks[] = { 802 /* INFRA0 */ 803 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 804 "axi_sel", 0), 805 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 806 "axi_sel", 1), 807 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 808 "axi_sel", 2), 809 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", 810 "axi_sel", 3), 811 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", 812 "scp_sel", 4), 813 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", 814 "f_f26m_ck", 5), 815 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", 816 "axi_sel", 6), 817 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", 818 "axi_sel", 8), 819 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", 820 "axi_sel", 9), 821 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", 822 "axi_sel", 10), 823 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", 824 "i2c_sel", 11), 825 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", 826 "i2c_sel", 12), 827 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", 828 "i2c_sel", 13), 829 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", 830 "i2c_sel", 14), 831 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", 832 "axi_sel", 15), 833 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", 834 "i2c_sel", 16), 835 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", 836 "i2c_sel", 17), 837 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", 838 "i2c_sel", 18), 839 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", 840 "i2c_sel", 19), 841 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 842 "i2c_sel", 21), 843 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 844 "uart_sel", 22), 845 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 846 "uart_sel", 23), 847 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", 848 "uart_sel", 24), 849 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", 850 "uart_sel", 25), 851 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", 852 "axi_sel", 27), 853 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", 854 "axi_sel", 28), 855 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", 856 "axi_sel", 31), 857 /* INFRA1 */ 858 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", 859 "spi_sel", 1), 860 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", 861 "msdc50_hclk_sel", 2), 862 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", 863 "axi_sel", 4), 864 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", 865 "axi_sel", 5), 866 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", 867 "msdc50_0_sel", 6), 868 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", 869 "f_f26m_ck", 7), 870 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", 871 "axi_sel", 8), 872 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", 873 "axi_sel", 9), 874 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", 875 "f_f26m_ck", 10), 876 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", 877 "axi_sel", 11), 878 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", 879 "axi_sel", 12), 880 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", 881 "axi_sel", 13), 882 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", 883 "f_f26m_ck", 14), 884 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", 885 "msdc30_1_sel", 16), 886 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", 887 "msdc30_2_sel", 17), 888 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", 889 "axi_sel", 18), 890 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", 891 "axi_sel", 19), 892 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", 893 "axi_sel", 20), 894 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", 895 "axi_sel", 23), 896 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", 897 "axi_sel", 24), 898 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", 899 "axi_sel", 25), 900 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", 901 "axi_sel", 26), 902 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", 903 "dxcc_sel", 27), 904 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", 905 "dxcc_sel", 28), 906 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", 907 "axi_sel", 30), 908 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 909 "f_f26m_ck", 31), 910 /* INFRA2 */ 911 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", 912 "f_f26m_ck", 0), 913 GATE_INFRA2(CLK_INFRA_USB, "infra_usb", 914 "usb_top_sel", 1), 915 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", 916 "axi_sel", 2), 917 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", 918 "axi_sel", 3), 919 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", 920 "f_f26m_ck", 4), 921 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", 922 "spi_sel", 6), 923 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", 924 "i2c_sel", 7), 925 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", 926 "f_f26m_ck", 8), 927 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", 928 "spi_sel", 9), 929 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", 930 "spi_sel", 10), 931 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", 932 "ssusb_top_xhci_sel", 11), 933 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", 934 "fufs_sel", 12), 935 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", 936 "fufs_sel", 13), 937 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", 938 "axi_sel", 14), 939 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", 940 "axi_sel", 16), 941 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", 942 "i2c_sel", 18), 943 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", 944 "i2c_sel", 19), 945 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", 946 "i2c_sel", 20), 947 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", 948 "i2c_sel", 21), 949 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", 950 "i2c_sel", 22), 951 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", 952 "i2c_sel", 23), 953 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", 954 "i2c_sel", 24), 955 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", 956 "spi_sel", 25), 957 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", 958 "spi_sel", 26), 959 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", 960 "axi_sel", 27), 961 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", 962 "fufs_sel", 28), 963 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", 964 "faes_ufsfde_sel", 29), 965 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", 966 "fufs_sel", 30), 967 /* INFRA3 */ 968 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", 969 "msdc50_0_sel", 0), 970 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", 971 "msdc50_0_sel", 1), 972 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", 973 "msdc50_0_sel", 2), 974 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", 975 "axi_sel", 5), 976 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", 977 "i2c_sel", 6), 978 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", 979 "msdc50_hclk_sel", 7), 980 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", 981 "msdc50_hclk_sel", 8), 982 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", 983 "axi_sel", 16), 984 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", 985 "axi_sel", 17), 986 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", 987 "axi_sel", 18), 988 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", 989 "axi_sel", 19), 990 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", 991 "f_f26m_ck", 20), 992 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", 993 "axi_sel", 21), 994 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", 995 "i2c_sel", 22), 996 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", 997 "i2c_sel", 23), 998 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", 999 "msdc50_0_sel", 24), 1000 }; 1001 1002 static const struct mtk_gate_regs apmixed_cg_regs = { 1003 .set_ofs = 0x20, 1004 .clr_ofs = 0x20, 1005 .sta_ofs = 0x20, 1006 }; 1007 1008 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ 1009 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ 1010 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) 1011 1012 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 1013 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) 1014 1015 /* 1016 * CRITICAL CLOCK: 1017 * apmixed_appll26m is the toppest clock gate of all PLLs. 1018 */ 1019 static const struct mtk_gate apmixed_clks[] = { 1020 /* AUDIO0 */ 1021 GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", 1022 "f_f26m_ck", 4), 1023 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", 1024 "f_f26m_ck", 5, CLK_IS_CRITICAL), 1025 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", 1026 "f_f26m_ck", 6), 1027 GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", 1028 "f_f26m_ck", 7), 1029 GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", 1030 "f_f26m_ck", 8), 1031 GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", 1032 "f_f26m_ck", 9), 1033 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", 1034 "f_f26m_ck", 11), 1035 GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", 1036 "f_f26m_ck", 13), 1037 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 1038 "f_f26m_ck", 14), 1039 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", 1040 "f_f26m_ck", 16), 1041 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", 1042 "f_f26m_ck", 17), 1043 }; 1044 1045 #define MT8183_PLL_FMAX (3800UL * MHZ) 1046 #define MT8183_PLL_FMIN (1500UL * MHZ) 1047 1048 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1049 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1050 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1051 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1052 _pcw_chg_reg, _div_table) { \ 1053 .id = _id, \ 1054 .name = _name, \ 1055 .reg = _reg, \ 1056 .pwr_reg = _pwr_reg, \ 1057 .en_mask = _en_mask, \ 1058 .flags = _flags, \ 1059 .rst_bar_mask = _rst_bar_mask, \ 1060 .fmax = MT8183_PLL_FMAX, \ 1061 .fmin = MT8183_PLL_FMIN, \ 1062 .pcwbits = _pcwbits, \ 1063 .pcwibits = _pcwibits, \ 1064 .pd_reg = _pd_reg, \ 1065 .pd_shift = _pd_shift, \ 1066 .tuner_reg = _tuner_reg, \ 1067 .tuner_en_reg = _tuner_en_reg, \ 1068 .tuner_en_bit = _tuner_en_bit, \ 1069 .pcw_reg = _pcw_reg, \ 1070 .pcw_shift = _pcw_shift, \ 1071 .pcw_chg_reg = _pcw_chg_reg, \ 1072 .div_table = _div_table, \ 1073 } 1074 1075 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1076 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1077 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1078 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1079 _pcw_chg_reg) \ 1080 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1081 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1082 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1083 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1084 _pcw_chg_reg, NULL) 1085 1086 static const struct mtk_pll_div_table armpll_div_table[] = { 1087 { .div = 0, .freq = MT8183_PLL_FMAX }, 1088 { .div = 1, .freq = 1500 * MHZ }, 1089 { .div = 2, .freq = 750 * MHZ }, 1090 { .div = 3, .freq = 375 * MHZ }, 1091 { .div = 4, .freq = 187500000 }, 1092 { } /* sentinel */ 1093 }; 1094 1095 static const struct mtk_pll_div_table mfgpll_div_table[] = { 1096 { .div = 0, .freq = MT8183_PLL_FMAX }, 1097 { .div = 1, .freq = 1600 * MHZ }, 1098 { .div = 2, .freq = 800 * MHZ }, 1099 { .div = 3, .freq = 400 * MHZ }, 1100 { .div = 4, .freq = 200 * MHZ }, 1101 { } /* sentinel */ 1102 }; 1103 1104 static const struct mtk_pll_data plls[] = { 1105 PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001, 1106 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, 1107 0x0204, 0, 0, armpll_div_table), 1108 PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001, 1109 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, 1110 0x0214, 0, 0, armpll_div_table), 1111 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001, 1112 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, 1113 0x0294, 0, 0), 1114 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001, 1115 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, 1116 0x0224, 0, 0), 1117 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001, 1118 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, 1119 0x0234, 0, 0), 1120 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001, 1121 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, 1122 mfgpll_div_table), 1123 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001, 1124 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), 1125 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001, 1126 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), 1127 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001, 1128 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, 1129 0x0274, 0, 0), 1130 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001, 1131 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), 1132 PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001, 1133 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), 1134 }; 1135 1136 static int clk_mt8183_apmixed_probe(struct platform_device *pdev) 1137 { 1138 struct clk_onecell_data *clk_data; 1139 struct device_node *node = pdev->dev.of_node; 1140 1141 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1142 1143 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1144 1145 mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), 1146 clk_data); 1147 1148 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1149 } 1150 1151 static int clk_mt8183_top_probe(struct platform_device *pdev) 1152 { 1153 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1154 void __iomem *base; 1155 struct clk_onecell_data *clk_data; 1156 struct device_node *node = pdev->dev.of_node; 1157 1158 base = devm_ioremap_resource(&pdev->dev, res); 1159 if (IS_ERR(base)) 1160 return PTR_ERR(base); 1161 1162 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1163 1164 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 1165 clk_data); 1166 1167 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 1168 1169 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), 1170 node, &mt8183_clk_lock, clk_data); 1171 1172 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), 1173 base, &mt8183_clk_lock, clk_data); 1174 1175 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), 1176 base, &mt8183_clk_lock, clk_data); 1177 1178 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 1179 clk_data); 1180 1181 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1182 } 1183 1184 static int clk_mt8183_infra_probe(struct platform_device *pdev) 1185 { 1186 struct clk_onecell_data *clk_data; 1187 struct device_node *node = pdev->dev.of_node; 1188 1189 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1190 1191 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1192 clk_data); 1193 1194 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1195 } 1196 1197 static int clk_mt8183_mcu_probe(struct platform_device *pdev) 1198 { 1199 struct clk_onecell_data *clk_data; 1200 struct device_node *node = pdev->dev.of_node; 1201 void __iomem *base; 1202 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1203 1204 base = devm_ioremap_resource(&pdev->dev, res); 1205 if (IS_ERR(base)) 1206 return PTR_ERR(base); 1207 1208 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); 1209 1210 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, 1211 &mt8183_clk_lock, clk_data); 1212 1213 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1214 } 1215 1216 static const struct of_device_id of_match_clk_mt8183[] = { 1217 { 1218 .compatible = "mediatek,mt8183-apmixedsys", 1219 .data = clk_mt8183_apmixed_probe, 1220 }, { 1221 .compatible = "mediatek,mt8183-topckgen", 1222 .data = clk_mt8183_top_probe, 1223 }, { 1224 .compatible = "mediatek,mt8183-infracfg", 1225 .data = clk_mt8183_infra_probe, 1226 }, { 1227 .compatible = "mediatek,mt8183-mcucfg", 1228 .data = clk_mt8183_mcu_probe, 1229 }, { 1230 /* sentinel */ 1231 } 1232 }; 1233 1234 static int clk_mt8183_probe(struct platform_device *pdev) 1235 { 1236 int (*clk_probe)(struct platform_device *pdev); 1237 int r; 1238 1239 clk_probe = of_device_get_match_data(&pdev->dev); 1240 if (!clk_probe) 1241 return -EINVAL; 1242 1243 r = clk_probe(pdev); 1244 if (r) 1245 dev_err(&pdev->dev, 1246 "could not register clock provider: %s: %d\n", 1247 pdev->name, r); 1248 1249 return r; 1250 } 1251 1252 static struct platform_driver clk_mt8183_drv = { 1253 .probe = clk_mt8183_probe, 1254 .driver = { 1255 .name = "clk-mt8183", 1256 .of_match_table = of_match_clk_mt8183, 1257 }, 1258 }; 1259 1260 static int __init clk_mt8183_init(void) 1261 { 1262 return platform_driver_register(&clk_mt8183_drv); 1263 } 1264 1265 arch_initcall(clk_mt8183_init); 1266