1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2018 MediaTek Inc.
4 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
5 
6 #include <linux/delay.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 
12 #include "clk-gate.h"
13 #include "clk-mtk.h"
14 #include "clk-mux.h"
15 
16 #include <dt-bindings/clock/mt8183-clk.h>
17 
18 static DEFINE_SPINLOCK(mt8183_clk_lock);
19 
20 static const struct mtk_fixed_clk top_fixed_clks[] = {
21 	FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
22 	FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000),
23 	FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
24 };
25 
26 /*
27  * To retain compatibility with older devicetrees, we keep CLK_TOP_CLK13M
28  * valid, but renamed from "clk13m" (defined as fixed clock in the new
29  * devicetrees) to "clk26m_d2", satisfying the older clock assignments.
30  * This means that on new devicetrees "clk26m_d2" is unused.
31  */
32 static const struct mtk_fixed_factor top_divs[] = {
33 	FACTOR(CLK_TOP_CLK13M, "clk26m_d2", "clk26m", 1, 2),
34 	FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
35 	FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
36 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
37 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
38 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
39 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
40 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
41 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
42 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
43 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
44 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
45 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0),
46 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0),
47 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 4, 0),
48 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0),
49 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 2, 0),
50 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 4, 0),
51 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1, 0),
52 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2, 0),
53 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0),
54 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0),
55 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8, 0),
56 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
57 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0),
58 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0),
59 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0),
60 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
61 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
62 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
63 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
64 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
65 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 1, 0),
66 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 2, 0),
67 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 4, 0),
68 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 8, 0),
69 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 16, 0),
70 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 32, 0),
71 	FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
72 	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
73 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
74 	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
75 	FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
76 	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
77 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
78 	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
79 	FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
80 	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
81 	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
82 	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
83 	FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
84 	FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
85 	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
86 	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
87 	FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
88 	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
89 	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
90 	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
91 	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
92 	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
93 	FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
94 	FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
95 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
96 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
97 	FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
98 	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
99 	FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
100 	FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
101 	FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
102 	FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
103 	FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
104 	FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0),
105 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16, 0),
106 };
107 
108 static const char * const axi_parents[] = {
109 	"clk26m",
110 	"syspll_d2_d4",
111 	"syspll_d7",
112 	"osc_d4"
113 };
114 
115 static const char * const mm_parents[] = {
116 	"clk26m",
117 	"mmpll_d7",
118 	"syspll_d3",
119 	"univpll_d2_d2",
120 	"syspll_d2_d2",
121 	"syspll_d3_d2"
122 };
123 
124 static const char * const img_parents[] = {
125 	"clk26m",
126 	"mmpll_d6",
127 	"univpll_d3",
128 	"syspll_d3",
129 	"univpll_d2_d2",
130 	"syspll_d2_d2",
131 	"univpll_d3_d2",
132 	"syspll_d3_d2"
133 };
134 
135 static const char * const cam_parents[] = {
136 	"clk26m",
137 	"syspll_d2",
138 	"mmpll_d6",
139 	"syspll_d3",
140 	"mmpll_d7",
141 	"univpll_d3",
142 	"univpll_d2_d2",
143 	"syspll_d2_d2",
144 	"syspll_d3_d2",
145 	"univpll_d3_d2"
146 };
147 
148 static const char * const dsp_parents[] = {
149 	"clk26m",
150 	"mmpll_d6",
151 	"mmpll_d7",
152 	"univpll_d3",
153 	"syspll_d3",
154 	"univpll_d2_d2",
155 	"syspll_d2_d2",
156 	"univpll_d3_d2",
157 	"syspll_d3_d2"
158 };
159 
160 static const char * const dsp1_parents[] = {
161 	"clk26m",
162 	"mmpll_d6",
163 	"mmpll_d7",
164 	"univpll_d3",
165 	"syspll_d3",
166 	"univpll_d2_d2",
167 	"syspll_d2_d2",
168 	"univpll_d3_d2",
169 	"syspll_d3_d2"
170 };
171 
172 static const char * const dsp2_parents[] = {
173 	"clk26m",
174 	"mmpll_d6",
175 	"mmpll_d7",
176 	"univpll_d3",
177 	"syspll_d3",
178 	"univpll_d2_d2",
179 	"syspll_d2_d2",
180 	"univpll_d3_d2",
181 	"syspll_d3_d2"
182 };
183 
184 static const char * const ipu_if_parents[] = {
185 	"clk26m",
186 	"mmpll_d6",
187 	"mmpll_d7",
188 	"univpll_d3",
189 	"syspll_d3",
190 	"univpll_d2_d2",
191 	"syspll_d2_d2",
192 	"univpll_d3_d2",
193 	"syspll_d3_d2"
194 };
195 
196 static const char * const mfg_parents[] = {
197 	"clk26m",
198 	"mfgpll_ck",
199 	"univpll_d3",
200 	"syspll_d3"
201 };
202 
203 static const char * const f52m_mfg_parents[] = {
204 	"clk26m",
205 	"univpll_d3_d2",
206 	"univpll_d3_d4",
207 	"univpll_d3_d8"
208 };
209 
210 static const char * const camtg_parents[] = {
211 	"clk26m",
212 	"univ_192m_d8",
213 	"univpll_d3_d8",
214 	"univ_192m_d4",
215 	"univpll_d3_d16",
216 	"csw_f26m_ck_d2",
217 	"univ_192m_d16",
218 	"univ_192m_d32"
219 };
220 
221 static const char * const camtg2_parents[] = {
222 	"clk26m",
223 	"univ_192m_d8",
224 	"univpll_d3_d8",
225 	"univ_192m_d4",
226 	"univpll_d3_d16",
227 	"csw_f26m_ck_d2",
228 	"univ_192m_d16",
229 	"univ_192m_d32"
230 };
231 
232 static const char * const camtg3_parents[] = {
233 	"clk26m",
234 	"univ_192m_d8",
235 	"univpll_d3_d8",
236 	"univ_192m_d4",
237 	"univpll_d3_d16",
238 	"csw_f26m_ck_d2",
239 	"univ_192m_d16",
240 	"univ_192m_d32"
241 };
242 
243 static const char * const camtg4_parents[] = {
244 	"clk26m",
245 	"univ_192m_d8",
246 	"univpll_d3_d8",
247 	"univ_192m_d4",
248 	"univpll_d3_d16",
249 	"csw_f26m_ck_d2",
250 	"univ_192m_d16",
251 	"univ_192m_d32"
252 };
253 
254 static const char * const uart_parents[] = {
255 	"clk26m",
256 	"univpll_d3_d8"
257 };
258 
259 static const char * const spi_parents[] = {
260 	"clk26m",
261 	"syspll_d5_d2",
262 	"syspll_d3_d4",
263 	"msdcpll_d4"
264 };
265 
266 static const char * const msdc50_hclk_parents[] = {
267 	"clk26m",
268 	"syspll_d2_d2",
269 	"syspll_d3_d2"
270 };
271 
272 static const char * const msdc50_0_parents[] = {
273 	"clk26m",
274 	"msdcpll_ck",
275 	"msdcpll_d2",
276 	"univpll_d2_d4",
277 	"syspll_d3_d2",
278 	"univpll_d2_d2"
279 };
280 
281 static const char * const msdc30_1_parents[] = {
282 	"clk26m",
283 	"univpll_d3_d2",
284 	"syspll_d3_d2",
285 	"syspll_d7",
286 	"msdcpll_d2"
287 };
288 
289 static const char * const msdc30_2_parents[] = {
290 	"clk26m",
291 	"univpll_d3_d2",
292 	"syspll_d3_d2",
293 	"syspll_d7",
294 	"msdcpll_d2"
295 };
296 
297 static const char * const audio_parents[] = {
298 	"clk26m",
299 	"syspll_d5_d4",
300 	"syspll_d7_d4",
301 	"syspll_d2_d16"
302 };
303 
304 static const char * const aud_intbus_parents[] = {
305 	"clk26m",
306 	"syspll_d2_d4",
307 	"syspll_d7_d2"
308 };
309 
310 static const char * const pmicspi_parents[] = {
311 	"clk26m",
312 	"syspll_d2_d8",
313 	"osc_d8"
314 };
315 
316 static const char * const fpwrap_ulposc_parents[] = {
317 	"clk26m",
318 	"osc_d16",
319 	"osc_d4",
320 	"osc_d8"
321 };
322 
323 static const char * const atb_parents[] = {
324 	"clk26m",
325 	"syspll_d2_d2",
326 	"syspll_d5"
327 };
328 
329 static const char * const sspm_parents[] = {
330 	"clk26m",
331 	"univpll_d2_d4",
332 	"syspll_d2_d2",
333 	"univpll_d2_d2",
334 	"syspll_d3"
335 };
336 
337 static const char * const dpi0_parents[] = {
338 	"clk26m",
339 	"tvdpll_d2",
340 	"tvdpll_d4",
341 	"tvdpll_d8",
342 	"tvdpll_d16",
343 	"univpll_d5_d2",
344 	"univpll_d3_d4",
345 	"syspll_d3_d4",
346 	"univpll_d3_d8"
347 };
348 
349 static const char * const scam_parents[] = {
350 	"clk26m",
351 	"syspll_d5_d2"
352 };
353 
354 static const char * const disppwm_parents[] = {
355 	"clk26m",
356 	"univpll_d3_d4",
357 	"osc_d2",
358 	"osc_d4",
359 	"osc_d16"
360 };
361 
362 static const char * const usb_top_parents[] = {
363 	"clk26m",
364 	"univpll_d5_d4",
365 	"univpll_d3_d4",
366 	"univpll_d5_d2"
367 };
368 
369 
370 static const char * const ssusb_top_xhci_parents[] = {
371 	"clk26m",
372 	"univpll_d5_d4",
373 	"univpll_d3_d4",
374 	"univpll_d5_d2"
375 };
376 
377 static const char * const spm_parents[] = {
378 	"clk26m",
379 	"syspll_d2_d8"
380 };
381 
382 static const char * const i2c_parents[] = {
383 	"clk26m",
384 	"syspll_d2_d8",
385 	"univpll_d5_d2"
386 };
387 
388 static const char * const scp_parents[] = {
389 	"clk26m",
390 	"univpll_d2_d8",
391 	"syspll_d5",
392 	"syspll_d2_d2",
393 	"univpll_d2_d2",
394 	"syspll_d3",
395 	"univpll_d3"
396 };
397 
398 static const char * const seninf_parents[] = {
399 	"clk26m",
400 	"univpll_d2_d2",
401 	"univpll_d3_d2",
402 	"univpll_d2_d4"
403 };
404 
405 static const char * const dxcc_parents[] = {
406 	"clk26m",
407 	"syspll_d2_d2",
408 	"syspll_d2_d4",
409 	"syspll_d2_d8"
410 };
411 
412 static const char * const aud_engen1_parents[] = {
413 	"clk26m",
414 	"apll1_d2",
415 	"apll1_d4",
416 	"apll1_d8"
417 };
418 
419 static const char * const aud_engen2_parents[] = {
420 	"clk26m",
421 	"apll2_d2",
422 	"apll2_d4",
423 	"apll2_d8"
424 };
425 
426 static const char * const faes_ufsfde_parents[] = {
427 	"clk26m",
428 	"syspll_d2",
429 	"syspll_d2_d2",
430 	"syspll_d3",
431 	"syspll_d2_d4",
432 	"univpll_d3"
433 };
434 
435 static const char * const fufs_parents[] = {
436 	"clk26m",
437 	"syspll_d2_d4",
438 	"syspll_d2_d8",
439 	"syspll_d2_d16"
440 };
441 
442 static const char * const aud_1_parents[] = {
443 	"clk26m",
444 	"apll1_ck"
445 };
446 
447 static const char * const aud_2_parents[] = {
448 	"clk26m",
449 	"apll2_ck"
450 };
451 
452 /*
453  * CRITICAL CLOCK:
454  * axi_sel is the main bus clock of whole SOC.
455  * spm_sel is the clock of the always-on co-processor.
456  */
457 static const struct mtk_mux top_muxes[] = {
458 	/* CLK_CFG_0 */
459 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
460 		axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0,
461 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
462 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
463 		mm_parents, 0x40, 0x44, 0x48, 8, 3, 15, 0x004, 1),
464 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
465 		img_parents, 0x40, 0x44, 0x48, 16, 3, 23, 0x004, 2),
466 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
467 		cam_parents, 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 3),
468 	/* CLK_CFG_1 */
469 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
470 		dsp_parents, 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 4),
471 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
472 		dsp1_parents, 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 5),
473 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
474 		dsp2_parents, 0x50, 0x54, 0x58, 16, 4, 23, 0x004, 6),
475 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
476 		ipu_if_parents, 0x50, 0x54, 0x58, 24, 4, 31, 0x004, 7),
477 	/* CLK_CFG_2 */
478 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
479 		mfg_parents, 0x60, 0x64, 0x68, 0, 2, 7, 0x004, 8),
480 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
481 		f52m_mfg_parents, 0x60, 0x64, 0x68, 8, 2, 15, 0x004, 9),
482 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
483 		camtg_parents, 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 10),
484 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel",
485 		camtg2_parents, 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 11),
486 	/* CLK_CFG_3 */
487 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel",
488 		camtg3_parents, 0x70, 0x74, 0x78, 0, 3, 7, 0x004, 12),
489 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel",
490 		camtg4_parents, 0x70, 0x74, 0x78, 8, 3, 15, 0x004, 13),
491 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
492 		uart_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x004, 14),
493 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
494 		spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15),
495 	/* CLK_CFG_4 */
496 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
497 		msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16, 0),
498 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
499 		msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17, 0),
500 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
501 		msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18, 0),
502 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
503 		msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19, 0),
504 	/* CLK_CFG_5 */
505 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
506 		audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20),
507 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel",
508 		aud_intbus_parents, 0x90, 0x94, 0x98, 8, 2, 15, 0x004, 21),
509 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel",
510 		pmicspi_parents, 0x90, 0x94, 0x98, 16, 2, 23, 0x004, 22),
511 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
512 		fpwrap_ulposc_parents, 0x90, 0x94, 0x98, 24, 2, 31, 0x004, 23),
513 	/* CLK_CFG_6 */
514 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
515 		atb_parents, 0xa0, 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
516 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SSPM, "sspm_sel",
517 				   sspm_parents, 0xa0, 0xa4, 0xa8, 8, 3, 15, 0x004, 25,
518 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
519 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
520 		dpi0_parents, 0xa0, 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
521 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
522 		scam_parents, 0xa0, 0xa4, 0xa8, 24, 1, 31, 0x004, 27),
523 	/* CLK_CFG_7 */
524 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel",
525 		disppwm_parents, 0xb0, 0xb4, 0xb8, 0, 3, 7, 0x004, 28),
526 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel",
527 		usb_top_parents, 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x004, 29),
528 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
529 		ssusb_top_xhci_parents, 0xb0, 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
530 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
531 		spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0,
532 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
533 	/* CLK_CFG_8 */
534 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
535 		i2c_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
536 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel",
537 		scp_parents, 0xc0, 0xc4, 0xc8, 8, 3, 15, 0x008, 2),
538 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel",
539 		seninf_parents, 0xc0, 0xc4, 0xc8, 16, 2, 23, 0x008, 3),
540 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel",
541 		dxcc_parents, 0xc0, 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
542 	/* CLK_CFG_9 */
543 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel",
544 		aud_engen1_parents, 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 5),
545 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel",
546 		aud_engen2_parents, 0xd0, 0xd4, 0xd8, 8, 2, 15, 0x008, 6),
547 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel",
548 		faes_ufsfde_parents, 0xd0, 0xd4, 0xd8, 16, 3, 23, 0x008, 7),
549 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel",
550 		fufs_parents, 0xd0, 0xd4, 0xd8, 24, 2, 31, 0x008, 8),
551 	/* CLK_CFG_10 */
552 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
553 		aud_1_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
554 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
555 		aud_2_parents, 0xe0, 0xe4, 0xe8, 8, 1, 15, 0x008, 10),
556 };
557 
558 static const char * const apll_i2s0_parents[] = {
559 	"aud_1_sel",
560 	"aud_2_sel"
561 };
562 
563 static const char * const apll_i2s1_parents[] = {
564 	"aud_1_sel",
565 	"aud_2_sel"
566 };
567 
568 static const char * const apll_i2s2_parents[] = {
569 	"aud_1_sel",
570 	"aud_2_sel"
571 };
572 
573 static const char * const apll_i2s3_parents[] = {
574 	"aud_1_sel",
575 	"aud_2_sel"
576 };
577 
578 static const char * const apll_i2s4_parents[] = {
579 	"aud_1_sel",
580 	"aud_2_sel"
581 };
582 
583 static const char * const apll_i2s5_parents[] = {
584 	"aud_1_sel",
585 	"aud_2_sel"
586 };
587 
588 static const char * const mcu_mp0_parents[] = {
589 	"clk26m",
590 	"armpll_ll",
591 	"armpll_div_pll1",
592 	"armpll_div_pll2"
593 };
594 
595 static const char * const mcu_mp2_parents[] = {
596 	"clk26m",
597 	"armpll_l",
598 	"armpll_div_pll1",
599 	"armpll_div_pll2"
600 };
601 
602 static const char * const mcu_bus_parents[] = {
603 	"clk26m",
604 	"ccipll",
605 	"armpll_div_pll1",
606 	"armpll_div_pll2"
607 };
608 
609 static struct mtk_composite mcu_muxes[] = {
610 	/* mp0_pll_divider_cfg */
611 	MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
612 	/* mp2_pll_divider_cfg */
613 	MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2),
614 	/* bus_pll_divider_cfg */
615 	MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
616 };
617 
618 static struct mtk_composite top_aud_comp[] = {
619 	MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 0x320, 8, 1),
620 	MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 0x320, 9, 1),
621 	MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 0x320, 10, 1),
622 	MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 0x320, 11, 1),
623 	MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 0x320, 12, 1),
624 	MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 0x328, 20, 1),
625 	DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 0x320, 2, 0x324, 8, 0),
626 	DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 0x320, 3, 0x324, 8, 8),
627 	DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 0x320, 4, 0x324, 8, 16),
628 	DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 0x320, 5, 0x324, 8, 24),
629 	DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 0x320, 6, 0x328, 8, 0),
630 	DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 7, 0x328, 8, 8),
631 };
632 
633 static const struct mtk_gate_regs top_cg_regs = {
634 	.set_ofs = 0x104,
635 	.clr_ofs = 0x104,
636 	.sta_ofs = 0x104,
637 };
638 
639 #define GATE_TOP(_id, _name, _parent, _shift)			\
640 	GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift,	\
641 		&mtk_clk_gate_ops_no_setclr_inv)
642 
643 static const struct mtk_gate top_clks[] = {
644 	/* TOP */
645 	GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),
646 	GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5),
647 };
648 
649 static const struct mtk_gate_regs infra0_cg_regs = {
650 	.set_ofs = 0x80,
651 	.clr_ofs = 0x84,
652 	.sta_ofs = 0x90,
653 };
654 
655 static const struct mtk_gate_regs infra1_cg_regs = {
656 	.set_ofs = 0x88,
657 	.clr_ofs = 0x8c,
658 	.sta_ofs = 0x94,
659 };
660 
661 static const struct mtk_gate_regs infra2_cg_regs = {
662 	.set_ofs = 0xa4,
663 	.clr_ofs = 0xa8,
664 	.sta_ofs = 0xac,
665 };
666 
667 static const struct mtk_gate_regs infra3_cg_regs = {
668 	.set_ofs = 0xc0,
669 	.clr_ofs = 0xc4,
670 	.sta_ofs = 0xc8,
671 };
672 
673 #define GATE_INFRA0(_id, _name, _parent, _shift)		\
674 	GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift,	\
675 		&mtk_clk_gate_ops_setclr)
676 
677 #define GATE_INFRA1(_id, _name, _parent, _shift)		\
678 	GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift,	\
679 		&mtk_clk_gate_ops_setclr)
680 
681 #define GATE_INFRA2(_id, _name, _parent, _shift)		\
682 	GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift,	\
683 		&mtk_clk_gate_ops_setclr)
684 
685 #define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flag)	\
686 	GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, 	\
687 		       _shift, &mtk_clk_gate_ops_setclr, _flag)
688 
689 #define GATE_INFRA3(_id, _name, _parent, _shift)		\
690 	GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift,	\
691 		&mtk_clk_gate_ops_setclr)
692 
693 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag)	\
694 	GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, 	\
695 		       _shift, &mtk_clk_gate_ops_setclr, _flag)
696 
697 static const struct mtk_gate infra_clks[] = {
698 	/* INFRA0 */
699 	GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0),
700 	GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "axi_sel", 1),
701 	GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "axi_sel", 2),
702 	GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "axi_sel", 3),
703 	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", "scp_sel", 4),
704 	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "f_f26m_ck", 5),
705 	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
706 	GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", "axi_sel", 8),
707 	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
708 	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
709 	GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11),
710 	GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", "i2c_sel", 12),
711 	GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13),
712 	GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14),
713 	GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
714 	GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "i2c_sel", 16),
715 	GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "i2c_sel", 17),
716 	GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "i2c_sel", 18),
717 	GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "i2c_sel", 19),
718 	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "i2c_sel", 21),
719 	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
720 	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
721 	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
722 	GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
723 	GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27),
724 	GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", "axi_sel", 28),
725 	GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
726 	/* INFRA1 */
727 	GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1),
728 	GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_hclk_sel", 2),
729 	GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "axi_sel", 4),
730 	GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "axi_sel", 5),
731 	GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", "msdc50_0_sel", 6),
732 	GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", "f_f26m_ck", 7),
733 	GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
734 	GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
735 	GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "f_f26m_ck", 10),
736 	GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
737 	GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12),
738 	GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13),
739 	GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "f_f26m_ck", 14),
740 	GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", "msdc30_1_sel", 16),
741 	GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", "msdc30_2_sel", 17),
742 	GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", "axi_sel", 18),
743 	GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", "axi_sel", 19),
744 	GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
745 	GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
746 	GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24),
747 	GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
748 	GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
749 	GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27),
750 	GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28),
751 	GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", "axi_sel", 30),
752 	GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "f_f26m_ck", 31),
753 	/* INFRA2 */
754 	GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "f_f26m_ck", 0),
755 	GATE_INFRA2(CLK_INFRA_USB, "infra_usb", "usb_top_sel", 1),
756 	GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", "axi_sel", 2),
757 	GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", "axi_sel", 3),
758 	GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", "f_f26m_ck", 4),
759 	GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6),
760 	GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7),
761 	GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", "f_f26m_ck", 8),
762 	GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9),
763 	GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10),
764 	GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", "ssusb_top_xhci_sel", 11),
765 	GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "fufs_sel", 12),
766 	GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", "fufs_sel", 13),
767 	GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14),
768 	/* infra_sspm is main clock in co-processor, should not be closed in Linux. */
769 	GATE_INFRA2_FLAGS(CLK_INFRA_SSPM, "infra_sspm", "sspm_sel", 15, CLK_IS_CRITICAL),
770 	GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16),
771 	/* infra_sspm_bus_hclk is main clock in co-processor, should not be closed in Linux. */
772 	GATE_INFRA2_FLAGS(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk", "axi_sel", 17, CLK_IS_CRITICAL),
773 	GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18),
774 	GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19),
775 	GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20),
776 	GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21),
777 	GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22),
778 	GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23),
779 	GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24),
780 	GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25),
781 	GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26),
782 	GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", "axi_sel", 27),
783 	GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "fufs_sel", 28),
784 	GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "faes_ufsfde_sel", 29),
785 	GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "fufs_sel", 30),
786 	/* INFRA3 */
787 	GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0),
788 	GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1),
789 	GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2),
790 	/* infra_sspm_26m_self is main clock in co-processor, should not be closed in Linux. */
791 	GATE_INFRA3_FLAGS(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self", "f_f26m_ck", 3, CLK_IS_CRITICAL),
792 	/* infra_sspm_32k_self is main clock in co-processor, should not be closed in Linux. */
793 	GATE_INFRA3_FLAGS(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self", "f_f26m_ck", 4, CLK_IS_CRITICAL),
794 	GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5),
795 	GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6),
796 	GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_hclk_sel", 7),
797 	GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_hclk_sel", 8),
798 	GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16),
799 	GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17),
800 	GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18),
801 	GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19),
802 	GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "f_f26m_ck", 20),
803 	GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", "axi_sel", 21),
804 	GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22),
805 	GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23),
806 	GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24),
807 };
808 
809 static const struct mtk_gate_regs peri_cg_regs = {
810 	.set_ofs = 0x20c,
811 	.clr_ofs = 0x20c,
812 	.sta_ofs = 0x20c,
813 };
814 
815 #define GATE_PERI(_id, _name, _parent, _shift)			\
816 	GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift,	\
817 		&mtk_clk_gate_ops_no_setclr_inv)
818 
819 static const struct mtk_gate peri_clks[] = {
820 	GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
821 };
822 
823 static u16 infra_rst_ofs[] = {
824 	INFRA_RST0_SET_OFFSET,
825 	INFRA_RST1_SET_OFFSET,
826 	INFRA_RST2_SET_OFFSET,
827 	INFRA_RST3_SET_OFFSET,
828 };
829 
830 static const struct mtk_clk_rst_desc clk_rst_desc = {
831 	.version = MTK_RST_SET_CLR,
832 	.rst_bank_ofs = infra_rst_ofs,
833 	.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
834 };
835 
836 /* Register mux notifier for MFG mux */
837 static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
838 {
839 	struct mtk_mux_nb *mfg_mux_nb;
840 	int i;
841 
842 	mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
843 	if (!mfg_mux_nb)
844 		return -ENOMEM;
845 
846 	for (i = 0; i < ARRAY_SIZE(top_muxes); i++)
847 		if (top_muxes[i].id == CLK_TOP_MUX_MFG)
848 			break;
849 	if (i == ARRAY_SIZE(top_muxes))
850 		return -EINVAL;
851 
852 	mfg_mux_nb->ops = top_muxes[i].ops;
853 	mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
854 
855 	return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
856 }
857 
858 static const struct mtk_clk_desc infra_desc = {
859 	.clks = infra_clks,
860 	.num_clks = ARRAY_SIZE(infra_clks),
861 	.rst_desc = &clk_rst_desc,
862 };
863 
864 static const struct mtk_clk_desc mcu_desc = {
865 	.composite_clks = mcu_muxes,
866 	.num_composite_clks = ARRAY_SIZE(mcu_muxes),
867 	.clk_lock = &mt8183_clk_lock,
868 };
869 
870 static const struct mtk_clk_desc peri_desc = {
871 	.clks = peri_clks,
872 	.num_clks = ARRAY_SIZE(peri_clks),
873 };
874 
875 static const struct mtk_clk_desc topck_desc = {
876 	.fixed_clks = top_fixed_clks,
877 	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
878 	.factor_clks = top_divs,
879 	.num_factor_clks = ARRAY_SIZE(top_divs),
880 	.mux_clks = top_muxes,
881 	.num_mux_clks = ARRAY_SIZE(top_muxes),
882 	.composite_clks = top_aud_comp,
883 	.num_composite_clks = ARRAY_SIZE(top_aud_comp),
884 	.clks = top_clks,
885 	.num_clks = ARRAY_SIZE(top_clks),
886 	.clk_lock = &mt8183_clk_lock,
887 	.clk_notifier_func = clk_mt8183_reg_mfg_mux_notifier,
888 	.mfg_clk_idx = CLK_TOP_MUX_MFG,
889 };
890 
891 static const struct of_device_id of_match_clk_mt8183[] = {
892 	{ .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc },
893 	{ .compatible = "mediatek,mt8183-mcucfg", .data = &mcu_desc },
894 	{ .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, },
895 	{ .compatible = "mediatek,mt8183-topckgen", .data = &topck_desc },
896 	{ /* sentinel */ }
897 };
898 MODULE_DEVICE_TABLE(of, of_match_clk_mt8183);
899 
900 static struct platform_driver clk_mt8183_drv = {
901 	.probe = mtk_clk_simple_probe,
902 	.remove_new = mtk_clk_simple_remove,
903 	.driver = {
904 		.name = "clk-mt8183",
905 		.of_match_table = of_match_clk_mt8183,
906 	},
907 };
908 module_platform_driver(clk_mt8183_drv)
909 MODULE_LICENSE("GPL");
910