1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 6 #include <linux/delay.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 14 #include "clk-gate.h" 15 #include "clk-mtk.h" 16 #include "clk-mux.h" 17 #include "clk-pll.h" 18 19 #include <dt-bindings/clock/mt8183-clk.h> 20 21 /* Infra global controller reset set register */ 22 #define INFRA_RST0_SET_OFFSET 0x120 23 24 static DEFINE_SPINLOCK(mt8183_clk_lock); 25 26 static const struct mtk_fixed_clk top_fixed_clks[] = { 27 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 28 FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 29 FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 30 }; 31 32 static const struct mtk_fixed_factor top_early_divs[] = { 33 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), 34 }; 35 36 static const struct mtk_fixed_factor top_divs[] = { 37 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 38 2), 39 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 40 1), 41 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 42 2), 43 FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 44 2), 45 FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 46 4), 47 FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 48 8), 49 FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 50 16), 51 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 52 3), 53 FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 54 2), 55 FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 56 4), 57 FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 58 8), 59 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 60 5), 61 FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 62 2), 63 FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 64 4), 65 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 66 7), 67 FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 68 2), 69 FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 70 4), 71 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 72 1), 73 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 74 2), 75 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 76 2), 77 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 78 4), 79 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 80 8), 81 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 82 3), 83 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 84 2), 85 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 86 4), 87 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 88 8), 89 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 90 5), 91 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 92 2), 93 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 94 4), 95 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 96 8), 97 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 98 7), 99 FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 100 1), 101 FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 102 2), 103 FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 104 4), 105 FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 106 8), 107 FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 108 16), 109 FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 110 32), 111 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 112 1), 113 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 114 2), 115 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 116 4), 117 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 118 8), 119 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 120 1), 121 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 122 2), 123 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 124 4), 125 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 126 8), 127 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 128 1), 129 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 130 2), 131 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 132 4), 133 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 134 8), 135 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 136 16), 137 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 138 1), 139 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 140 4), 141 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 142 2), 143 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 144 4), 145 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 146 5), 147 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 148 2), 149 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 150 4), 151 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 152 6), 153 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 154 7), 155 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 156 1), 157 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 158 1), 159 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 160 2), 161 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 162 4), 163 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 164 8), 165 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 166 16), 167 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 168 1), 169 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 170 2), 171 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 172 4), 173 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 174 8), 175 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 176 16), 177 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 178 2), 179 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 180 16), 181 }; 182 183 static const char * const axi_parents[] = { 184 "clk26m", 185 "syspll_d2_d4", 186 "syspll_d7", 187 "osc_d4" 188 }; 189 190 static const char * const mm_parents[] = { 191 "clk26m", 192 "mmpll_d7", 193 "syspll_d3", 194 "univpll_d2_d2", 195 "syspll_d2_d2", 196 "syspll_d3_d2" 197 }; 198 199 static const char * const img_parents[] = { 200 "clk26m", 201 "mmpll_d6", 202 "univpll_d3", 203 "syspll_d3", 204 "univpll_d2_d2", 205 "syspll_d2_d2", 206 "univpll_d3_d2", 207 "syspll_d3_d2" 208 }; 209 210 static const char * const cam_parents[] = { 211 "clk26m", 212 "syspll_d2", 213 "mmpll_d6", 214 "syspll_d3", 215 "mmpll_d7", 216 "univpll_d3", 217 "univpll_d2_d2", 218 "syspll_d2_d2", 219 "syspll_d3_d2", 220 "univpll_d3_d2" 221 }; 222 223 static const char * const dsp_parents[] = { 224 "clk26m", 225 "mmpll_d6", 226 "mmpll_d7", 227 "univpll_d3", 228 "syspll_d3", 229 "univpll_d2_d2", 230 "syspll_d2_d2", 231 "univpll_d3_d2", 232 "syspll_d3_d2" 233 }; 234 235 static const char * const dsp1_parents[] = { 236 "clk26m", 237 "mmpll_d6", 238 "mmpll_d7", 239 "univpll_d3", 240 "syspll_d3", 241 "univpll_d2_d2", 242 "syspll_d2_d2", 243 "univpll_d3_d2", 244 "syspll_d3_d2" 245 }; 246 247 static const char * const dsp2_parents[] = { 248 "clk26m", 249 "mmpll_d6", 250 "mmpll_d7", 251 "univpll_d3", 252 "syspll_d3", 253 "univpll_d2_d2", 254 "syspll_d2_d2", 255 "univpll_d3_d2", 256 "syspll_d3_d2" 257 }; 258 259 static const char * const ipu_if_parents[] = { 260 "clk26m", 261 "mmpll_d6", 262 "mmpll_d7", 263 "univpll_d3", 264 "syspll_d3", 265 "univpll_d2_d2", 266 "syspll_d2_d2", 267 "univpll_d3_d2", 268 "syspll_d3_d2" 269 }; 270 271 static const char * const mfg_parents[] = { 272 "clk26m", 273 "mfgpll_ck", 274 "univpll_d3", 275 "syspll_d3" 276 }; 277 278 static const char * const f52m_mfg_parents[] = { 279 "clk26m", 280 "univpll_d3_d2", 281 "univpll_d3_d4", 282 "univpll_d3_d8" 283 }; 284 285 static const char * const camtg_parents[] = { 286 "clk26m", 287 "univ_192m_d8", 288 "univpll_d3_d8", 289 "univ_192m_d4", 290 "univpll_d3_d16", 291 "csw_f26m_ck_d2", 292 "univ_192m_d16", 293 "univ_192m_d32" 294 }; 295 296 static const char * const camtg2_parents[] = { 297 "clk26m", 298 "univ_192m_d8", 299 "univpll_d3_d8", 300 "univ_192m_d4", 301 "univpll_d3_d16", 302 "csw_f26m_ck_d2", 303 "univ_192m_d16", 304 "univ_192m_d32" 305 }; 306 307 static const char * const camtg3_parents[] = { 308 "clk26m", 309 "univ_192m_d8", 310 "univpll_d3_d8", 311 "univ_192m_d4", 312 "univpll_d3_d16", 313 "csw_f26m_ck_d2", 314 "univ_192m_d16", 315 "univ_192m_d32" 316 }; 317 318 static const char * const camtg4_parents[] = { 319 "clk26m", 320 "univ_192m_d8", 321 "univpll_d3_d8", 322 "univ_192m_d4", 323 "univpll_d3_d16", 324 "csw_f26m_ck_d2", 325 "univ_192m_d16", 326 "univ_192m_d32" 327 }; 328 329 static const char * const uart_parents[] = { 330 "clk26m", 331 "univpll_d3_d8" 332 }; 333 334 static const char * const spi_parents[] = { 335 "clk26m", 336 "syspll_d5_d2", 337 "syspll_d3_d4", 338 "msdcpll_d4" 339 }; 340 341 static const char * const msdc50_hclk_parents[] = { 342 "clk26m", 343 "syspll_d2_d2", 344 "syspll_d3_d2" 345 }; 346 347 static const char * const msdc50_0_parents[] = { 348 "clk26m", 349 "msdcpll_ck", 350 "msdcpll_d2", 351 "univpll_d2_d4", 352 "syspll_d3_d2", 353 "univpll_d2_d2" 354 }; 355 356 static const char * const msdc30_1_parents[] = { 357 "clk26m", 358 "univpll_d3_d2", 359 "syspll_d3_d2", 360 "syspll_d7", 361 "msdcpll_d2" 362 }; 363 364 static const char * const msdc30_2_parents[] = { 365 "clk26m", 366 "univpll_d3_d2", 367 "syspll_d3_d2", 368 "syspll_d7", 369 "msdcpll_d2" 370 }; 371 372 static const char * const audio_parents[] = { 373 "clk26m", 374 "syspll_d5_d4", 375 "syspll_d7_d4", 376 "syspll_d2_d16" 377 }; 378 379 static const char * const aud_intbus_parents[] = { 380 "clk26m", 381 "syspll_d2_d4", 382 "syspll_d7_d2" 383 }; 384 385 static const char * const pmicspi_parents[] = { 386 "clk26m", 387 "syspll_d2_d8", 388 "osc_d8" 389 }; 390 391 static const char * const fpwrap_ulposc_parents[] = { 392 "clk26m", 393 "osc_d16", 394 "osc_d4", 395 "osc_d8" 396 }; 397 398 static const char * const atb_parents[] = { 399 "clk26m", 400 "syspll_d2_d2", 401 "syspll_d5" 402 }; 403 404 static const char * const dpi0_parents[] = { 405 "clk26m", 406 "tvdpll_d2", 407 "tvdpll_d4", 408 "tvdpll_d8", 409 "tvdpll_d16", 410 "univpll_d5_d2", 411 "univpll_d3_d4", 412 "syspll_d3_d4", 413 "univpll_d3_d8" 414 }; 415 416 static const char * const scam_parents[] = { 417 "clk26m", 418 "syspll_d5_d2" 419 }; 420 421 static const char * const disppwm_parents[] = { 422 "clk26m", 423 "univpll_d3_d4", 424 "osc_d2", 425 "osc_d4", 426 "osc_d16" 427 }; 428 429 static const char * const usb_top_parents[] = { 430 "clk26m", 431 "univpll_d5_d4", 432 "univpll_d3_d4", 433 "univpll_d5_d2" 434 }; 435 436 437 static const char * const ssusb_top_xhci_parents[] = { 438 "clk26m", 439 "univpll_d5_d4", 440 "univpll_d3_d4", 441 "univpll_d5_d2" 442 }; 443 444 static const char * const spm_parents[] = { 445 "clk26m", 446 "syspll_d2_d8" 447 }; 448 449 static const char * const i2c_parents[] = { 450 "clk26m", 451 "syspll_d2_d8", 452 "univpll_d5_d2" 453 }; 454 455 static const char * const scp_parents[] = { 456 "clk26m", 457 "univpll_d2_d8", 458 "syspll_d5", 459 "syspll_d2_d2", 460 "univpll_d2_d2", 461 "syspll_d3", 462 "univpll_d3" 463 }; 464 465 static const char * const seninf_parents[] = { 466 "clk26m", 467 "univpll_d2_d2", 468 "univpll_d3_d2", 469 "univpll_d2_d4" 470 }; 471 472 static const char * const dxcc_parents[] = { 473 "clk26m", 474 "syspll_d2_d2", 475 "syspll_d2_d4", 476 "syspll_d2_d8" 477 }; 478 479 static const char * const aud_engen1_parents[] = { 480 "clk26m", 481 "apll1_d2", 482 "apll1_d4", 483 "apll1_d8" 484 }; 485 486 static const char * const aud_engen2_parents[] = { 487 "clk26m", 488 "apll2_d2", 489 "apll2_d4", 490 "apll2_d8" 491 }; 492 493 static const char * const faes_ufsfde_parents[] = { 494 "clk26m", 495 "syspll_d2", 496 "syspll_d2_d2", 497 "syspll_d3", 498 "syspll_d2_d4", 499 "univpll_d3" 500 }; 501 502 static const char * const fufs_parents[] = { 503 "clk26m", 504 "syspll_d2_d4", 505 "syspll_d2_d8", 506 "syspll_d2_d16" 507 }; 508 509 static const char * const aud_1_parents[] = { 510 "clk26m", 511 "apll1_ck" 512 }; 513 514 static const char * const aud_2_parents[] = { 515 "clk26m", 516 "apll2_ck" 517 }; 518 519 /* 520 * CRITICAL CLOCK: 521 * axi_sel is the main bus clock of whole SOC. 522 * spm_sel is the clock of the always-on co-processor. 523 */ 524 static const struct mtk_mux top_muxes[] = { 525 /* CLK_CFG_0 */ 526 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 527 axi_parents, 0x40, 528 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), 529 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 530 mm_parents, 0x40, 531 0x44, 0x48, 8, 3, 15, 0x004, 1), 532 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 533 img_parents, 0x40, 534 0x44, 0x48, 16, 3, 23, 0x004, 2), 535 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 536 cam_parents, 0x40, 537 0x44, 0x48, 24, 4, 31, 0x004, 3), 538 /* CLK_CFG_1 */ 539 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 540 dsp_parents, 0x50, 541 0x54, 0x58, 0, 4, 7, 0x004, 4), 542 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 543 dsp1_parents, 0x50, 544 0x54, 0x58, 8, 4, 15, 0x004, 5), 545 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 546 dsp2_parents, 0x50, 547 0x54, 0x58, 16, 4, 23, 0x004, 6), 548 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 549 ipu_if_parents, 0x50, 550 0x54, 0x58, 24, 4, 31, 0x004, 7), 551 /* CLK_CFG_2 */ 552 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 553 mfg_parents, 0x60, 554 0x64, 0x68, 0, 2, 7, 0x004, 8), 555 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 556 f52m_mfg_parents, 0x60, 557 0x64, 0x68, 8, 2, 15, 0x004, 9), 558 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 559 camtg_parents, 0x60, 560 0x64, 0x68, 16, 3, 23, 0x004, 10), 561 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 562 camtg2_parents, 0x60, 563 0x64, 0x68, 24, 3, 31, 0x004, 11), 564 /* CLK_CFG_3 */ 565 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 566 camtg3_parents, 0x70, 567 0x74, 0x78, 0, 3, 7, 0x004, 12), 568 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 569 camtg4_parents, 0x70, 570 0x74, 0x78, 8, 3, 15, 0x004, 13), 571 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 572 uart_parents, 0x70, 573 0x74, 0x78, 16, 1, 23, 0x004, 14), 574 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 575 spi_parents, 0x70, 576 0x74, 0x78, 24, 2, 31, 0x004, 15), 577 /* CLK_CFG_4 */ 578 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 579 msdc50_hclk_parents, 0x80, 580 0x84, 0x88, 0, 2, 7, 0x004, 16), 581 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 582 msdc50_0_parents, 0x80, 583 0x84, 0x88, 8, 3, 15, 0x004, 17), 584 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 585 msdc30_1_parents, 0x80, 586 0x84, 0x88, 16, 3, 23, 0x004, 18), 587 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 588 msdc30_2_parents, 0x80, 589 0x84, 0x88, 24, 3, 31, 0x004, 19), 590 /* CLK_CFG_5 */ 591 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 592 audio_parents, 0x90, 593 0x94, 0x98, 0, 2, 7, 0x004, 20), 594 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 595 aud_intbus_parents, 0x90, 596 0x94, 0x98, 8, 2, 15, 0x004, 21), 597 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 598 pmicspi_parents, 0x90, 599 0x94, 0x98, 16, 2, 23, 0x004, 22), 600 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 601 fpwrap_ulposc_parents, 0x90, 602 0x94, 0x98, 24, 2, 31, 0x004, 23), 603 /* CLK_CFG_6 */ 604 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 605 atb_parents, 0xa0, 606 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 607 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 608 dpi0_parents, 0xa0, 609 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 610 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 611 scam_parents, 0xa0, 612 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 613 /* CLK_CFG_7 */ 614 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 615 disppwm_parents, 0xb0, 616 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 617 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 618 usb_top_parents, 0xb0, 619 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 620 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 621 ssusb_top_xhci_parents, 0xb0, 622 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 623 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 624 spm_parents, 0xb0, 625 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), 626 /* CLK_CFG_8 */ 627 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 628 i2c_parents, 0xc0, 629 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 630 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 631 scp_parents, 0xc0, 632 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 633 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 634 seninf_parents, 0xc0, 635 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 636 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 637 dxcc_parents, 0xc0, 638 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 639 /* CLK_CFG_9 */ 640 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 641 aud_engen1_parents, 0xd0, 642 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 643 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 644 aud_engen2_parents, 0xd0, 645 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 646 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 647 faes_ufsfde_parents, 0xd0, 648 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 649 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 650 fufs_parents, 0xd0, 651 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 652 /* CLK_CFG_10 */ 653 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 654 aud_1_parents, 0xe0, 655 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 656 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 657 aud_2_parents, 0xe0, 658 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 659 }; 660 661 static const char * const apll_i2s0_parents[] = { 662 "aud_1_sel", 663 "aud_2_sel" 664 }; 665 666 static const char * const apll_i2s1_parents[] = { 667 "aud_1_sel", 668 "aud_2_sel" 669 }; 670 671 static const char * const apll_i2s2_parents[] = { 672 "aud_1_sel", 673 "aud_2_sel" 674 }; 675 676 static const char * const apll_i2s3_parents[] = { 677 "aud_1_sel", 678 "aud_2_sel" 679 }; 680 681 static const char * const apll_i2s4_parents[] = { 682 "aud_1_sel", 683 "aud_2_sel" 684 }; 685 686 static const char * const apll_i2s5_parents[] = { 687 "aud_1_sel", 688 "aud_2_sel" 689 }; 690 691 static struct mtk_composite top_aud_muxes[] = { 692 MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 693 0x320, 8, 1), 694 MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 695 0x320, 9, 1), 696 MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 697 0x320, 10, 1), 698 MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 699 0x320, 11, 1), 700 MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 701 0x320, 12, 1), 702 MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 703 0x328, 20, 1), 704 }; 705 706 static const char * const mcu_mp0_parents[] = { 707 "clk26m", 708 "armpll_ll", 709 "armpll_div_pll1", 710 "armpll_div_pll2" 711 }; 712 713 static const char * const mcu_mp2_parents[] = { 714 "clk26m", 715 "armpll_l", 716 "armpll_div_pll1", 717 "armpll_div_pll2" 718 }; 719 720 static const char * const mcu_bus_parents[] = { 721 "clk26m", 722 "ccipll", 723 "armpll_div_pll1", 724 "armpll_div_pll2" 725 }; 726 727 static struct mtk_composite mcu_muxes[] = { 728 /* mp0_pll_divider_cfg */ 729 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 730 /* mp2_pll_divider_cfg */ 731 MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 732 /* bus_pll_divider_cfg */ 733 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 734 }; 735 736 static struct mtk_composite top_aud_divs[] = { 737 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 738 0x320, 2, 0x324, 8, 0), 739 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 740 0x320, 3, 0x324, 8, 8), 741 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 742 0x320, 4, 0x324, 8, 16), 743 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 744 0x320, 5, 0x324, 8, 24), 745 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 746 0x320, 6, 0x328, 8, 0), 747 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 748 0x320, 7, 0x328, 8, 8), 749 }; 750 751 static const struct mtk_gate_regs top_cg_regs = { 752 .set_ofs = 0x104, 753 .clr_ofs = 0x104, 754 .sta_ofs = 0x104, 755 }; 756 757 #define GATE_TOP(_id, _name, _parent, _shift) \ 758 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 759 &mtk_clk_gate_ops_no_setclr_inv) 760 761 static const struct mtk_gate top_clks[] = { 762 /* TOP */ 763 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 764 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 765 }; 766 767 static const struct mtk_gate_regs infra0_cg_regs = { 768 .set_ofs = 0x80, 769 .clr_ofs = 0x84, 770 .sta_ofs = 0x90, 771 }; 772 773 static const struct mtk_gate_regs infra1_cg_regs = { 774 .set_ofs = 0x88, 775 .clr_ofs = 0x8c, 776 .sta_ofs = 0x94, 777 }; 778 779 static const struct mtk_gate_regs infra2_cg_regs = { 780 .set_ofs = 0xa4, 781 .clr_ofs = 0xa8, 782 .sta_ofs = 0xac, 783 }; 784 785 static const struct mtk_gate_regs infra3_cg_regs = { 786 .set_ofs = 0xc0, 787 .clr_ofs = 0xc4, 788 .sta_ofs = 0xc8, 789 }; 790 791 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 792 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 793 &mtk_clk_gate_ops_setclr) 794 795 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 796 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 797 &mtk_clk_gate_ops_setclr) 798 799 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 800 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 801 &mtk_clk_gate_ops_setclr) 802 803 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 804 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 805 &mtk_clk_gate_ops_setclr) 806 807 static const struct mtk_gate infra_clks[] = { 808 /* INFRA0 */ 809 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 810 "axi_sel", 0), 811 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 812 "axi_sel", 1), 813 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 814 "axi_sel", 2), 815 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", 816 "axi_sel", 3), 817 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", 818 "scp_sel", 4), 819 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", 820 "f_f26m_ck", 5), 821 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", 822 "axi_sel", 6), 823 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", 824 "axi_sel", 8), 825 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", 826 "axi_sel", 9), 827 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", 828 "axi_sel", 10), 829 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", 830 "i2c_sel", 11), 831 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", 832 "i2c_sel", 12), 833 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", 834 "i2c_sel", 13), 835 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", 836 "i2c_sel", 14), 837 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", 838 "axi_sel", 15), 839 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", 840 "i2c_sel", 16), 841 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", 842 "i2c_sel", 17), 843 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", 844 "i2c_sel", 18), 845 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", 846 "i2c_sel", 19), 847 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 848 "i2c_sel", 21), 849 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 850 "uart_sel", 22), 851 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 852 "uart_sel", 23), 853 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", 854 "uart_sel", 24), 855 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", 856 "uart_sel", 25), 857 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", 858 "axi_sel", 27), 859 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", 860 "axi_sel", 28), 861 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", 862 "axi_sel", 31), 863 /* INFRA1 */ 864 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", 865 "spi_sel", 1), 866 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", 867 "msdc50_hclk_sel", 2), 868 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", 869 "axi_sel", 4), 870 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", 871 "axi_sel", 5), 872 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", 873 "msdc50_0_sel", 6), 874 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", 875 "f_f26m_ck", 7), 876 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", 877 "axi_sel", 8), 878 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", 879 "axi_sel", 9), 880 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", 881 "f_f26m_ck", 10), 882 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", 883 "axi_sel", 11), 884 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", 885 "axi_sel", 12), 886 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", 887 "axi_sel", 13), 888 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", 889 "f_f26m_ck", 14), 890 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", 891 "msdc30_1_sel", 16), 892 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", 893 "msdc30_2_sel", 17), 894 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", 895 "axi_sel", 18), 896 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", 897 "axi_sel", 19), 898 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", 899 "axi_sel", 20), 900 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", 901 "axi_sel", 23), 902 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", 903 "axi_sel", 24), 904 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", 905 "axi_sel", 25), 906 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", 907 "axi_sel", 26), 908 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", 909 "dxcc_sel", 27), 910 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", 911 "dxcc_sel", 28), 912 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", 913 "axi_sel", 30), 914 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 915 "f_f26m_ck", 31), 916 /* INFRA2 */ 917 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", 918 "f_f26m_ck", 0), 919 GATE_INFRA2(CLK_INFRA_USB, "infra_usb", 920 "usb_top_sel", 1), 921 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", 922 "axi_sel", 2), 923 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", 924 "axi_sel", 3), 925 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", 926 "f_f26m_ck", 4), 927 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", 928 "spi_sel", 6), 929 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", 930 "i2c_sel", 7), 931 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", 932 "f_f26m_ck", 8), 933 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", 934 "spi_sel", 9), 935 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", 936 "spi_sel", 10), 937 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", 938 "ssusb_top_xhci_sel", 11), 939 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", 940 "fufs_sel", 12), 941 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", 942 "fufs_sel", 13), 943 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", 944 "axi_sel", 14), 945 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", 946 "axi_sel", 16), 947 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", 948 "i2c_sel", 18), 949 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", 950 "i2c_sel", 19), 951 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", 952 "i2c_sel", 20), 953 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", 954 "i2c_sel", 21), 955 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", 956 "i2c_sel", 22), 957 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", 958 "i2c_sel", 23), 959 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", 960 "i2c_sel", 24), 961 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", 962 "spi_sel", 25), 963 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", 964 "spi_sel", 26), 965 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", 966 "axi_sel", 27), 967 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", 968 "fufs_sel", 28), 969 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", 970 "faes_ufsfde_sel", 29), 971 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", 972 "fufs_sel", 30), 973 /* INFRA3 */ 974 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", 975 "msdc50_0_sel", 0), 976 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", 977 "msdc50_0_sel", 1), 978 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", 979 "msdc50_0_sel", 2), 980 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", 981 "axi_sel", 5), 982 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", 983 "i2c_sel", 6), 984 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", 985 "msdc50_hclk_sel", 7), 986 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", 987 "msdc50_hclk_sel", 8), 988 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", 989 "axi_sel", 16), 990 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", 991 "axi_sel", 17), 992 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", 993 "axi_sel", 18), 994 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", 995 "axi_sel", 19), 996 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", 997 "f_f26m_ck", 20), 998 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", 999 "axi_sel", 21), 1000 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", 1001 "i2c_sel", 22), 1002 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", 1003 "i2c_sel", 23), 1004 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", 1005 "msdc50_0_sel", 24), 1006 }; 1007 1008 static const struct mtk_gate_regs peri_cg_regs = { 1009 .set_ofs = 0x20c, 1010 .clr_ofs = 0x20c, 1011 .sta_ofs = 0x20c, 1012 }; 1013 1014 #define GATE_PERI(_id, _name, _parent, _shift) \ 1015 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ 1016 &mtk_clk_gate_ops_no_setclr_inv) 1017 1018 static const struct mtk_gate peri_clks[] = { 1019 GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), 1020 }; 1021 1022 static const struct mtk_gate_regs apmixed_cg_regs = { 1023 .set_ofs = 0x20, 1024 .clr_ofs = 0x20, 1025 .sta_ofs = 0x20, 1026 }; 1027 1028 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ 1029 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ 1030 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) 1031 1032 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 1033 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) 1034 1035 /* 1036 * CRITICAL CLOCK: 1037 * apmixed_appll26m is the toppest clock gate of all PLLs. 1038 */ 1039 static const struct mtk_gate apmixed_clks[] = { 1040 /* AUDIO0 */ 1041 GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", 1042 "f_f26m_ck", 4), 1043 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", 1044 "f_f26m_ck", 5, CLK_IS_CRITICAL), 1045 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", 1046 "f_f26m_ck", 6), 1047 GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", 1048 "f_f26m_ck", 7), 1049 GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", 1050 "f_f26m_ck", 8), 1051 GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", 1052 "f_f26m_ck", 9), 1053 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", 1054 "f_f26m_ck", 11), 1055 GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", 1056 "f_f26m_ck", 13), 1057 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 1058 "f_f26m_ck", 14), 1059 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", 1060 "f_f26m_ck", 16), 1061 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", 1062 "f_f26m_ck", 17), 1063 }; 1064 1065 #define MT8183_PLL_FMAX (3800UL * MHZ) 1066 #define MT8183_PLL_FMIN (1500UL * MHZ) 1067 1068 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1069 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1070 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1071 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1072 _pcw_chg_reg, _div_table) { \ 1073 .id = _id, \ 1074 .name = _name, \ 1075 .reg = _reg, \ 1076 .pwr_reg = _pwr_reg, \ 1077 .en_mask = _en_mask, \ 1078 .flags = _flags, \ 1079 .rst_bar_mask = _rst_bar_mask, \ 1080 .fmax = MT8183_PLL_FMAX, \ 1081 .fmin = MT8183_PLL_FMIN, \ 1082 .pcwbits = _pcwbits, \ 1083 .pcwibits = _pcwibits, \ 1084 .pd_reg = _pd_reg, \ 1085 .pd_shift = _pd_shift, \ 1086 .tuner_reg = _tuner_reg, \ 1087 .tuner_en_reg = _tuner_en_reg, \ 1088 .tuner_en_bit = _tuner_en_bit, \ 1089 .pcw_reg = _pcw_reg, \ 1090 .pcw_shift = _pcw_shift, \ 1091 .pcw_chg_reg = _pcw_chg_reg, \ 1092 .div_table = _div_table, \ 1093 } 1094 1095 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1096 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1097 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1098 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1099 _pcw_chg_reg) \ 1100 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1101 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1102 _pd_shift, _tuner_reg, _tuner_en_reg, \ 1103 _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1104 _pcw_chg_reg, NULL) 1105 1106 static const struct mtk_pll_div_table armpll_div_table[] = { 1107 { .div = 0, .freq = MT8183_PLL_FMAX }, 1108 { .div = 1, .freq = 1500 * MHZ }, 1109 { .div = 2, .freq = 750 * MHZ }, 1110 { .div = 3, .freq = 375 * MHZ }, 1111 { .div = 4, .freq = 187500000 }, 1112 { } /* sentinel */ 1113 }; 1114 1115 static const struct mtk_pll_div_table mfgpll_div_table[] = { 1116 { .div = 0, .freq = MT8183_PLL_FMAX }, 1117 { .div = 1, .freq = 1600 * MHZ }, 1118 { .div = 2, .freq = 800 * MHZ }, 1119 { .div = 3, .freq = 400 * MHZ }, 1120 { .div = 4, .freq = 200 * MHZ }, 1121 { } /* sentinel */ 1122 }; 1123 1124 static const struct mtk_pll_data plls[] = { 1125 PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0, 1126 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, 1127 0x0204, 0, 0, armpll_div_table), 1128 PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0, 1129 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, 1130 0x0214, 0, 0, armpll_div_table), 1131 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0, 1132 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, 1133 0x0294, 0, 0), 1134 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0, 1135 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, 1136 0x0224, 0, 0), 1137 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0, 1138 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, 1139 0x0234, 0, 0), 1140 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0, 1141 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, 1142 mfgpll_div_table), 1143 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0, 1144 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), 1145 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0, 1146 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), 1147 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0, 1148 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, 1149 0x0274, 0, 0), 1150 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0, 1151 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), 1152 PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0, 1153 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), 1154 }; 1155 1156 static int clk_mt8183_apmixed_probe(struct platform_device *pdev) 1157 { 1158 struct clk_hw_onecell_data *clk_data; 1159 struct device_node *node = pdev->dev.of_node; 1160 1161 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1162 1163 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1164 1165 mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), 1166 clk_data); 1167 1168 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1169 } 1170 1171 static struct clk_hw_onecell_data *top_clk_data; 1172 1173 static void clk_mt8183_top_init_early(struct device_node *node) 1174 { 1175 int i; 1176 1177 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1178 1179 for (i = 0; i < CLK_TOP_NR_CLK; i++) 1180 top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 1181 1182 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1183 top_clk_data); 1184 1185 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); 1186 } 1187 1188 CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", 1189 clk_mt8183_top_init_early); 1190 1191 static int clk_mt8183_top_probe(struct platform_device *pdev) 1192 { 1193 void __iomem *base; 1194 struct device_node *node = pdev->dev.of_node; 1195 1196 base = devm_platform_ioremap_resource(pdev, 0); 1197 if (IS_ERR(base)) 1198 return PTR_ERR(base); 1199 1200 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 1201 top_clk_data); 1202 1203 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1204 top_clk_data); 1205 1206 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); 1207 1208 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), 1209 node, &mt8183_clk_lock, top_clk_data); 1210 1211 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), 1212 base, &mt8183_clk_lock, top_clk_data); 1213 1214 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), 1215 base, &mt8183_clk_lock, top_clk_data); 1216 1217 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 1218 top_clk_data); 1219 1220 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 1221 top_clk_data); 1222 } 1223 1224 static int clk_mt8183_infra_probe(struct platform_device *pdev) 1225 { 1226 struct clk_hw_onecell_data *clk_data; 1227 struct device_node *node = pdev->dev.of_node; 1228 int r; 1229 1230 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1231 1232 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1233 clk_data); 1234 1235 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1236 if (r) { 1237 dev_err(&pdev->dev, 1238 "%s(): could not register clock provider: %d\n", 1239 __func__, r); 1240 return r; 1241 } 1242 1243 mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET); 1244 1245 return r; 1246 } 1247 1248 static int clk_mt8183_peri_probe(struct platform_device *pdev) 1249 { 1250 struct clk_hw_onecell_data *clk_data; 1251 struct device_node *node = pdev->dev.of_node; 1252 1253 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 1254 1255 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), 1256 clk_data); 1257 1258 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1259 } 1260 1261 static int clk_mt8183_mcu_probe(struct platform_device *pdev) 1262 { 1263 struct clk_hw_onecell_data *clk_data; 1264 struct device_node *node = pdev->dev.of_node; 1265 void __iomem *base; 1266 1267 base = devm_platform_ioremap_resource(pdev, 0); 1268 if (IS_ERR(base)) 1269 return PTR_ERR(base); 1270 1271 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); 1272 1273 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, 1274 &mt8183_clk_lock, clk_data); 1275 1276 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1277 } 1278 1279 static const struct of_device_id of_match_clk_mt8183[] = { 1280 { 1281 .compatible = "mediatek,mt8183-apmixedsys", 1282 .data = clk_mt8183_apmixed_probe, 1283 }, { 1284 .compatible = "mediatek,mt8183-topckgen", 1285 .data = clk_mt8183_top_probe, 1286 }, { 1287 .compatible = "mediatek,mt8183-infracfg", 1288 .data = clk_mt8183_infra_probe, 1289 }, { 1290 .compatible = "mediatek,mt8183-pericfg", 1291 .data = clk_mt8183_peri_probe, 1292 }, { 1293 .compatible = "mediatek,mt8183-mcucfg", 1294 .data = clk_mt8183_mcu_probe, 1295 }, { 1296 /* sentinel */ 1297 } 1298 }; 1299 1300 static int clk_mt8183_probe(struct platform_device *pdev) 1301 { 1302 int (*clk_probe)(struct platform_device *pdev); 1303 int r; 1304 1305 clk_probe = of_device_get_match_data(&pdev->dev); 1306 if (!clk_probe) 1307 return -EINVAL; 1308 1309 r = clk_probe(pdev); 1310 if (r) 1311 dev_err(&pdev->dev, 1312 "could not register clock provider: %s: %d\n", 1313 pdev->name, r); 1314 1315 return r; 1316 } 1317 1318 static struct platform_driver clk_mt8183_drv = { 1319 .probe = clk_mt8183_probe, 1320 .driver = { 1321 .name = "clk-mt8183", 1322 .of_match_table = of_match_clk_mt8183, 1323 }, 1324 }; 1325 1326 static int __init clk_mt8183_init(void) 1327 { 1328 return platform_driver_register(&clk_mt8183_drv); 1329 } 1330 1331 arch_initcall(clk_mt8183_init); 1332