1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 6 #include <linux/delay.h> 7 #include <linux/mfd/syscon.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 14 #include "clk-gate.h" 15 #include "clk-mtk.h" 16 #include "clk-mux.h" 17 18 #include <dt-bindings/clock/mt8183-clk.h> 19 20 static DEFINE_SPINLOCK(mt8183_clk_lock); 21 22 static const struct mtk_fixed_clk top_fixed_clks[] = { 23 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 24 FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 25 FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 26 }; 27 28 /* 29 * To retain compatibility with older devicetrees, we keep CLK_TOP_CLK13M 30 * valid, but renamed from "clk13m" (defined as fixed clock in the new 31 * devicetrees) to "clk26m_d2", satisfying the older clock assignments. 32 * This means that on new devicetrees "clk26m_d2" is unused. 33 */ 34 static const struct mtk_fixed_factor top_divs[] = { 35 FACTOR(CLK_TOP_CLK13M, "clk26m_d2", "clk26m", 1, 2), 36 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2), 37 FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0), 38 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0), 39 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0), 40 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0), 41 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0), 42 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0), 43 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0), 44 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0), 45 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0), 46 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0), 47 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0), 48 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0), 49 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 4, 0), 50 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0), 51 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 2, 0), 52 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 4, 0), 53 FACTOR_FLAGS(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1, 0), 54 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2, 0), 55 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0), 56 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0), 57 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8, 0), 58 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0), 59 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0), 60 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0), 61 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0), 62 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0), 63 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0), 64 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0), 65 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0), 66 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0), 67 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 1, 0), 68 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 2, 0), 69 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 4, 0), 70 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 8, 0), 71 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 16, 0), 72 FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 32, 0), 73 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1), 74 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 75 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 76 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 77 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1), 78 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 79 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 80 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 81 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1), 82 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 83 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 84 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 85 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 86 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1), 87 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 88 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 89 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4), 90 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 91 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 92 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4), 93 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 94 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 95 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1), 96 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1), 97 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 98 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 99 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 100 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16), 101 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1), 102 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2), 103 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4), 104 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8), 105 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16), 106 FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0), 107 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16, 0), 108 }; 109 110 static const char * const axi_parents[] = { 111 "clk26m", 112 "syspll_d2_d4", 113 "syspll_d7", 114 "osc_d4" 115 }; 116 117 static const char * const mm_parents[] = { 118 "clk26m", 119 "mmpll_d7", 120 "syspll_d3", 121 "univpll_d2_d2", 122 "syspll_d2_d2", 123 "syspll_d3_d2" 124 }; 125 126 static const char * const img_parents[] = { 127 "clk26m", 128 "mmpll_d6", 129 "univpll_d3", 130 "syspll_d3", 131 "univpll_d2_d2", 132 "syspll_d2_d2", 133 "univpll_d3_d2", 134 "syspll_d3_d2" 135 }; 136 137 static const char * const cam_parents[] = { 138 "clk26m", 139 "syspll_d2", 140 "mmpll_d6", 141 "syspll_d3", 142 "mmpll_d7", 143 "univpll_d3", 144 "univpll_d2_d2", 145 "syspll_d2_d2", 146 "syspll_d3_d2", 147 "univpll_d3_d2" 148 }; 149 150 static const char * const dsp_parents[] = { 151 "clk26m", 152 "mmpll_d6", 153 "mmpll_d7", 154 "univpll_d3", 155 "syspll_d3", 156 "univpll_d2_d2", 157 "syspll_d2_d2", 158 "univpll_d3_d2", 159 "syspll_d3_d2" 160 }; 161 162 static const char * const dsp1_parents[] = { 163 "clk26m", 164 "mmpll_d6", 165 "mmpll_d7", 166 "univpll_d3", 167 "syspll_d3", 168 "univpll_d2_d2", 169 "syspll_d2_d2", 170 "univpll_d3_d2", 171 "syspll_d3_d2" 172 }; 173 174 static const char * const dsp2_parents[] = { 175 "clk26m", 176 "mmpll_d6", 177 "mmpll_d7", 178 "univpll_d3", 179 "syspll_d3", 180 "univpll_d2_d2", 181 "syspll_d2_d2", 182 "univpll_d3_d2", 183 "syspll_d3_d2" 184 }; 185 186 static const char * const ipu_if_parents[] = { 187 "clk26m", 188 "mmpll_d6", 189 "mmpll_d7", 190 "univpll_d3", 191 "syspll_d3", 192 "univpll_d2_d2", 193 "syspll_d2_d2", 194 "univpll_d3_d2", 195 "syspll_d3_d2" 196 }; 197 198 static const char * const mfg_parents[] = { 199 "clk26m", 200 "mfgpll_ck", 201 "univpll_d3", 202 "syspll_d3" 203 }; 204 205 static const char * const f52m_mfg_parents[] = { 206 "clk26m", 207 "univpll_d3_d2", 208 "univpll_d3_d4", 209 "univpll_d3_d8" 210 }; 211 212 static const char * const camtg_parents[] = { 213 "clk26m", 214 "univ_192m_d8", 215 "univpll_d3_d8", 216 "univ_192m_d4", 217 "univpll_d3_d16", 218 "csw_f26m_ck_d2", 219 "univ_192m_d16", 220 "univ_192m_d32" 221 }; 222 223 static const char * const camtg2_parents[] = { 224 "clk26m", 225 "univ_192m_d8", 226 "univpll_d3_d8", 227 "univ_192m_d4", 228 "univpll_d3_d16", 229 "csw_f26m_ck_d2", 230 "univ_192m_d16", 231 "univ_192m_d32" 232 }; 233 234 static const char * const camtg3_parents[] = { 235 "clk26m", 236 "univ_192m_d8", 237 "univpll_d3_d8", 238 "univ_192m_d4", 239 "univpll_d3_d16", 240 "csw_f26m_ck_d2", 241 "univ_192m_d16", 242 "univ_192m_d32" 243 }; 244 245 static const char * const camtg4_parents[] = { 246 "clk26m", 247 "univ_192m_d8", 248 "univpll_d3_d8", 249 "univ_192m_d4", 250 "univpll_d3_d16", 251 "csw_f26m_ck_d2", 252 "univ_192m_d16", 253 "univ_192m_d32" 254 }; 255 256 static const char * const uart_parents[] = { 257 "clk26m", 258 "univpll_d3_d8" 259 }; 260 261 static const char * const spi_parents[] = { 262 "clk26m", 263 "syspll_d5_d2", 264 "syspll_d3_d4", 265 "msdcpll_d4" 266 }; 267 268 static const char * const msdc50_hclk_parents[] = { 269 "clk26m", 270 "syspll_d2_d2", 271 "syspll_d3_d2" 272 }; 273 274 static const char * const msdc50_0_parents[] = { 275 "clk26m", 276 "msdcpll_ck", 277 "msdcpll_d2", 278 "univpll_d2_d4", 279 "syspll_d3_d2", 280 "univpll_d2_d2" 281 }; 282 283 static const char * const msdc30_1_parents[] = { 284 "clk26m", 285 "univpll_d3_d2", 286 "syspll_d3_d2", 287 "syspll_d7", 288 "msdcpll_d2" 289 }; 290 291 static const char * const msdc30_2_parents[] = { 292 "clk26m", 293 "univpll_d3_d2", 294 "syspll_d3_d2", 295 "syspll_d7", 296 "msdcpll_d2" 297 }; 298 299 static const char * const audio_parents[] = { 300 "clk26m", 301 "syspll_d5_d4", 302 "syspll_d7_d4", 303 "syspll_d2_d16" 304 }; 305 306 static const char * const aud_intbus_parents[] = { 307 "clk26m", 308 "syspll_d2_d4", 309 "syspll_d7_d2" 310 }; 311 312 static const char * const pmicspi_parents[] = { 313 "clk26m", 314 "syspll_d2_d8", 315 "osc_d8" 316 }; 317 318 static const char * const fpwrap_ulposc_parents[] = { 319 "clk26m", 320 "osc_d16", 321 "osc_d4", 322 "osc_d8" 323 }; 324 325 static const char * const atb_parents[] = { 326 "clk26m", 327 "syspll_d2_d2", 328 "syspll_d5" 329 }; 330 331 static const char * const dpi0_parents[] = { 332 "clk26m", 333 "tvdpll_d2", 334 "tvdpll_d4", 335 "tvdpll_d8", 336 "tvdpll_d16", 337 "univpll_d5_d2", 338 "univpll_d3_d4", 339 "syspll_d3_d4", 340 "univpll_d3_d8" 341 }; 342 343 static const char * const scam_parents[] = { 344 "clk26m", 345 "syspll_d5_d2" 346 }; 347 348 static const char * const disppwm_parents[] = { 349 "clk26m", 350 "univpll_d3_d4", 351 "osc_d2", 352 "osc_d4", 353 "osc_d16" 354 }; 355 356 static const char * const usb_top_parents[] = { 357 "clk26m", 358 "univpll_d5_d4", 359 "univpll_d3_d4", 360 "univpll_d5_d2" 361 }; 362 363 364 static const char * const ssusb_top_xhci_parents[] = { 365 "clk26m", 366 "univpll_d5_d4", 367 "univpll_d3_d4", 368 "univpll_d5_d2" 369 }; 370 371 static const char * const spm_parents[] = { 372 "clk26m", 373 "syspll_d2_d8" 374 }; 375 376 static const char * const i2c_parents[] = { 377 "clk26m", 378 "syspll_d2_d8", 379 "univpll_d5_d2" 380 }; 381 382 static const char * const scp_parents[] = { 383 "clk26m", 384 "univpll_d2_d8", 385 "syspll_d5", 386 "syspll_d2_d2", 387 "univpll_d2_d2", 388 "syspll_d3", 389 "univpll_d3" 390 }; 391 392 static const char * const seninf_parents[] = { 393 "clk26m", 394 "univpll_d2_d2", 395 "univpll_d3_d2", 396 "univpll_d2_d4" 397 }; 398 399 static const char * const dxcc_parents[] = { 400 "clk26m", 401 "syspll_d2_d2", 402 "syspll_d2_d4", 403 "syspll_d2_d8" 404 }; 405 406 static const char * const aud_engen1_parents[] = { 407 "clk26m", 408 "apll1_d2", 409 "apll1_d4", 410 "apll1_d8" 411 }; 412 413 static const char * const aud_engen2_parents[] = { 414 "clk26m", 415 "apll2_d2", 416 "apll2_d4", 417 "apll2_d8" 418 }; 419 420 static const char * const faes_ufsfde_parents[] = { 421 "clk26m", 422 "syspll_d2", 423 "syspll_d2_d2", 424 "syspll_d3", 425 "syspll_d2_d4", 426 "univpll_d3" 427 }; 428 429 static const char * const fufs_parents[] = { 430 "clk26m", 431 "syspll_d2_d4", 432 "syspll_d2_d8", 433 "syspll_d2_d16" 434 }; 435 436 static const char * const aud_1_parents[] = { 437 "clk26m", 438 "apll1_ck" 439 }; 440 441 static const char * const aud_2_parents[] = { 442 "clk26m", 443 "apll2_ck" 444 }; 445 446 /* 447 * CRITICAL CLOCK: 448 * axi_sel is the main bus clock of whole SOC. 449 * spm_sel is the clock of the always-on co-processor. 450 */ 451 static const struct mtk_mux top_muxes[] = { 452 /* CLK_CFG_0 */ 453 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 454 axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), 455 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 456 mm_parents, 0x40, 0x44, 0x48, 8, 3, 15, 0x004, 1), 457 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 458 img_parents, 0x40, 0x44, 0x48, 16, 3, 23, 0x004, 2), 459 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 460 cam_parents, 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 3), 461 /* CLK_CFG_1 */ 462 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 463 dsp_parents, 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 4), 464 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 465 dsp1_parents, 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 5), 466 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 467 dsp2_parents, 0x50, 0x54, 0x58, 16, 4, 23, 0x004, 6), 468 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 469 ipu_if_parents, 0x50, 0x54, 0x58, 24, 4, 31, 0x004, 7), 470 /* CLK_CFG_2 */ 471 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 472 mfg_parents, 0x60, 0x64, 0x68, 0, 2, 7, 0x004, 8), 473 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 474 f52m_mfg_parents, 0x60, 0x64, 0x68, 8, 2, 15, 0x004, 9), 475 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 476 camtg_parents, 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 10), 477 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 478 camtg2_parents, 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 11), 479 /* CLK_CFG_3 */ 480 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 481 camtg3_parents, 0x70, 0x74, 0x78, 0, 3, 7, 0x004, 12), 482 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 483 camtg4_parents, 0x70, 0x74, 0x78, 8, 3, 15, 0x004, 13), 484 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 485 uart_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x004, 14), 486 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 487 spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15), 488 /* CLK_CFG_4 */ 489 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 490 msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16), 491 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 492 msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17), 493 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 494 msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18), 495 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 496 msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19), 497 /* CLK_CFG_5 */ 498 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 499 audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20), 500 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 501 aud_intbus_parents, 0x90, 0x94, 0x98, 8, 2, 15, 0x004, 21), 502 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 503 pmicspi_parents, 0x90, 0x94, 0x98, 16, 2, 23, 0x004, 22), 504 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 505 fpwrap_ulposc_parents, 0x90, 0x94, 0x98, 24, 2, 31, 0x004, 23), 506 /* CLK_CFG_6 */ 507 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 508 atb_parents, 0xa0, 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 509 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 510 dpi0_parents, 0xa0, 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 511 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 512 scam_parents, 0xa0, 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 513 /* CLK_CFG_7 */ 514 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 515 disppwm_parents, 0xb0, 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 516 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 517 usb_top_parents, 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 518 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 519 ssusb_top_xhci_parents, 0xb0, 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 520 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 521 spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), 522 /* CLK_CFG_8 */ 523 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 524 i2c_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 525 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 526 scp_parents, 0xc0, 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 527 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 528 seninf_parents, 0xc0, 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 529 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 530 dxcc_parents, 0xc0, 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 531 /* CLK_CFG_9 */ 532 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 533 aud_engen1_parents, 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 534 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 535 aud_engen2_parents, 0xd0, 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 536 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 537 faes_ufsfde_parents, 0xd0, 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 538 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 539 fufs_parents, 0xd0, 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 540 /* CLK_CFG_10 */ 541 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 542 aud_1_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 543 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 544 aud_2_parents, 0xe0, 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 545 }; 546 547 static const char * const apll_i2s0_parents[] = { 548 "aud_1_sel", 549 "aud_2_sel" 550 }; 551 552 static const char * const apll_i2s1_parents[] = { 553 "aud_1_sel", 554 "aud_2_sel" 555 }; 556 557 static const char * const apll_i2s2_parents[] = { 558 "aud_1_sel", 559 "aud_2_sel" 560 }; 561 562 static const char * const apll_i2s3_parents[] = { 563 "aud_1_sel", 564 "aud_2_sel" 565 }; 566 567 static const char * const apll_i2s4_parents[] = { 568 "aud_1_sel", 569 "aud_2_sel" 570 }; 571 572 static const char * const apll_i2s5_parents[] = { 573 "aud_1_sel", 574 "aud_2_sel" 575 }; 576 577 static const char * const mcu_mp0_parents[] = { 578 "clk26m", 579 "armpll_ll", 580 "armpll_div_pll1", 581 "armpll_div_pll2" 582 }; 583 584 static const char * const mcu_mp2_parents[] = { 585 "clk26m", 586 "armpll_l", 587 "armpll_div_pll1", 588 "armpll_div_pll2" 589 }; 590 591 static const char * const mcu_bus_parents[] = { 592 "clk26m", 593 "ccipll", 594 "armpll_div_pll1", 595 "armpll_div_pll2" 596 }; 597 598 static struct mtk_composite mcu_muxes[] = { 599 /* mp0_pll_divider_cfg */ 600 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 601 /* mp2_pll_divider_cfg */ 602 MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 603 /* bus_pll_divider_cfg */ 604 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 605 }; 606 607 static struct mtk_composite top_aud_comp[] = { 608 MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 0x320, 8, 1), 609 MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 0x320, 9, 1), 610 MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 0x320, 10, 1), 611 MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 0x320, 11, 1), 612 MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 0x320, 12, 1), 613 MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 0x328, 20, 1), 614 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 0x320, 2, 0x324, 8, 0), 615 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 0x320, 3, 0x324, 8, 8), 616 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 0x320, 4, 0x324, 8, 16), 617 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 0x320, 5, 0x324, 8, 24), 618 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 0x320, 6, 0x328, 8, 0), 619 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 7, 0x328, 8, 8), 620 }; 621 622 static const struct mtk_gate_regs top_cg_regs = { 623 .set_ofs = 0x104, 624 .clr_ofs = 0x104, 625 .sta_ofs = 0x104, 626 }; 627 628 #define GATE_TOP(_id, _name, _parent, _shift) \ 629 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 630 &mtk_clk_gate_ops_no_setclr_inv) 631 632 static const struct mtk_gate top_clks[] = { 633 /* TOP */ 634 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 635 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 636 }; 637 638 static const struct mtk_gate_regs infra0_cg_regs = { 639 .set_ofs = 0x80, 640 .clr_ofs = 0x84, 641 .sta_ofs = 0x90, 642 }; 643 644 static const struct mtk_gate_regs infra1_cg_regs = { 645 .set_ofs = 0x88, 646 .clr_ofs = 0x8c, 647 .sta_ofs = 0x94, 648 }; 649 650 static const struct mtk_gate_regs infra2_cg_regs = { 651 .set_ofs = 0xa4, 652 .clr_ofs = 0xa8, 653 .sta_ofs = 0xac, 654 }; 655 656 static const struct mtk_gate_regs infra3_cg_regs = { 657 .set_ofs = 0xc0, 658 .clr_ofs = 0xc4, 659 .sta_ofs = 0xc8, 660 }; 661 662 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 663 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 664 &mtk_clk_gate_ops_setclr) 665 666 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 667 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 668 &mtk_clk_gate_ops_setclr) 669 670 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 671 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 672 &mtk_clk_gate_ops_setclr) 673 674 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 675 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 676 &mtk_clk_gate_ops_setclr) 677 678 static const struct mtk_gate infra_clks[] = { 679 /* INFRA0 */ 680 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0), 681 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "axi_sel", 1), 682 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "axi_sel", 2), 683 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "axi_sel", 3), 684 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", "scp_sel", 4), 685 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "f_f26m_ck", 5), 686 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 687 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", "axi_sel", 8), 688 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9), 689 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 690 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), 691 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", "i2c_sel", 12), 692 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), 693 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), 694 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15), 695 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "i2c_sel", 16), 696 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "i2c_sel", 17), 697 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "i2c_sel", 18), 698 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "i2c_sel", 19), 699 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "i2c_sel", 21), 700 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 701 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 702 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 703 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 704 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), 705 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", "axi_sel", 28), 706 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 707 /* INFRA1 */ 708 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), 709 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_hclk_sel", 2), 710 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "axi_sel", 4), 711 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "axi_sel", 5), 712 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", "msdc50_0_sel", 6), 713 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", "f_f26m_ck", 7), 714 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 715 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 716 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "f_f26m_ck", 10), 717 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 718 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), 719 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), 720 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "f_f26m_ck", 14), 721 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", "msdc30_1_sel", 16), 722 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", "msdc30_2_sel", 17), 723 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", "axi_sel", 18), 724 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", "axi_sel", 19), 725 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20), 726 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 727 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), 728 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 729 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 730 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), 731 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), 732 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", "axi_sel", 30), 733 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "f_f26m_ck", 31), 734 /* INFRA2 */ 735 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "f_f26m_ck", 0), 736 GATE_INFRA2(CLK_INFRA_USB, "infra_usb", "usb_top_sel", 1), 737 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", "axi_sel", 2), 738 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", "axi_sel", 3), 739 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", "f_f26m_ck", 4), 740 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), 741 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), 742 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", "f_f26m_ck", 8), 743 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), 744 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), 745 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", "ssusb_top_xhci_sel", 11), 746 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "fufs_sel", 12), 747 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", "fufs_sel", 13), 748 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14), 749 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), 750 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), 751 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), 752 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), 753 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), 754 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), 755 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), 756 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), 757 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), 758 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), 759 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", "axi_sel", 27), 760 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "fufs_sel", 28), 761 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "faes_ufsfde_sel", 29), 762 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "fufs_sel", 30), 763 /* INFRA3 */ 764 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), 765 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), 766 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), 767 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), 768 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), 769 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_hclk_sel", 7), 770 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_hclk_sel", 8), 771 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), 772 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), 773 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), 774 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), 775 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "f_f26m_ck", 20), 776 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", "axi_sel", 21), 777 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), 778 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), 779 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), 780 }; 781 782 static const struct mtk_gate_regs peri_cg_regs = { 783 .set_ofs = 0x20c, 784 .clr_ofs = 0x20c, 785 .sta_ofs = 0x20c, 786 }; 787 788 #define GATE_PERI(_id, _name, _parent, _shift) \ 789 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ 790 &mtk_clk_gate_ops_no_setclr_inv) 791 792 static const struct mtk_gate peri_clks[] = { 793 GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), 794 }; 795 796 static u16 infra_rst_ofs[] = { 797 INFRA_RST0_SET_OFFSET, 798 INFRA_RST1_SET_OFFSET, 799 INFRA_RST2_SET_OFFSET, 800 INFRA_RST3_SET_OFFSET, 801 }; 802 803 static const struct mtk_clk_rst_desc clk_rst_desc = { 804 .version = MTK_RST_SET_CLR, 805 .rst_bank_ofs = infra_rst_ofs, 806 .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), 807 }; 808 809 /* Register mux notifier for MFG mux */ 810 static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) 811 { 812 struct mtk_mux_nb *mfg_mux_nb; 813 int i; 814 815 mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); 816 if (!mfg_mux_nb) 817 return -ENOMEM; 818 819 for (i = 0; i < ARRAY_SIZE(top_muxes); i++) 820 if (top_muxes[i].id == CLK_TOP_MUX_MFG) 821 break; 822 if (i == ARRAY_SIZE(top_muxes)) 823 return -EINVAL; 824 825 mfg_mux_nb->ops = top_muxes[i].ops; 826 mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */ 827 828 return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); 829 } 830 831 static const struct mtk_clk_desc infra_desc = { 832 .clks = infra_clks, 833 .num_clks = ARRAY_SIZE(infra_clks), 834 .rst_desc = &clk_rst_desc, 835 }; 836 837 static const struct mtk_clk_desc mcu_desc = { 838 .composite_clks = mcu_muxes, 839 .num_composite_clks = ARRAY_SIZE(mcu_muxes), 840 .clk_lock = &mt8183_clk_lock, 841 }; 842 843 static const struct mtk_clk_desc peri_desc = { 844 .clks = peri_clks, 845 .num_clks = ARRAY_SIZE(peri_clks), 846 }; 847 848 static const struct mtk_clk_desc topck_desc = { 849 .fixed_clks = top_fixed_clks, 850 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 851 .factor_clks = top_divs, 852 .num_factor_clks = ARRAY_SIZE(top_divs), 853 .mux_clks = top_muxes, 854 .num_mux_clks = ARRAY_SIZE(top_muxes), 855 .composite_clks = top_aud_comp, 856 .num_composite_clks = ARRAY_SIZE(top_aud_comp), 857 .clks = top_clks, 858 .num_clks = ARRAY_SIZE(top_clks), 859 .clk_lock = &mt8183_clk_lock, 860 .clk_notifier_func = clk_mt8183_reg_mfg_mux_notifier, 861 .mfg_clk_idx = CLK_TOP_MUX_MFG, 862 }; 863 864 static const struct of_device_id of_match_clk_mt8183[] = { 865 { .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc }, 866 { .compatible = "mediatek,mt8183-mcucfg", .data = &mcu_desc }, 867 { .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, }, 868 { .compatible = "mediatek,mt8183-topckgen", .data = &topck_desc }, 869 { /* sentinel */ } 870 }; 871 MODULE_DEVICE_TABLE(of, of_match_clk_mt8183); 872 873 static struct platform_driver clk_mt8183_drv = { 874 .probe = mtk_clk_simple_probe, 875 .remove = mtk_clk_simple_remove, 876 .driver = { 877 .name = "clk-mt8183", 878 .of_match_table = of_match_clk_mt8183, 879 }, 880 }; 881 module_platform_driver(clk_mt8183_drv) 882 MODULE_LICENSE("GPL"); 883