1acddfc2cSWeiyi Lu // SPDX-License-Identifier: GPL-2.0 2acddfc2cSWeiyi Lu // 3acddfc2cSWeiyi Lu // Copyright (c) 2018 MediaTek Inc. 4acddfc2cSWeiyi Lu // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5acddfc2cSWeiyi Lu 6acddfc2cSWeiyi Lu #include <linux/delay.h> 7acddfc2cSWeiyi Lu #include <linux/mfd/syscon.h> 8acddfc2cSWeiyi Lu #include <linux/of.h> 9acddfc2cSWeiyi Lu #include <linux/of_address.h> 10acddfc2cSWeiyi Lu #include <linux/of_device.h> 11acddfc2cSWeiyi Lu #include <linux/platform_device.h> 12acddfc2cSWeiyi Lu #include <linux/slab.h> 13acddfc2cSWeiyi Lu 1439691fb6SChen-Yu Tsai #include "clk-gate.h" 15acddfc2cSWeiyi Lu #include "clk-mtk.h" 16acddfc2cSWeiyi Lu #include "clk-mux.h" 17acddfc2cSWeiyi Lu 18acddfc2cSWeiyi Lu #include <dt-bindings/clock/mt8183-clk.h> 19acddfc2cSWeiyi Lu 20acddfc2cSWeiyi Lu static DEFINE_SPINLOCK(mt8183_clk_lock); 21acddfc2cSWeiyi Lu 22acddfc2cSWeiyi Lu static const struct mtk_fixed_clk top_fixed_clks[] = { 23acddfc2cSWeiyi Lu FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 24acddfc2cSWeiyi Lu FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 25acddfc2cSWeiyi Lu FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 26acddfc2cSWeiyi Lu }; 27acddfc2cSWeiyi Lu 283f37ba7cSAngeloGioacchino Del Regno /* 293f37ba7cSAngeloGioacchino Del Regno * To retain compatibility with older devicetrees, we keep CLK_TOP_CLK13M 303f37ba7cSAngeloGioacchino Del Regno * valid, but renamed from "clk13m" (defined as fixed clock in the new 313f37ba7cSAngeloGioacchino Del Regno * devicetrees) to "clk26m_d2", satisfying the older clock assignments. 323f37ba7cSAngeloGioacchino Del Regno * This means that on new devicetrees "clk26m_d2" is unused. 333f37ba7cSAngeloGioacchino Del Regno */ 34acddfc2cSWeiyi Lu static const struct mtk_fixed_factor top_divs[] = { 353f37ba7cSAngeloGioacchino Del Regno FACTOR(CLK_TOP_CLK13M, "clk26m_d2", "clk26m", 1, 2), 3623037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2), 37c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0), 38c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0), 39c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0), 40c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0), 41c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0), 42c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0), 43c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0), 44c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0), 45c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0), 46c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0), 47c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0), 48c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0), 49c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 4, 0), 50c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0), 51c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 2, 0), 52c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 4, 0), 53c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1, 0), 54c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2, 0), 55c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0), 56c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0), 57c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8, 0), 58c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0), 59c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0), 60c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0), 61c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0), 62c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0), 63c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0), 64c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0), 65c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0), 66c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0), 67c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 1, 0), 68c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 2, 0), 69c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 4, 0), 70c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 8, 0), 71c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 16, 0), 72c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 32, 0), 7323037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1), 7423037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 7523037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 7623037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 7723037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1), 7823037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 7923037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 8023037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 8123037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1), 8223037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 8323037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 8423037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 8523037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 8623037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1), 8723037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 8823037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 8923037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4), 9023037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 9123037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 9223037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4), 9323037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 9423037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 9523037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1), 9623037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1), 9723037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 9823037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 9923037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 10023037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16), 10123037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1), 10223037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2), 10323037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4), 10423037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8), 10523037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16), 106c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0), 107c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16, 0), 108acddfc2cSWeiyi Lu }; 109acddfc2cSWeiyi Lu 110acddfc2cSWeiyi Lu static const char * const axi_parents[] = { 111acddfc2cSWeiyi Lu "clk26m", 112acddfc2cSWeiyi Lu "syspll_d2_d4", 113acddfc2cSWeiyi Lu "syspll_d7", 114acddfc2cSWeiyi Lu "osc_d4" 115acddfc2cSWeiyi Lu }; 116acddfc2cSWeiyi Lu 117acddfc2cSWeiyi Lu static const char * const mm_parents[] = { 118acddfc2cSWeiyi Lu "clk26m", 119acddfc2cSWeiyi Lu "mmpll_d7", 120acddfc2cSWeiyi Lu "syspll_d3", 121acddfc2cSWeiyi Lu "univpll_d2_d2", 122acddfc2cSWeiyi Lu "syspll_d2_d2", 123acddfc2cSWeiyi Lu "syspll_d3_d2" 124acddfc2cSWeiyi Lu }; 125acddfc2cSWeiyi Lu 126acddfc2cSWeiyi Lu static const char * const img_parents[] = { 127acddfc2cSWeiyi Lu "clk26m", 128acddfc2cSWeiyi Lu "mmpll_d6", 129acddfc2cSWeiyi Lu "univpll_d3", 130acddfc2cSWeiyi Lu "syspll_d3", 131acddfc2cSWeiyi Lu "univpll_d2_d2", 132acddfc2cSWeiyi Lu "syspll_d2_d2", 133acddfc2cSWeiyi Lu "univpll_d3_d2", 134acddfc2cSWeiyi Lu "syspll_d3_d2" 135acddfc2cSWeiyi Lu }; 136acddfc2cSWeiyi Lu 137acddfc2cSWeiyi Lu static const char * const cam_parents[] = { 138acddfc2cSWeiyi Lu "clk26m", 139acddfc2cSWeiyi Lu "syspll_d2", 140acddfc2cSWeiyi Lu "mmpll_d6", 141acddfc2cSWeiyi Lu "syspll_d3", 142acddfc2cSWeiyi Lu "mmpll_d7", 143acddfc2cSWeiyi Lu "univpll_d3", 144acddfc2cSWeiyi Lu "univpll_d2_d2", 145acddfc2cSWeiyi Lu "syspll_d2_d2", 146acddfc2cSWeiyi Lu "syspll_d3_d2", 147acddfc2cSWeiyi Lu "univpll_d3_d2" 148acddfc2cSWeiyi Lu }; 149acddfc2cSWeiyi Lu 150acddfc2cSWeiyi Lu static const char * const dsp_parents[] = { 151acddfc2cSWeiyi Lu "clk26m", 152acddfc2cSWeiyi Lu "mmpll_d6", 153acddfc2cSWeiyi Lu "mmpll_d7", 154acddfc2cSWeiyi Lu "univpll_d3", 155acddfc2cSWeiyi Lu "syspll_d3", 156acddfc2cSWeiyi Lu "univpll_d2_d2", 157acddfc2cSWeiyi Lu "syspll_d2_d2", 158acddfc2cSWeiyi Lu "univpll_d3_d2", 159acddfc2cSWeiyi Lu "syspll_d3_d2" 160acddfc2cSWeiyi Lu }; 161acddfc2cSWeiyi Lu 162acddfc2cSWeiyi Lu static const char * const dsp1_parents[] = { 163acddfc2cSWeiyi Lu "clk26m", 164acddfc2cSWeiyi Lu "mmpll_d6", 165acddfc2cSWeiyi Lu "mmpll_d7", 166acddfc2cSWeiyi Lu "univpll_d3", 167acddfc2cSWeiyi Lu "syspll_d3", 168acddfc2cSWeiyi Lu "univpll_d2_d2", 169acddfc2cSWeiyi Lu "syspll_d2_d2", 170acddfc2cSWeiyi Lu "univpll_d3_d2", 171acddfc2cSWeiyi Lu "syspll_d3_d2" 172acddfc2cSWeiyi Lu }; 173acddfc2cSWeiyi Lu 174acddfc2cSWeiyi Lu static const char * const dsp2_parents[] = { 175acddfc2cSWeiyi Lu "clk26m", 176acddfc2cSWeiyi Lu "mmpll_d6", 177acddfc2cSWeiyi Lu "mmpll_d7", 178acddfc2cSWeiyi Lu "univpll_d3", 179acddfc2cSWeiyi Lu "syspll_d3", 180acddfc2cSWeiyi Lu "univpll_d2_d2", 181acddfc2cSWeiyi Lu "syspll_d2_d2", 182acddfc2cSWeiyi Lu "univpll_d3_d2", 183acddfc2cSWeiyi Lu "syspll_d3_d2" 184acddfc2cSWeiyi Lu }; 185acddfc2cSWeiyi Lu 186acddfc2cSWeiyi Lu static const char * const ipu_if_parents[] = { 187acddfc2cSWeiyi Lu "clk26m", 188acddfc2cSWeiyi Lu "mmpll_d6", 189acddfc2cSWeiyi Lu "mmpll_d7", 190acddfc2cSWeiyi Lu "univpll_d3", 191acddfc2cSWeiyi Lu "syspll_d3", 192acddfc2cSWeiyi Lu "univpll_d2_d2", 193acddfc2cSWeiyi Lu "syspll_d2_d2", 194acddfc2cSWeiyi Lu "univpll_d3_d2", 195acddfc2cSWeiyi Lu "syspll_d3_d2" 196acddfc2cSWeiyi Lu }; 197acddfc2cSWeiyi Lu 198acddfc2cSWeiyi Lu static const char * const mfg_parents[] = { 199acddfc2cSWeiyi Lu "clk26m", 200acddfc2cSWeiyi Lu "mfgpll_ck", 201acddfc2cSWeiyi Lu "univpll_d3", 202acddfc2cSWeiyi Lu "syspll_d3" 203acddfc2cSWeiyi Lu }; 204acddfc2cSWeiyi Lu 205acddfc2cSWeiyi Lu static const char * const f52m_mfg_parents[] = { 206acddfc2cSWeiyi Lu "clk26m", 207acddfc2cSWeiyi Lu "univpll_d3_d2", 208acddfc2cSWeiyi Lu "univpll_d3_d4", 209acddfc2cSWeiyi Lu "univpll_d3_d8" 210acddfc2cSWeiyi Lu }; 211acddfc2cSWeiyi Lu 212acddfc2cSWeiyi Lu static const char * const camtg_parents[] = { 213acddfc2cSWeiyi Lu "clk26m", 214acddfc2cSWeiyi Lu "univ_192m_d8", 215acddfc2cSWeiyi Lu "univpll_d3_d8", 216acddfc2cSWeiyi Lu "univ_192m_d4", 217acddfc2cSWeiyi Lu "univpll_d3_d16", 218acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 219acddfc2cSWeiyi Lu "univ_192m_d16", 220acddfc2cSWeiyi Lu "univ_192m_d32" 221acddfc2cSWeiyi Lu }; 222acddfc2cSWeiyi Lu 223acddfc2cSWeiyi Lu static const char * const camtg2_parents[] = { 224acddfc2cSWeiyi Lu "clk26m", 225acddfc2cSWeiyi Lu "univ_192m_d8", 226acddfc2cSWeiyi Lu "univpll_d3_d8", 227acddfc2cSWeiyi Lu "univ_192m_d4", 228acddfc2cSWeiyi Lu "univpll_d3_d16", 229acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 230acddfc2cSWeiyi Lu "univ_192m_d16", 231acddfc2cSWeiyi Lu "univ_192m_d32" 232acddfc2cSWeiyi Lu }; 233acddfc2cSWeiyi Lu 234acddfc2cSWeiyi Lu static const char * const camtg3_parents[] = { 235acddfc2cSWeiyi Lu "clk26m", 236acddfc2cSWeiyi Lu "univ_192m_d8", 237acddfc2cSWeiyi Lu "univpll_d3_d8", 238acddfc2cSWeiyi Lu "univ_192m_d4", 239acddfc2cSWeiyi Lu "univpll_d3_d16", 240acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 241acddfc2cSWeiyi Lu "univ_192m_d16", 242acddfc2cSWeiyi Lu "univ_192m_d32" 243acddfc2cSWeiyi Lu }; 244acddfc2cSWeiyi Lu 245acddfc2cSWeiyi Lu static const char * const camtg4_parents[] = { 246acddfc2cSWeiyi Lu "clk26m", 247acddfc2cSWeiyi Lu "univ_192m_d8", 248acddfc2cSWeiyi Lu "univpll_d3_d8", 249acddfc2cSWeiyi Lu "univ_192m_d4", 250acddfc2cSWeiyi Lu "univpll_d3_d16", 251acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 252acddfc2cSWeiyi Lu "univ_192m_d16", 253acddfc2cSWeiyi Lu "univ_192m_d32" 254acddfc2cSWeiyi Lu }; 255acddfc2cSWeiyi Lu 256acddfc2cSWeiyi Lu static const char * const uart_parents[] = { 257acddfc2cSWeiyi Lu "clk26m", 258acddfc2cSWeiyi Lu "univpll_d3_d8" 259acddfc2cSWeiyi Lu }; 260acddfc2cSWeiyi Lu 261acddfc2cSWeiyi Lu static const char * const spi_parents[] = { 262acddfc2cSWeiyi Lu "clk26m", 263acddfc2cSWeiyi Lu "syspll_d5_d2", 264acddfc2cSWeiyi Lu "syspll_d3_d4", 265acddfc2cSWeiyi Lu "msdcpll_d4" 266acddfc2cSWeiyi Lu }; 267acddfc2cSWeiyi Lu 268acddfc2cSWeiyi Lu static const char * const msdc50_hclk_parents[] = { 269acddfc2cSWeiyi Lu "clk26m", 270acddfc2cSWeiyi Lu "syspll_d2_d2", 271acddfc2cSWeiyi Lu "syspll_d3_d2" 272acddfc2cSWeiyi Lu }; 273acddfc2cSWeiyi Lu 274acddfc2cSWeiyi Lu static const char * const msdc50_0_parents[] = { 275acddfc2cSWeiyi Lu "clk26m", 276acddfc2cSWeiyi Lu "msdcpll_ck", 277acddfc2cSWeiyi Lu "msdcpll_d2", 278acddfc2cSWeiyi Lu "univpll_d2_d4", 279acddfc2cSWeiyi Lu "syspll_d3_d2", 280acddfc2cSWeiyi Lu "univpll_d2_d2" 281acddfc2cSWeiyi Lu }; 282acddfc2cSWeiyi Lu 283acddfc2cSWeiyi Lu static const char * const msdc30_1_parents[] = { 284acddfc2cSWeiyi Lu "clk26m", 285acddfc2cSWeiyi Lu "univpll_d3_d2", 286acddfc2cSWeiyi Lu "syspll_d3_d2", 287acddfc2cSWeiyi Lu "syspll_d7", 288acddfc2cSWeiyi Lu "msdcpll_d2" 289acddfc2cSWeiyi Lu }; 290acddfc2cSWeiyi Lu 291acddfc2cSWeiyi Lu static const char * const msdc30_2_parents[] = { 292acddfc2cSWeiyi Lu "clk26m", 293acddfc2cSWeiyi Lu "univpll_d3_d2", 294acddfc2cSWeiyi Lu "syspll_d3_d2", 295acddfc2cSWeiyi Lu "syspll_d7", 296acddfc2cSWeiyi Lu "msdcpll_d2" 297acddfc2cSWeiyi Lu }; 298acddfc2cSWeiyi Lu 299acddfc2cSWeiyi Lu static const char * const audio_parents[] = { 300acddfc2cSWeiyi Lu "clk26m", 301acddfc2cSWeiyi Lu "syspll_d5_d4", 302acddfc2cSWeiyi Lu "syspll_d7_d4", 303acddfc2cSWeiyi Lu "syspll_d2_d16" 304acddfc2cSWeiyi Lu }; 305acddfc2cSWeiyi Lu 306acddfc2cSWeiyi Lu static const char * const aud_intbus_parents[] = { 307acddfc2cSWeiyi Lu "clk26m", 308acddfc2cSWeiyi Lu "syspll_d2_d4", 309acddfc2cSWeiyi Lu "syspll_d7_d2" 310acddfc2cSWeiyi Lu }; 311acddfc2cSWeiyi Lu 312acddfc2cSWeiyi Lu static const char * const pmicspi_parents[] = { 313acddfc2cSWeiyi Lu "clk26m", 314acddfc2cSWeiyi Lu "syspll_d2_d8", 315acddfc2cSWeiyi Lu "osc_d8" 316acddfc2cSWeiyi Lu }; 317acddfc2cSWeiyi Lu 318acddfc2cSWeiyi Lu static const char * const fpwrap_ulposc_parents[] = { 319acddfc2cSWeiyi Lu "clk26m", 320acddfc2cSWeiyi Lu "osc_d16", 321acddfc2cSWeiyi Lu "osc_d4", 322acddfc2cSWeiyi Lu "osc_d8" 323acddfc2cSWeiyi Lu }; 324acddfc2cSWeiyi Lu 325acddfc2cSWeiyi Lu static const char * const atb_parents[] = { 326acddfc2cSWeiyi Lu "clk26m", 327acddfc2cSWeiyi Lu "syspll_d2_d2", 328acddfc2cSWeiyi Lu "syspll_d5" 329acddfc2cSWeiyi Lu }; 330acddfc2cSWeiyi Lu 331acddfc2cSWeiyi Lu static const char * const dpi0_parents[] = { 332acddfc2cSWeiyi Lu "clk26m", 333acddfc2cSWeiyi Lu "tvdpll_d2", 334acddfc2cSWeiyi Lu "tvdpll_d4", 335acddfc2cSWeiyi Lu "tvdpll_d8", 336acddfc2cSWeiyi Lu "tvdpll_d16", 337acddfc2cSWeiyi Lu "univpll_d5_d2", 338acddfc2cSWeiyi Lu "univpll_d3_d4", 339acddfc2cSWeiyi Lu "syspll_d3_d4", 340acddfc2cSWeiyi Lu "univpll_d3_d8" 341acddfc2cSWeiyi Lu }; 342acddfc2cSWeiyi Lu 343acddfc2cSWeiyi Lu static const char * const scam_parents[] = { 344acddfc2cSWeiyi Lu "clk26m", 345acddfc2cSWeiyi Lu "syspll_d5_d2" 346acddfc2cSWeiyi Lu }; 347acddfc2cSWeiyi Lu 348acddfc2cSWeiyi Lu static const char * const disppwm_parents[] = { 349acddfc2cSWeiyi Lu "clk26m", 350acddfc2cSWeiyi Lu "univpll_d3_d4", 351acddfc2cSWeiyi Lu "osc_d2", 352acddfc2cSWeiyi Lu "osc_d4", 353acddfc2cSWeiyi Lu "osc_d16" 354acddfc2cSWeiyi Lu }; 355acddfc2cSWeiyi Lu 356acddfc2cSWeiyi Lu static const char * const usb_top_parents[] = { 357acddfc2cSWeiyi Lu "clk26m", 358acddfc2cSWeiyi Lu "univpll_d5_d4", 359acddfc2cSWeiyi Lu "univpll_d3_d4", 360acddfc2cSWeiyi Lu "univpll_d5_d2" 361acddfc2cSWeiyi Lu }; 362acddfc2cSWeiyi Lu 363acddfc2cSWeiyi Lu 364acddfc2cSWeiyi Lu static const char * const ssusb_top_xhci_parents[] = { 365acddfc2cSWeiyi Lu "clk26m", 366acddfc2cSWeiyi Lu "univpll_d5_d4", 367acddfc2cSWeiyi Lu "univpll_d3_d4", 368acddfc2cSWeiyi Lu "univpll_d5_d2" 369acddfc2cSWeiyi Lu }; 370acddfc2cSWeiyi Lu 371acddfc2cSWeiyi Lu static const char * const spm_parents[] = { 372acddfc2cSWeiyi Lu "clk26m", 373acddfc2cSWeiyi Lu "syspll_d2_d8" 374acddfc2cSWeiyi Lu }; 375acddfc2cSWeiyi Lu 376acddfc2cSWeiyi Lu static const char * const i2c_parents[] = { 377acddfc2cSWeiyi Lu "clk26m", 378acddfc2cSWeiyi Lu "syspll_d2_d8", 379acddfc2cSWeiyi Lu "univpll_d5_d2" 380acddfc2cSWeiyi Lu }; 381acddfc2cSWeiyi Lu 382acddfc2cSWeiyi Lu static const char * const scp_parents[] = { 383acddfc2cSWeiyi Lu "clk26m", 384acddfc2cSWeiyi Lu "univpll_d2_d8", 385acddfc2cSWeiyi Lu "syspll_d5", 386acddfc2cSWeiyi Lu "syspll_d2_d2", 387acddfc2cSWeiyi Lu "univpll_d2_d2", 388acddfc2cSWeiyi Lu "syspll_d3", 389acddfc2cSWeiyi Lu "univpll_d3" 390acddfc2cSWeiyi Lu }; 391acddfc2cSWeiyi Lu 392acddfc2cSWeiyi Lu static const char * const seninf_parents[] = { 393acddfc2cSWeiyi Lu "clk26m", 394acddfc2cSWeiyi Lu "univpll_d2_d2", 395acddfc2cSWeiyi Lu "univpll_d3_d2", 396acddfc2cSWeiyi Lu "univpll_d2_d4" 397acddfc2cSWeiyi Lu }; 398acddfc2cSWeiyi Lu 399acddfc2cSWeiyi Lu static const char * const dxcc_parents[] = { 400acddfc2cSWeiyi Lu "clk26m", 401acddfc2cSWeiyi Lu "syspll_d2_d2", 402acddfc2cSWeiyi Lu "syspll_d2_d4", 403acddfc2cSWeiyi Lu "syspll_d2_d8" 404acddfc2cSWeiyi Lu }; 405acddfc2cSWeiyi Lu 406acddfc2cSWeiyi Lu static const char * const aud_engen1_parents[] = { 407acddfc2cSWeiyi Lu "clk26m", 408acddfc2cSWeiyi Lu "apll1_d2", 409acddfc2cSWeiyi Lu "apll1_d4", 410acddfc2cSWeiyi Lu "apll1_d8" 411acddfc2cSWeiyi Lu }; 412acddfc2cSWeiyi Lu 413acddfc2cSWeiyi Lu static const char * const aud_engen2_parents[] = { 414acddfc2cSWeiyi Lu "clk26m", 415acddfc2cSWeiyi Lu "apll2_d2", 416acddfc2cSWeiyi Lu "apll2_d4", 417acddfc2cSWeiyi Lu "apll2_d8" 418acddfc2cSWeiyi Lu }; 419acddfc2cSWeiyi Lu 420acddfc2cSWeiyi Lu static const char * const faes_ufsfde_parents[] = { 421acddfc2cSWeiyi Lu "clk26m", 422acddfc2cSWeiyi Lu "syspll_d2", 423acddfc2cSWeiyi Lu "syspll_d2_d2", 424acddfc2cSWeiyi Lu "syspll_d3", 425acddfc2cSWeiyi Lu "syspll_d2_d4", 426acddfc2cSWeiyi Lu "univpll_d3" 427acddfc2cSWeiyi Lu }; 428acddfc2cSWeiyi Lu 429acddfc2cSWeiyi Lu static const char * const fufs_parents[] = { 430acddfc2cSWeiyi Lu "clk26m", 431acddfc2cSWeiyi Lu "syspll_d2_d4", 432acddfc2cSWeiyi Lu "syspll_d2_d8", 433acddfc2cSWeiyi Lu "syspll_d2_d16" 434acddfc2cSWeiyi Lu }; 435acddfc2cSWeiyi Lu 436acddfc2cSWeiyi Lu static const char * const aud_1_parents[] = { 437acddfc2cSWeiyi Lu "clk26m", 438acddfc2cSWeiyi Lu "apll1_ck" 439acddfc2cSWeiyi Lu }; 440acddfc2cSWeiyi Lu 441acddfc2cSWeiyi Lu static const char * const aud_2_parents[] = { 442acddfc2cSWeiyi Lu "clk26m", 443acddfc2cSWeiyi Lu "apll2_ck" 444acddfc2cSWeiyi Lu }; 445acddfc2cSWeiyi Lu 446acddfc2cSWeiyi Lu /* 447acddfc2cSWeiyi Lu * CRITICAL CLOCK: 448acddfc2cSWeiyi Lu * axi_sel is the main bus clock of whole SOC. 449acddfc2cSWeiyi Lu * spm_sel is the clock of the always-on co-processor. 450acddfc2cSWeiyi Lu */ 451acddfc2cSWeiyi Lu static const struct mtk_mux top_muxes[] = { 452acddfc2cSWeiyi Lu /* CLK_CFG_0 */ 453acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 4541775790eSAngeloGioacchino Del Regno axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0, 4551775790eSAngeloGioacchino Del Regno CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 456acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 4572f140dabSAngeloGioacchino Del Regno mm_parents, 0x40, 0x44, 0x48, 8, 3, 15, 0x004, 1), 458acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 4592f140dabSAngeloGioacchino Del Regno img_parents, 0x40, 0x44, 0x48, 16, 3, 23, 0x004, 2), 460acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 4612f140dabSAngeloGioacchino Del Regno cam_parents, 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 3), 462acddfc2cSWeiyi Lu /* CLK_CFG_1 */ 463acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 4642f140dabSAngeloGioacchino Del Regno dsp_parents, 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 4), 465acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 4662f140dabSAngeloGioacchino Del Regno dsp1_parents, 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 5), 467acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 4682f140dabSAngeloGioacchino Del Regno dsp2_parents, 0x50, 0x54, 0x58, 16, 4, 23, 0x004, 6), 469acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 4702f140dabSAngeloGioacchino Del Regno ipu_if_parents, 0x50, 0x54, 0x58, 24, 4, 31, 0x004, 7), 471acddfc2cSWeiyi Lu /* CLK_CFG_2 */ 472acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 4732f140dabSAngeloGioacchino Del Regno mfg_parents, 0x60, 0x64, 0x68, 0, 2, 7, 0x004, 8), 474acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 4752f140dabSAngeloGioacchino Del Regno f52m_mfg_parents, 0x60, 0x64, 0x68, 8, 2, 15, 0x004, 9), 476acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 4772f140dabSAngeloGioacchino Del Regno camtg_parents, 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 10), 478acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 4792f140dabSAngeloGioacchino Del Regno camtg2_parents, 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 11), 480acddfc2cSWeiyi Lu /* CLK_CFG_3 */ 481acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 4822f140dabSAngeloGioacchino Del Regno camtg3_parents, 0x70, 0x74, 0x78, 0, 3, 7, 0x004, 12), 483acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 4842f140dabSAngeloGioacchino Del Regno camtg4_parents, 0x70, 0x74, 0x78, 8, 3, 15, 0x004, 13), 485acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 4862f140dabSAngeloGioacchino Del Regno uart_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x004, 14), 487acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 4882f140dabSAngeloGioacchino Del Regno spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15), 489acddfc2cSWeiyi Lu /* CLK_CFG_4 */ 490*f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 491*f235f6aeSAngeloGioacchino Del Regno msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16, 0), 492*f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 493*f235f6aeSAngeloGioacchino Del Regno msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17, 0), 494*f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 495*f235f6aeSAngeloGioacchino Del Regno msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18, 0), 496*f235f6aeSAngeloGioacchino Del Regno MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 497*f235f6aeSAngeloGioacchino Del Regno msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19, 0), 498acddfc2cSWeiyi Lu /* CLK_CFG_5 */ 499acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 5002f140dabSAngeloGioacchino Del Regno audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20), 501acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 5022f140dabSAngeloGioacchino Del Regno aud_intbus_parents, 0x90, 0x94, 0x98, 8, 2, 15, 0x004, 21), 503acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 5042f140dabSAngeloGioacchino Del Regno pmicspi_parents, 0x90, 0x94, 0x98, 16, 2, 23, 0x004, 22), 505acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 5062f140dabSAngeloGioacchino Del Regno fpwrap_ulposc_parents, 0x90, 0x94, 0x98, 24, 2, 31, 0x004, 23), 507acddfc2cSWeiyi Lu /* CLK_CFG_6 */ 508acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 5092f140dabSAngeloGioacchino Del Regno atb_parents, 0xa0, 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 510acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 5112f140dabSAngeloGioacchino Del Regno dpi0_parents, 0xa0, 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 512acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 5132f140dabSAngeloGioacchino Del Regno scam_parents, 0xa0, 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 514acddfc2cSWeiyi Lu /* CLK_CFG_7 */ 515acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 5162f140dabSAngeloGioacchino Del Regno disppwm_parents, 0xb0, 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 517acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 5182f140dabSAngeloGioacchino Del Regno usb_top_parents, 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 519acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 5202f140dabSAngeloGioacchino Del Regno ssusb_top_xhci_parents, 0xb0, 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 521acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 5221775790eSAngeloGioacchino Del Regno spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0, 5231775790eSAngeloGioacchino Del Regno CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 524acddfc2cSWeiyi Lu /* CLK_CFG_8 */ 525acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 5262f140dabSAngeloGioacchino Del Regno i2c_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 527acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 5282f140dabSAngeloGioacchino Del Regno scp_parents, 0xc0, 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 529acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 5302f140dabSAngeloGioacchino Del Regno seninf_parents, 0xc0, 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 531acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 5322f140dabSAngeloGioacchino Del Regno dxcc_parents, 0xc0, 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 533acddfc2cSWeiyi Lu /* CLK_CFG_9 */ 534acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 5352f140dabSAngeloGioacchino Del Regno aud_engen1_parents, 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 536acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 5372f140dabSAngeloGioacchino Del Regno aud_engen2_parents, 0xd0, 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 538acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 5392f140dabSAngeloGioacchino Del Regno faes_ufsfde_parents, 0xd0, 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 540acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 5412f140dabSAngeloGioacchino Del Regno fufs_parents, 0xd0, 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 542acddfc2cSWeiyi Lu /* CLK_CFG_10 */ 543acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 5442f140dabSAngeloGioacchino Del Regno aud_1_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 545acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 5462f140dabSAngeloGioacchino Del Regno aud_2_parents, 0xe0, 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 547acddfc2cSWeiyi Lu }; 548acddfc2cSWeiyi Lu 549acddfc2cSWeiyi Lu static const char * const apll_i2s0_parents[] = { 550acddfc2cSWeiyi Lu "aud_1_sel", 551acddfc2cSWeiyi Lu "aud_2_sel" 552acddfc2cSWeiyi Lu }; 553acddfc2cSWeiyi Lu 554acddfc2cSWeiyi Lu static const char * const apll_i2s1_parents[] = { 555acddfc2cSWeiyi Lu "aud_1_sel", 556acddfc2cSWeiyi Lu "aud_2_sel" 557acddfc2cSWeiyi Lu }; 558acddfc2cSWeiyi Lu 559acddfc2cSWeiyi Lu static const char * const apll_i2s2_parents[] = { 560acddfc2cSWeiyi Lu "aud_1_sel", 561acddfc2cSWeiyi Lu "aud_2_sel" 562acddfc2cSWeiyi Lu }; 563acddfc2cSWeiyi Lu 564acddfc2cSWeiyi Lu static const char * const apll_i2s3_parents[] = { 565acddfc2cSWeiyi Lu "aud_1_sel", 566acddfc2cSWeiyi Lu "aud_2_sel" 567acddfc2cSWeiyi Lu }; 568acddfc2cSWeiyi Lu 569acddfc2cSWeiyi Lu static const char * const apll_i2s4_parents[] = { 570acddfc2cSWeiyi Lu "aud_1_sel", 571acddfc2cSWeiyi Lu "aud_2_sel" 572acddfc2cSWeiyi Lu }; 573acddfc2cSWeiyi Lu 574acddfc2cSWeiyi Lu static const char * const apll_i2s5_parents[] = { 575acddfc2cSWeiyi Lu "aud_1_sel", 576acddfc2cSWeiyi Lu "aud_2_sel" 577acddfc2cSWeiyi Lu }; 578acddfc2cSWeiyi Lu 579acddfc2cSWeiyi Lu static const char * const mcu_mp0_parents[] = { 580acddfc2cSWeiyi Lu "clk26m", 581acddfc2cSWeiyi Lu "armpll_ll", 582acddfc2cSWeiyi Lu "armpll_div_pll1", 583acddfc2cSWeiyi Lu "armpll_div_pll2" 584acddfc2cSWeiyi Lu }; 585acddfc2cSWeiyi Lu 586acddfc2cSWeiyi Lu static const char * const mcu_mp2_parents[] = { 587acddfc2cSWeiyi Lu "clk26m", 588acddfc2cSWeiyi Lu "armpll_l", 589acddfc2cSWeiyi Lu "armpll_div_pll1", 590acddfc2cSWeiyi Lu "armpll_div_pll2" 591acddfc2cSWeiyi Lu }; 592acddfc2cSWeiyi Lu 593acddfc2cSWeiyi Lu static const char * const mcu_bus_parents[] = { 594acddfc2cSWeiyi Lu "clk26m", 595acddfc2cSWeiyi Lu "ccipll", 596acddfc2cSWeiyi Lu "armpll_div_pll1", 597acddfc2cSWeiyi Lu "armpll_div_pll2" 598acddfc2cSWeiyi Lu }; 599acddfc2cSWeiyi Lu 600acddfc2cSWeiyi Lu static struct mtk_composite mcu_muxes[] = { 601acddfc2cSWeiyi Lu /* mp0_pll_divider_cfg */ 602acddfc2cSWeiyi Lu MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 603acddfc2cSWeiyi Lu /* mp2_pll_divider_cfg */ 604acddfc2cSWeiyi Lu MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 605acddfc2cSWeiyi Lu /* bus_pll_divider_cfg */ 606acddfc2cSWeiyi Lu MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 607acddfc2cSWeiyi Lu }; 608acddfc2cSWeiyi Lu 609d7595ddeSAngeloGioacchino Del Regno static struct mtk_composite top_aud_comp[] = { 6102f140dabSAngeloGioacchino Del Regno MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 0x320, 8, 1), 6112f140dabSAngeloGioacchino Del Regno MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 0x320, 9, 1), 6122f140dabSAngeloGioacchino Del Regno MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 0x320, 10, 1), 6132f140dabSAngeloGioacchino Del Regno MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 0x320, 11, 1), 6142f140dabSAngeloGioacchino Del Regno MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 0x320, 12, 1), 6152f140dabSAngeloGioacchino Del Regno MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 0x328, 20, 1), 6162f140dabSAngeloGioacchino Del Regno DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 0x320, 2, 0x324, 8, 0), 6172f140dabSAngeloGioacchino Del Regno DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 0x320, 3, 0x324, 8, 8), 6182f140dabSAngeloGioacchino Del Regno DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 0x320, 4, 0x324, 8, 16), 6192f140dabSAngeloGioacchino Del Regno DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 0x320, 5, 0x324, 8, 24), 6202f140dabSAngeloGioacchino Del Regno DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 0x320, 6, 0x328, 8, 0), 6212f140dabSAngeloGioacchino Del Regno DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 7, 0x328, 8, 8), 622acddfc2cSWeiyi Lu }; 623acddfc2cSWeiyi Lu 624acddfc2cSWeiyi Lu static const struct mtk_gate_regs top_cg_regs = { 625acddfc2cSWeiyi Lu .set_ofs = 0x104, 626acddfc2cSWeiyi Lu .clr_ofs = 0x104, 627acddfc2cSWeiyi Lu .sta_ofs = 0x104, 628acddfc2cSWeiyi Lu }; 629acddfc2cSWeiyi Lu 630acddfc2cSWeiyi Lu #define GATE_TOP(_id, _name, _parent, _shift) \ 631acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 632acddfc2cSWeiyi Lu &mtk_clk_gate_ops_no_setclr_inv) 633acddfc2cSWeiyi Lu 634acddfc2cSWeiyi Lu static const struct mtk_gate top_clks[] = { 635acddfc2cSWeiyi Lu /* TOP */ 636acddfc2cSWeiyi Lu GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 637acddfc2cSWeiyi Lu GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 638acddfc2cSWeiyi Lu }; 639acddfc2cSWeiyi Lu 640acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra0_cg_regs = { 641acddfc2cSWeiyi Lu .set_ofs = 0x80, 642acddfc2cSWeiyi Lu .clr_ofs = 0x84, 643acddfc2cSWeiyi Lu .sta_ofs = 0x90, 644acddfc2cSWeiyi Lu }; 645acddfc2cSWeiyi Lu 646acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra1_cg_regs = { 647acddfc2cSWeiyi Lu .set_ofs = 0x88, 648acddfc2cSWeiyi Lu .clr_ofs = 0x8c, 649acddfc2cSWeiyi Lu .sta_ofs = 0x94, 650acddfc2cSWeiyi Lu }; 651acddfc2cSWeiyi Lu 652acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra2_cg_regs = { 653acddfc2cSWeiyi Lu .set_ofs = 0xa4, 654acddfc2cSWeiyi Lu .clr_ofs = 0xa8, 655acddfc2cSWeiyi Lu .sta_ofs = 0xac, 656acddfc2cSWeiyi Lu }; 657acddfc2cSWeiyi Lu 658acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra3_cg_regs = { 659acddfc2cSWeiyi Lu .set_ofs = 0xc0, 660acddfc2cSWeiyi Lu .clr_ofs = 0xc4, 661acddfc2cSWeiyi Lu .sta_ofs = 0xc8, 662acddfc2cSWeiyi Lu }; 663acddfc2cSWeiyi Lu 664acddfc2cSWeiyi Lu #define GATE_INFRA0(_id, _name, _parent, _shift) \ 665acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 666acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 667acddfc2cSWeiyi Lu 668acddfc2cSWeiyi Lu #define GATE_INFRA1(_id, _name, _parent, _shift) \ 669acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 670acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 671acddfc2cSWeiyi Lu 672acddfc2cSWeiyi Lu #define GATE_INFRA2(_id, _name, _parent, _shift) \ 673acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 674acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 675acddfc2cSWeiyi Lu 676acddfc2cSWeiyi Lu #define GATE_INFRA3(_id, _name, _parent, _shift) \ 677acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 678acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 679acddfc2cSWeiyi Lu 680acddfc2cSWeiyi Lu static const struct mtk_gate infra_clks[] = { 681acddfc2cSWeiyi Lu /* INFRA0 */ 6822f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0), 6832f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "axi_sel", 1), 6842f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "axi_sel", 2), 6852f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "axi_sel", 3), 6862f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", "scp_sel", 4), 6872f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "f_f26m_ck", 5), 6882f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 6892f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", "axi_sel", 8), 6902f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9), 6912f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 6922f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), 6932f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", "i2c_sel", 12), 6942f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), 6952f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), 6962f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15), 6972f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "i2c_sel", 16), 6982f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "i2c_sel", 17), 6992f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "i2c_sel", 18), 7002f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "i2c_sel", 19), 7012f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "i2c_sel", 21), 7022f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 7032f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 7042f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 7052f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 7062f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), 7072f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", "axi_sel", 28), 7082f140dabSAngeloGioacchino Del Regno GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 709acddfc2cSWeiyi Lu /* INFRA1 */ 7102f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), 7112f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_hclk_sel", 2), 7122f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "axi_sel", 4), 7132f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "axi_sel", 5), 7142f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", "msdc50_0_sel", 6), 7152f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", "f_f26m_ck", 7), 7162f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 7172f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 7182f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "f_f26m_ck", 10), 7192f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 7202f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), 7212f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), 7222f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "f_f26m_ck", 14), 7232f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", "msdc30_1_sel", 16), 7242f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", "msdc30_2_sel", 17), 7252f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", "axi_sel", 18), 7262f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", "axi_sel", 19), 7272f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20), 7282f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 7292f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), 7302f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 7312f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 7322f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), 7332f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), 7342f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", "axi_sel", 30), 7352f140dabSAngeloGioacchino Del Regno GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "f_f26m_ck", 31), 736acddfc2cSWeiyi Lu /* INFRA2 */ 7372f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "f_f26m_ck", 0), 7382f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_USB, "infra_usb", "usb_top_sel", 1), 7392f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", "axi_sel", 2), 7402f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", "axi_sel", 3), 7412f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", "f_f26m_ck", 4), 7422f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), 7432f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), 7442f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", "f_f26m_ck", 8), 7452f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), 7462f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), 7472f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", "ssusb_top_xhci_sel", 11), 7482f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "fufs_sel", 12), 7492f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", "fufs_sel", 13), 7502f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14), 7512f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), 7522f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), 7532f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), 7542f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), 7552f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), 7562f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), 7572f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), 7582f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), 7592f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), 7602f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), 7612f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", "axi_sel", 27), 7622f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "fufs_sel", 28), 7632f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "faes_ufsfde_sel", 29), 7642f140dabSAngeloGioacchino Del Regno GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "fufs_sel", 30), 765acddfc2cSWeiyi Lu /* INFRA3 */ 7662f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), 7672f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), 7682f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), 7692f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), 7702f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), 7712f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_hclk_sel", 7), 7722f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_hclk_sel", 8), 7732f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), 7742f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), 7752f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), 7762f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), 7772f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "f_f26m_ck", 20), 7782f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", "axi_sel", 21), 7792f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), 7802f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), 7812f140dabSAngeloGioacchino Del Regno GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), 782acddfc2cSWeiyi Lu }; 783acddfc2cSWeiyi Lu 784f9e55ac2SChunfeng Yun static const struct mtk_gate_regs peri_cg_regs = { 785f9e55ac2SChunfeng Yun .set_ofs = 0x20c, 786f9e55ac2SChunfeng Yun .clr_ofs = 0x20c, 787f9e55ac2SChunfeng Yun .sta_ofs = 0x20c, 788f9e55ac2SChunfeng Yun }; 789f9e55ac2SChunfeng Yun 790f9e55ac2SChunfeng Yun #define GATE_PERI(_id, _name, _parent, _shift) \ 791f9e55ac2SChunfeng Yun GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ 792f9e55ac2SChunfeng Yun &mtk_clk_gate_ops_no_setclr_inv) 793f9e55ac2SChunfeng Yun 794f9e55ac2SChunfeng Yun static const struct mtk_gate peri_clks[] = { 795f9e55ac2SChunfeng Yun GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), 796f9e55ac2SChunfeng Yun }; 797f9e55ac2SChunfeng Yun 798723e3671SRex-BC Chen static u16 infra_rst_ofs[] = { 799723e3671SRex-BC Chen INFRA_RST0_SET_OFFSET, 800723e3671SRex-BC Chen INFRA_RST1_SET_OFFSET, 801723e3671SRex-BC Chen INFRA_RST2_SET_OFFSET, 802723e3671SRex-BC Chen INFRA_RST3_SET_OFFSET, 803723e3671SRex-BC Chen }; 804723e3671SRex-BC Chen 8052d2a2900SRex-BC Chen static const struct mtk_clk_rst_desc clk_rst_desc = { 8062d2a2900SRex-BC Chen .version = MTK_RST_SET_CLR, 807723e3671SRex-BC Chen .rst_bank_ofs = infra_rst_ofs, 808723e3671SRex-BC Chen .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), 8092d2a2900SRex-BC Chen }; 8102d2a2900SRex-BC Chen 811ae333e63SChen-Yu Tsai /* Register mux notifier for MFG mux */ 812ae333e63SChen-Yu Tsai static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) 813ae333e63SChen-Yu Tsai { 814ae333e63SChen-Yu Tsai struct mtk_mux_nb *mfg_mux_nb; 815ae333e63SChen-Yu Tsai int i; 816ae333e63SChen-Yu Tsai 817ae333e63SChen-Yu Tsai mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); 818ae333e63SChen-Yu Tsai if (!mfg_mux_nb) 819ae333e63SChen-Yu Tsai return -ENOMEM; 820ae333e63SChen-Yu Tsai 821ae333e63SChen-Yu Tsai for (i = 0; i < ARRAY_SIZE(top_muxes); i++) 822ae333e63SChen-Yu Tsai if (top_muxes[i].id == CLK_TOP_MUX_MFG) 823ae333e63SChen-Yu Tsai break; 824ae333e63SChen-Yu Tsai if (i == ARRAY_SIZE(top_muxes)) 825ae333e63SChen-Yu Tsai return -EINVAL; 826ae333e63SChen-Yu Tsai 827ae333e63SChen-Yu Tsai mfg_mux_nb->ops = top_muxes[i].ops; 828ae333e63SChen-Yu Tsai mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */ 829ae333e63SChen-Yu Tsai 830ae333e63SChen-Yu Tsai return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); 831ae333e63SChen-Yu Tsai } 832ae333e63SChen-Yu Tsai 8330f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc infra_desc = { 8340f69a423SAngeloGioacchino Del Regno .clks = infra_clks, 8350f69a423SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(infra_clks), 8360f69a423SAngeloGioacchino Del Regno .rst_desc = &clk_rst_desc, 8370f69a423SAngeloGioacchino Del Regno }; 8380f69a423SAngeloGioacchino Del Regno 8393f37ba7cSAngeloGioacchino Del Regno static const struct mtk_clk_desc mcu_desc = { 8403f37ba7cSAngeloGioacchino Del Regno .composite_clks = mcu_muxes, 8413f37ba7cSAngeloGioacchino Del Regno .num_composite_clks = ARRAY_SIZE(mcu_muxes), 8423f37ba7cSAngeloGioacchino Del Regno .clk_lock = &mt8183_clk_lock, 8433f37ba7cSAngeloGioacchino Del Regno }; 8443f37ba7cSAngeloGioacchino Del Regno 8450f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc peri_desc = { 8460f69a423SAngeloGioacchino Del Regno .clks = peri_clks, 8470f69a423SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(peri_clks), 8480f69a423SAngeloGioacchino Del Regno }; 8490f69a423SAngeloGioacchino Del Regno 8503f37ba7cSAngeloGioacchino Del Regno static const struct mtk_clk_desc topck_desc = { 8513f37ba7cSAngeloGioacchino Del Regno .fixed_clks = top_fixed_clks, 8523f37ba7cSAngeloGioacchino Del Regno .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 8533f37ba7cSAngeloGioacchino Del Regno .factor_clks = top_divs, 8543f37ba7cSAngeloGioacchino Del Regno .num_factor_clks = ARRAY_SIZE(top_divs), 8553f37ba7cSAngeloGioacchino Del Regno .mux_clks = top_muxes, 8563f37ba7cSAngeloGioacchino Del Regno .num_mux_clks = ARRAY_SIZE(top_muxes), 8573f37ba7cSAngeloGioacchino Del Regno .composite_clks = top_aud_comp, 8583f37ba7cSAngeloGioacchino Del Regno .num_composite_clks = ARRAY_SIZE(top_aud_comp), 8593f37ba7cSAngeloGioacchino Del Regno .clks = top_clks, 8603f37ba7cSAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(top_clks), 8613f37ba7cSAngeloGioacchino Del Regno .clk_lock = &mt8183_clk_lock, 8623f37ba7cSAngeloGioacchino Del Regno .clk_notifier_func = clk_mt8183_reg_mfg_mux_notifier, 8633f37ba7cSAngeloGioacchino Del Regno .mfg_clk_idx = CLK_TOP_MUX_MFG, 8643f37ba7cSAngeloGioacchino Del Regno }; 8653f37ba7cSAngeloGioacchino Del Regno 8663f37ba7cSAngeloGioacchino Del Regno static const struct of_device_id of_match_clk_mt8183[] = { 8670f69a423SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc }, 8683f37ba7cSAngeloGioacchino Del Regno { .compatible = "mediatek,mt8183-mcucfg", .data = &mcu_desc }, 8690f69a423SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, }, 8703f37ba7cSAngeloGioacchino Del Regno { .compatible = "mediatek,mt8183-topckgen", .data = &topck_desc }, 8710f69a423SAngeloGioacchino Del Regno { /* sentinel */ } 8720f69a423SAngeloGioacchino Del Regno }; 87365c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt8183); 8740f69a423SAngeloGioacchino Del Regno 8753f37ba7cSAngeloGioacchino Del Regno static struct platform_driver clk_mt8183_drv = { 8760f69a423SAngeloGioacchino Del Regno .probe = mtk_clk_simple_probe, 8770f69a423SAngeloGioacchino Del Regno .remove = mtk_clk_simple_remove, 8780f69a423SAngeloGioacchino Del Regno .driver = { 879acddfc2cSWeiyi Lu .name = "clk-mt8183", 880acddfc2cSWeiyi Lu .of_match_table = of_match_clk_mt8183, 881acddfc2cSWeiyi Lu }, 882acddfc2cSWeiyi Lu }; 8833f37ba7cSAngeloGioacchino Del Regno module_platform_driver(clk_mt8183_drv) 884a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 885