1acddfc2cSWeiyi Lu // SPDX-License-Identifier: GPL-2.0 2acddfc2cSWeiyi Lu // 3acddfc2cSWeiyi Lu // Copyright (c) 2018 MediaTek Inc. 4acddfc2cSWeiyi Lu // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5acddfc2cSWeiyi Lu 6acddfc2cSWeiyi Lu #include <linux/delay.h> 7acddfc2cSWeiyi Lu #include <linux/mfd/syscon.h> 8acddfc2cSWeiyi Lu #include <linux/of.h> 9acddfc2cSWeiyi Lu #include <linux/of_address.h> 10acddfc2cSWeiyi Lu #include <linux/of_device.h> 11acddfc2cSWeiyi Lu #include <linux/platform_device.h> 12acddfc2cSWeiyi Lu #include <linux/slab.h> 13acddfc2cSWeiyi Lu 1439691fb6SChen-Yu Tsai #include "clk-gate.h" 15acddfc2cSWeiyi Lu #include "clk-mtk.h" 16acddfc2cSWeiyi Lu #include "clk-mux.h" 1739691fb6SChen-Yu Tsai #include "clk-pll.h" 18acddfc2cSWeiyi Lu 19acddfc2cSWeiyi Lu #include <dt-bindings/clock/mt8183-clk.h> 20acddfc2cSWeiyi Lu 21acddfc2cSWeiyi Lu static DEFINE_SPINLOCK(mt8183_clk_lock); 22acddfc2cSWeiyi Lu 23acddfc2cSWeiyi Lu static const struct mtk_fixed_clk top_fixed_clks[] = { 24acddfc2cSWeiyi Lu FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 25acddfc2cSWeiyi Lu FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 26acddfc2cSWeiyi Lu FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 27acddfc2cSWeiyi Lu }; 28acddfc2cSWeiyi Lu 29c93d059aSWeiyi Lu static const struct mtk_fixed_factor top_early_divs[] = { 30c93d059aSWeiyi Lu FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), 31c93d059aSWeiyi Lu }; 32c93d059aSWeiyi Lu 33acddfc2cSWeiyi Lu static const struct mtk_fixed_factor top_divs[] = { 3423037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2), 35c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0), 36c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0), 37c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0), 38c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0), 39c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0), 40c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0), 41c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0), 42c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0), 43c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0), 44c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0), 45c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0), 46c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0), 47c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 4, 0), 48c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0), 49c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 2, 0), 50c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 4, 0), 51c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1, 0), 52c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2, 0), 53c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0), 54c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0), 55c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8, 0), 56c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0), 57c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0), 58c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0), 59c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0), 60c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0), 61c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0), 62c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0), 63c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0), 64c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0), 65c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 1, 0), 66c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 2, 0), 67c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 4, 0), 68c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 8, 0), 69c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 16, 0), 70c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 32, 0), 7123037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1), 7223037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 7323037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 7423037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 7523037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1), 7623037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 7723037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 7823037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 7923037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1), 8023037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 8123037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 8223037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 8323037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 8423037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1), 8523037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 8623037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 8723037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4), 8823037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 8923037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 9023037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4), 9123037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 9223037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 9323037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1), 9423037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1), 9523037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 9623037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 9723037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8), 9823037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16), 9923037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1), 10023037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2), 10123037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4), 10223037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8), 10323037ab6SAngeloGioacchino Del Regno FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16), 104c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0), 105c01d64caSAngeloGioacchino Del Regno FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16, 0), 106acddfc2cSWeiyi Lu }; 107acddfc2cSWeiyi Lu 108acddfc2cSWeiyi Lu static const char * const axi_parents[] = { 109acddfc2cSWeiyi Lu "clk26m", 110acddfc2cSWeiyi Lu "syspll_d2_d4", 111acddfc2cSWeiyi Lu "syspll_d7", 112acddfc2cSWeiyi Lu "osc_d4" 113acddfc2cSWeiyi Lu }; 114acddfc2cSWeiyi Lu 115acddfc2cSWeiyi Lu static const char * const mm_parents[] = { 116acddfc2cSWeiyi Lu "clk26m", 117acddfc2cSWeiyi Lu "mmpll_d7", 118acddfc2cSWeiyi Lu "syspll_d3", 119acddfc2cSWeiyi Lu "univpll_d2_d2", 120acddfc2cSWeiyi Lu "syspll_d2_d2", 121acddfc2cSWeiyi Lu "syspll_d3_d2" 122acddfc2cSWeiyi Lu }; 123acddfc2cSWeiyi Lu 124acddfc2cSWeiyi Lu static const char * const img_parents[] = { 125acddfc2cSWeiyi Lu "clk26m", 126acddfc2cSWeiyi Lu "mmpll_d6", 127acddfc2cSWeiyi Lu "univpll_d3", 128acddfc2cSWeiyi Lu "syspll_d3", 129acddfc2cSWeiyi Lu "univpll_d2_d2", 130acddfc2cSWeiyi Lu "syspll_d2_d2", 131acddfc2cSWeiyi Lu "univpll_d3_d2", 132acddfc2cSWeiyi Lu "syspll_d3_d2" 133acddfc2cSWeiyi Lu }; 134acddfc2cSWeiyi Lu 135acddfc2cSWeiyi Lu static const char * const cam_parents[] = { 136acddfc2cSWeiyi Lu "clk26m", 137acddfc2cSWeiyi Lu "syspll_d2", 138acddfc2cSWeiyi Lu "mmpll_d6", 139acddfc2cSWeiyi Lu "syspll_d3", 140acddfc2cSWeiyi Lu "mmpll_d7", 141acddfc2cSWeiyi Lu "univpll_d3", 142acddfc2cSWeiyi Lu "univpll_d2_d2", 143acddfc2cSWeiyi Lu "syspll_d2_d2", 144acddfc2cSWeiyi Lu "syspll_d3_d2", 145acddfc2cSWeiyi Lu "univpll_d3_d2" 146acddfc2cSWeiyi Lu }; 147acddfc2cSWeiyi Lu 148acddfc2cSWeiyi Lu static const char * const dsp_parents[] = { 149acddfc2cSWeiyi Lu "clk26m", 150acddfc2cSWeiyi Lu "mmpll_d6", 151acddfc2cSWeiyi Lu "mmpll_d7", 152acddfc2cSWeiyi Lu "univpll_d3", 153acddfc2cSWeiyi Lu "syspll_d3", 154acddfc2cSWeiyi Lu "univpll_d2_d2", 155acddfc2cSWeiyi Lu "syspll_d2_d2", 156acddfc2cSWeiyi Lu "univpll_d3_d2", 157acddfc2cSWeiyi Lu "syspll_d3_d2" 158acddfc2cSWeiyi Lu }; 159acddfc2cSWeiyi Lu 160acddfc2cSWeiyi Lu static const char * const dsp1_parents[] = { 161acddfc2cSWeiyi Lu "clk26m", 162acddfc2cSWeiyi Lu "mmpll_d6", 163acddfc2cSWeiyi Lu "mmpll_d7", 164acddfc2cSWeiyi Lu "univpll_d3", 165acddfc2cSWeiyi Lu "syspll_d3", 166acddfc2cSWeiyi Lu "univpll_d2_d2", 167acddfc2cSWeiyi Lu "syspll_d2_d2", 168acddfc2cSWeiyi Lu "univpll_d3_d2", 169acddfc2cSWeiyi Lu "syspll_d3_d2" 170acddfc2cSWeiyi Lu }; 171acddfc2cSWeiyi Lu 172acddfc2cSWeiyi Lu static const char * const dsp2_parents[] = { 173acddfc2cSWeiyi Lu "clk26m", 174acddfc2cSWeiyi Lu "mmpll_d6", 175acddfc2cSWeiyi Lu "mmpll_d7", 176acddfc2cSWeiyi Lu "univpll_d3", 177acddfc2cSWeiyi Lu "syspll_d3", 178acddfc2cSWeiyi Lu "univpll_d2_d2", 179acddfc2cSWeiyi Lu "syspll_d2_d2", 180acddfc2cSWeiyi Lu "univpll_d3_d2", 181acddfc2cSWeiyi Lu "syspll_d3_d2" 182acddfc2cSWeiyi Lu }; 183acddfc2cSWeiyi Lu 184acddfc2cSWeiyi Lu static const char * const ipu_if_parents[] = { 185acddfc2cSWeiyi Lu "clk26m", 186acddfc2cSWeiyi Lu "mmpll_d6", 187acddfc2cSWeiyi Lu "mmpll_d7", 188acddfc2cSWeiyi Lu "univpll_d3", 189acddfc2cSWeiyi Lu "syspll_d3", 190acddfc2cSWeiyi Lu "univpll_d2_d2", 191acddfc2cSWeiyi Lu "syspll_d2_d2", 192acddfc2cSWeiyi Lu "univpll_d3_d2", 193acddfc2cSWeiyi Lu "syspll_d3_d2" 194acddfc2cSWeiyi Lu }; 195acddfc2cSWeiyi Lu 196acddfc2cSWeiyi Lu static const char * const mfg_parents[] = { 197acddfc2cSWeiyi Lu "clk26m", 198acddfc2cSWeiyi Lu "mfgpll_ck", 199acddfc2cSWeiyi Lu "univpll_d3", 200acddfc2cSWeiyi Lu "syspll_d3" 201acddfc2cSWeiyi Lu }; 202acddfc2cSWeiyi Lu 203acddfc2cSWeiyi Lu static const char * const f52m_mfg_parents[] = { 204acddfc2cSWeiyi Lu "clk26m", 205acddfc2cSWeiyi Lu "univpll_d3_d2", 206acddfc2cSWeiyi Lu "univpll_d3_d4", 207acddfc2cSWeiyi Lu "univpll_d3_d8" 208acddfc2cSWeiyi Lu }; 209acddfc2cSWeiyi Lu 210acddfc2cSWeiyi Lu static const char * const camtg_parents[] = { 211acddfc2cSWeiyi Lu "clk26m", 212acddfc2cSWeiyi Lu "univ_192m_d8", 213acddfc2cSWeiyi Lu "univpll_d3_d8", 214acddfc2cSWeiyi Lu "univ_192m_d4", 215acddfc2cSWeiyi Lu "univpll_d3_d16", 216acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 217acddfc2cSWeiyi Lu "univ_192m_d16", 218acddfc2cSWeiyi Lu "univ_192m_d32" 219acddfc2cSWeiyi Lu }; 220acddfc2cSWeiyi Lu 221acddfc2cSWeiyi Lu static const char * const camtg2_parents[] = { 222acddfc2cSWeiyi Lu "clk26m", 223acddfc2cSWeiyi Lu "univ_192m_d8", 224acddfc2cSWeiyi Lu "univpll_d3_d8", 225acddfc2cSWeiyi Lu "univ_192m_d4", 226acddfc2cSWeiyi Lu "univpll_d3_d16", 227acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 228acddfc2cSWeiyi Lu "univ_192m_d16", 229acddfc2cSWeiyi Lu "univ_192m_d32" 230acddfc2cSWeiyi Lu }; 231acddfc2cSWeiyi Lu 232acddfc2cSWeiyi Lu static const char * const camtg3_parents[] = { 233acddfc2cSWeiyi Lu "clk26m", 234acddfc2cSWeiyi Lu "univ_192m_d8", 235acddfc2cSWeiyi Lu "univpll_d3_d8", 236acddfc2cSWeiyi Lu "univ_192m_d4", 237acddfc2cSWeiyi Lu "univpll_d3_d16", 238acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 239acddfc2cSWeiyi Lu "univ_192m_d16", 240acddfc2cSWeiyi Lu "univ_192m_d32" 241acddfc2cSWeiyi Lu }; 242acddfc2cSWeiyi Lu 243acddfc2cSWeiyi Lu static const char * const camtg4_parents[] = { 244acddfc2cSWeiyi Lu "clk26m", 245acddfc2cSWeiyi Lu "univ_192m_d8", 246acddfc2cSWeiyi Lu "univpll_d3_d8", 247acddfc2cSWeiyi Lu "univ_192m_d4", 248acddfc2cSWeiyi Lu "univpll_d3_d16", 249acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 250acddfc2cSWeiyi Lu "univ_192m_d16", 251acddfc2cSWeiyi Lu "univ_192m_d32" 252acddfc2cSWeiyi Lu }; 253acddfc2cSWeiyi Lu 254acddfc2cSWeiyi Lu static const char * const uart_parents[] = { 255acddfc2cSWeiyi Lu "clk26m", 256acddfc2cSWeiyi Lu "univpll_d3_d8" 257acddfc2cSWeiyi Lu }; 258acddfc2cSWeiyi Lu 259acddfc2cSWeiyi Lu static const char * const spi_parents[] = { 260acddfc2cSWeiyi Lu "clk26m", 261acddfc2cSWeiyi Lu "syspll_d5_d2", 262acddfc2cSWeiyi Lu "syspll_d3_d4", 263acddfc2cSWeiyi Lu "msdcpll_d4" 264acddfc2cSWeiyi Lu }; 265acddfc2cSWeiyi Lu 266acddfc2cSWeiyi Lu static const char * const msdc50_hclk_parents[] = { 267acddfc2cSWeiyi Lu "clk26m", 268acddfc2cSWeiyi Lu "syspll_d2_d2", 269acddfc2cSWeiyi Lu "syspll_d3_d2" 270acddfc2cSWeiyi Lu }; 271acddfc2cSWeiyi Lu 272acddfc2cSWeiyi Lu static const char * const msdc50_0_parents[] = { 273acddfc2cSWeiyi Lu "clk26m", 274acddfc2cSWeiyi Lu "msdcpll_ck", 275acddfc2cSWeiyi Lu "msdcpll_d2", 276acddfc2cSWeiyi Lu "univpll_d2_d4", 277acddfc2cSWeiyi Lu "syspll_d3_d2", 278acddfc2cSWeiyi Lu "univpll_d2_d2" 279acddfc2cSWeiyi Lu }; 280acddfc2cSWeiyi Lu 281acddfc2cSWeiyi Lu static const char * const msdc30_1_parents[] = { 282acddfc2cSWeiyi Lu "clk26m", 283acddfc2cSWeiyi Lu "univpll_d3_d2", 284acddfc2cSWeiyi Lu "syspll_d3_d2", 285acddfc2cSWeiyi Lu "syspll_d7", 286acddfc2cSWeiyi Lu "msdcpll_d2" 287acddfc2cSWeiyi Lu }; 288acddfc2cSWeiyi Lu 289acddfc2cSWeiyi Lu static const char * const msdc30_2_parents[] = { 290acddfc2cSWeiyi Lu "clk26m", 291acddfc2cSWeiyi Lu "univpll_d3_d2", 292acddfc2cSWeiyi Lu "syspll_d3_d2", 293acddfc2cSWeiyi Lu "syspll_d7", 294acddfc2cSWeiyi Lu "msdcpll_d2" 295acddfc2cSWeiyi Lu }; 296acddfc2cSWeiyi Lu 297acddfc2cSWeiyi Lu static const char * const audio_parents[] = { 298acddfc2cSWeiyi Lu "clk26m", 299acddfc2cSWeiyi Lu "syspll_d5_d4", 300acddfc2cSWeiyi Lu "syspll_d7_d4", 301acddfc2cSWeiyi Lu "syspll_d2_d16" 302acddfc2cSWeiyi Lu }; 303acddfc2cSWeiyi Lu 304acddfc2cSWeiyi Lu static const char * const aud_intbus_parents[] = { 305acddfc2cSWeiyi Lu "clk26m", 306acddfc2cSWeiyi Lu "syspll_d2_d4", 307acddfc2cSWeiyi Lu "syspll_d7_d2" 308acddfc2cSWeiyi Lu }; 309acddfc2cSWeiyi Lu 310acddfc2cSWeiyi Lu static const char * const pmicspi_parents[] = { 311acddfc2cSWeiyi Lu "clk26m", 312acddfc2cSWeiyi Lu "syspll_d2_d8", 313acddfc2cSWeiyi Lu "osc_d8" 314acddfc2cSWeiyi Lu }; 315acddfc2cSWeiyi Lu 316acddfc2cSWeiyi Lu static const char * const fpwrap_ulposc_parents[] = { 317acddfc2cSWeiyi Lu "clk26m", 318acddfc2cSWeiyi Lu "osc_d16", 319acddfc2cSWeiyi Lu "osc_d4", 320acddfc2cSWeiyi Lu "osc_d8" 321acddfc2cSWeiyi Lu }; 322acddfc2cSWeiyi Lu 323acddfc2cSWeiyi Lu static const char * const atb_parents[] = { 324acddfc2cSWeiyi Lu "clk26m", 325acddfc2cSWeiyi Lu "syspll_d2_d2", 326acddfc2cSWeiyi Lu "syspll_d5" 327acddfc2cSWeiyi Lu }; 328acddfc2cSWeiyi Lu 329acddfc2cSWeiyi Lu static const char * const dpi0_parents[] = { 330acddfc2cSWeiyi Lu "clk26m", 331acddfc2cSWeiyi Lu "tvdpll_d2", 332acddfc2cSWeiyi Lu "tvdpll_d4", 333acddfc2cSWeiyi Lu "tvdpll_d8", 334acddfc2cSWeiyi Lu "tvdpll_d16", 335acddfc2cSWeiyi Lu "univpll_d5_d2", 336acddfc2cSWeiyi Lu "univpll_d3_d4", 337acddfc2cSWeiyi Lu "syspll_d3_d4", 338acddfc2cSWeiyi Lu "univpll_d3_d8" 339acddfc2cSWeiyi Lu }; 340acddfc2cSWeiyi Lu 341acddfc2cSWeiyi Lu static const char * const scam_parents[] = { 342acddfc2cSWeiyi Lu "clk26m", 343acddfc2cSWeiyi Lu "syspll_d5_d2" 344acddfc2cSWeiyi Lu }; 345acddfc2cSWeiyi Lu 346acddfc2cSWeiyi Lu static const char * const disppwm_parents[] = { 347acddfc2cSWeiyi Lu "clk26m", 348acddfc2cSWeiyi Lu "univpll_d3_d4", 349acddfc2cSWeiyi Lu "osc_d2", 350acddfc2cSWeiyi Lu "osc_d4", 351acddfc2cSWeiyi Lu "osc_d16" 352acddfc2cSWeiyi Lu }; 353acddfc2cSWeiyi Lu 354acddfc2cSWeiyi Lu static const char * const usb_top_parents[] = { 355acddfc2cSWeiyi Lu "clk26m", 356acddfc2cSWeiyi Lu "univpll_d5_d4", 357acddfc2cSWeiyi Lu "univpll_d3_d4", 358acddfc2cSWeiyi Lu "univpll_d5_d2" 359acddfc2cSWeiyi Lu }; 360acddfc2cSWeiyi Lu 361acddfc2cSWeiyi Lu 362acddfc2cSWeiyi Lu static const char * const ssusb_top_xhci_parents[] = { 363acddfc2cSWeiyi Lu "clk26m", 364acddfc2cSWeiyi Lu "univpll_d5_d4", 365acddfc2cSWeiyi Lu "univpll_d3_d4", 366acddfc2cSWeiyi Lu "univpll_d5_d2" 367acddfc2cSWeiyi Lu }; 368acddfc2cSWeiyi Lu 369acddfc2cSWeiyi Lu static const char * const spm_parents[] = { 370acddfc2cSWeiyi Lu "clk26m", 371acddfc2cSWeiyi Lu "syspll_d2_d8" 372acddfc2cSWeiyi Lu }; 373acddfc2cSWeiyi Lu 374acddfc2cSWeiyi Lu static const char * const i2c_parents[] = { 375acddfc2cSWeiyi Lu "clk26m", 376acddfc2cSWeiyi Lu "syspll_d2_d8", 377acddfc2cSWeiyi Lu "univpll_d5_d2" 378acddfc2cSWeiyi Lu }; 379acddfc2cSWeiyi Lu 380acddfc2cSWeiyi Lu static const char * const scp_parents[] = { 381acddfc2cSWeiyi Lu "clk26m", 382acddfc2cSWeiyi Lu "univpll_d2_d8", 383acddfc2cSWeiyi Lu "syspll_d5", 384acddfc2cSWeiyi Lu "syspll_d2_d2", 385acddfc2cSWeiyi Lu "univpll_d2_d2", 386acddfc2cSWeiyi Lu "syspll_d3", 387acddfc2cSWeiyi Lu "univpll_d3" 388acddfc2cSWeiyi Lu }; 389acddfc2cSWeiyi Lu 390acddfc2cSWeiyi Lu static const char * const seninf_parents[] = { 391acddfc2cSWeiyi Lu "clk26m", 392acddfc2cSWeiyi Lu "univpll_d2_d2", 393acddfc2cSWeiyi Lu "univpll_d3_d2", 394acddfc2cSWeiyi Lu "univpll_d2_d4" 395acddfc2cSWeiyi Lu }; 396acddfc2cSWeiyi Lu 397acddfc2cSWeiyi Lu static const char * const dxcc_parents[] = { 398acddfc2cSWeiyi Lu "clk26m", 399acddfc2cSWeiyi Lu "syspll_d2_d2", 400acddfc2cSWeiyi Lu "syspll_d2_d4", 401acddfc2cSWeiyi Lu "syspll_d2_d8" 402acddfc2cSWeiyi Lu }; 403acddfc2cSWeiyi Lu 404acddfc2cSWeiyi Lu static const char * const aud_engen1_parents[] = { 405acddfc2cSWeiyi Lu "clk26m", 406acddfc2cSWeiyi Lu "apll1_d2", 407acddfc2cSWeiyi Lu "apll1_d4", 408acddfc2cSWeiyi Lu "apll1_d8" 409acddfc2cSWeiyi Lu }; 410acddfc2cSWeiyi Lu 411acddfc2cSWeiyi Lu static const char * const aud_engen2_parents[] = { 412acddfc2cSWeiyi Lu "clk26m", 413acddfc2cSWeiyi Lu "apll2_d2", 414acddfc2cSWeiyi Lu "apll2_d4", 415acddfc2cSWeiyi Lu "apll2_d8" 416acddfc2cSWeiyi Lu }; 417acddfc2cSWeiyi Lu 418acddfc2cSWeiyi Lu static const char * const faes_ufsfde_parents[] = { 419acddfc2cSWeiyi Lu "clk26m", 420acddfc2cSWeiyi Lu "syspll_d2", 421acddfc2cSWeiyi Lu "syspll_d2_d2", 422acddfc2cSWeiyi Lu "syspll_d3", 423acddfc2cSWeiyi Lu "syspll_d2_d4", 424acddfc2cSWeiyi Lu "univpll_d3" 425acddfc2cSWeiyi Lu }; 426acddfc2cSWeiyi Lu 427acddfc2cSWeiyi Lu static const char * const fufs_parents[] = { 428acddfc2cSWeiyi Lu "clk26m", 429acddfc2cSWeiyi Lu "syspll_d2_d4", 430acddfc2cSWeiyi Lu "syspll_d2_d8", 431acddfc2cSWeiyi Lu "syspll_d2_d16" 432acddfc2cSWeiyi Lu }; 433acddfc2cSWeiyi Lu 434acddfc2cSWeiyi Lu static const char * const aud_1_parents[] = { 435acddfc2cSWeiyi Lu "clk26m", 436acddfc2cSWeiyi Lu "apll1_ck" 437acddfc2cSWeiyi Lu }; 438acddfc2cSWeiyi Lu 439acddfc2cSWeiyi Lu static const char * const aud_2_parents[] = { 440acddfc2cSWeiyi Lu "clk26m", 441acddfc2cSWeiyi Lu "apll2_ck" 442acddfc2cSWeiyi Lu }; 443acddfc2cSWeiyi Lu 444acddfc2cSWeiyi Lu /* 445acddfc2cSWeiyi Lu * CRITICAL CLOCK: 446acddfc2cSWeiyi Lu * axi_sel is the main bus clock of whole SOC. 447acddfc2cSWeiyi Lu * spm_sel is the clock of the always-on co-processor. 448acddfc2cSWeiyi Lu */ 449acddfc2cSWeiyi Lu static const struct mtk_mux top_muxes[] = { 450acddfc2cSWeiyi Lu /* CLK_CFG_0 */ 451acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 452acddfc2cSWeiyi Lu axi_parents, 0x40, 453acddfc2cSWeiyi Lu 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), 454acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 455acddfc2cSWeiyi Lu mm_parents, 0x40, 456acddfc2cSWeiyi Lu 0x44, 0x48, 8, 3, 15, 0x004, 1), 457acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 458acddfc2cSWeiyi Lu img_parents, 0x40, 459acddfc2cSWeiyi Lu 0x44, 0x48, 16, 3, 23, 0x004, 2), 460acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 461acddfc2cSWeiyi Lu cam_parents, 0x40, 462acddfc2cSWeiyi Lu 0x44, 0x48, 24, 4, 31, 0x004, 3), 463acddfc2cSWeiyi Lu /* CLK_CFG_1 */ 464acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 465acddfc2cSWeiyi Lu dsp_parents, 0x50, 466acddfc2cSWeiyi Lu 0x54, 0x58, 0, 4, 7, 0x004, 4), 467acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 468acddfc2cSWeiyi Lu dsp1_parents, 0x50, 469acddfc2cSWeiyi Lu 0x54, 0x58, 8, 4, 15, 0x004, 5), 470acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 471acddfc2cSWeiyi Lu dsp2_parents, 0x50, 472acddfc2cSWeiyi Lu 0x54, 0x58, 16, 4, 23, 0x004, 6), 473acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 474acddfc2cSWeiyi Lu ipu_if_parents, 0x50, 475acddfc2cSWeiyi Lu 0x54, 0x58, 24, 4, 31, 0x004, 7), 476acddfc2cSWeiyi Lu /* CLK_CFG_2 */ 477acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 478acddfc2cSWeiyi Lu mfg_parents, 0x60, 479acddfc2cSWeiyi Lu 0x64, 0x68, 0, 2, 7, 0x004, 8), 480acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 481acddfc2cSWeiyi Lu f52m_mfg_parents, 0x60, 482acddfc2cSWeiyi Lu 0x64, 0x68, 8, 2, 15, 0x004, 9), 483acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 484acddfc2cSWeiyi Lu camtg_parents, 0x60, 485acddfc2cSWeiyi Lu 0x64, 0x68, 16, 3, 23, 0x004, 10), 486acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 487acddfc2cSWeiyi Lu camtg2_parents, 0x60, 488acddfc2cSWeiyi Lu 0x64, 0x68, 24, 3, 31, 0x004, 11), 489acddfc2cSWeiyi Lu /* CLK_CFG_3 */ 490acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 491acddfc2cSWeiyi Lu camtg3_parents, 0x70, 492acddfc2cSWeiyi Lu 0x74, 0x78, 0, 3, 7, 0x004, 12), 493acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 494acddfc2cSWeiyi Lu camtg4_parents, 0x70, 495acddfc2cSWeiyi Lu 0x74, 0x78, 8, 3, 15, 0x004, 13), 496acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 497acddfc2cSWeiyi Lu uart_parents, 0x70, 498acddfc2cSWeiyi Lu 0x74, 0x78, 16, 1, 23, 0x004, 14), 499acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 500acddfc2cSWeiyi Lu spi_parents, 0x70, 501acddfc2cSWeiyi Lu 0x74, 0x78, 24, 2, 31, 0x004, 15), 502acddfc2cSWeiyi Lu /* CLK_CFG_4 */ 503acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 504acddfc2cSWeiyi Lu msdc50_hclk_parents, 0x80, 505acddfc2cSWeiyi Lu 0x84, 0x88, 0, 2, 7, 0x004, 16), 506acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 507acddfc2cSWeiyi Lu msdc50_0_parents, 0x80, 508acddfc2cSWeiyi Lu 0x84, 0x88, 8, 3, 15, 0x004, 17), 509acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 510acddfc2cSWeiyi Lu msdc30_1_parents, 0x80, 511acddfc2cSWeiyi Lu 0x84, 0x88, 16, 3, 23, 0x004, 18), 512acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 513acddfc2cSWeiyi Lu msdc30_2_parents, 0x80, 514acddfc2cSWeiyi Lu 0x84, 0x88, 24, 3, 31, 0x004, 19), 515acddfc2cSWeiyi Lu /* CLK_CFG_5 */ 516acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 517acddfc2cSWeiyi Lu audio_parents, 0x90, 518acddfc2cSWeiyi Lu 0x94, 0x98, 0, 2, 7, 0x004, 20), 519acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 520acddfc2cSWeiyi Lu aud_intbus_parents, 0x90, 521acddfc2cSWeiyi Lu 0x94, 0x98, 8, 2, 15, 0x004, 21), 522acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 523acddfc2cSWeiyi Lu pmicspi_parents, 0x90, 524acddfc2cSWeiyi Lu 0x94, 0x98, 16, 2, 23, 0x004, 22), 525acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 526acddfc2cSWeiyi Lu fpwrap_ulposc_parents, 0x90, 527acddfc2cSWeiyi Lu 0x94, 0x98, 24, 2, 31, 0x004, 23), 528acddfc2cSWeiyi Lu /* CLK_CFG_6 */ 529acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 530acddfc2cSWeiyi Lu atb_parents, 0xa0, 531acddfc2cSWeiyi Lu 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 532acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 533acddfc2cSWeiyi Lu dpi0_parents, 0xa0, 534acddfc2cSWeiyi Lu 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 535acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 536acddfc2cSWeiyi Lu scam_parents, 0xa0, 537acddfc2cSWeiyi Lu 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 538acddfc2cSWeiyi Lu /* CLK_CFG_7 */ 539acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 540acddfc2cSWeiyi Lu disppwm_parents, 0xb0, 541acddfc2cSWeiyi Lu 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 542acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 543acddfc2cSWeiyi Lu usb_top_parents, 0xb0, 544acddfc2cSWeiyi Lu 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 545acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 546acddfc2cSWeiyi Lu ssusb_top_xhci_parents, 0xb0, 547acddfc2cSWeiyi Lu 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 548acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 549acddfc2cSWeiyi Lu spm_parents, 0xb0, 550acddfc2cSWeiyi Lu 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), 551acddfc2cSWeiyi Lu /* CLK_CFG_8 */ 552acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 553acddfc2cSWeiyi Lu i2c_parents, 0xc0, 554acddfc2cSWeiyi Lu 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 555acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 556acddfc2cSWeiyi Lu scp_parents, 0xc0, 557acddfc2cSWeiyi Lu 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 558acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 559acddfc2cSWeiyi Lu seninf_parents, 0xc0, 560acddfc2cSWeiyi Lu 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 561acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 562acddfc2cSWeiyi Lu dxcc_parents, 0xc0, 563acddfc2cSWeiyi Lu 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 564acddfc2cSWeiyi Lu /* CLK_CFG_9 */ 565acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 566acddfc2cSWeiyi Lu aud_engen1_parents, 0xd0, 567acddfc2cSWeiyi Lu 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 568acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 569acddfc2cSWeiyi Lu aud_engen2_parents, 0xd0, 570acddfc2cSWeiyi Lu 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 571acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 572acddfc2cSWeiyi Lu faes_ufsfde_parents, 0xd0, 573acddfc2cSWeiyi Lu 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 574acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 575acddfc2cSWeiyi Lu fufs_parents, 0xd0, 576acddfc2cSWeiyi Lu 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 577acddfc2cSWeiyi Lu /* CLK_CFG_10 */ 578acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 579acddfc2cSWeiyi Lu aud_1_parents, 0xe0, 580acddfc2cSWeiyi Lu 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 581acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 582acddfc2cSWeiyi Lu aud_2_parents, 0xe0, 583acddfc2cSWeiyi Lu 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 584acddfc2cSWeiyi Lu }; 585acddfc2cSWeiyi Lu 586acddfc2cSWeiyi Lu static const char * const apll_i2s0_parents[] = { 587acddfc2cSWeiyi Lu "aud_1_sel", 588acddfc2cSWeiyi Lu "aud_2_sel" 589acddfc2cSWeiyi Lu }; 590acddfc2cSWeiyi Lu 591acddfc2cSWeiyi Lu static const char * const apll_i2s1_parents[] = { 592acddfc2cSWeiyi Lu "aud_1_sel", 593acddfc2cSWeiyi Lu "aud_2_sel" 594acddfc2cSWeiyi Lu }; 595acddfc2cSWeiyi Lu 596acddfc2cSWeiyi Lu static const char * const apll_i2s2_parents[] = { 597acddfc2cSWeiyi Lu "aud_1_sel", 598acddfc2cSWeiyi Lu "aud_2_sel" 599acddfc2cSWeiyi Lu }; 600acddfc2cSWeiyi Lu 601acddfc2cSWeiyi Lu static const char * const apll_i2s3_parents[] = { 602acddfc2cSWeiyi Lu "aud_1_sel", 603acddfc2cSWeiyi Lu "aud_2_sel" 604acddfc2cSWeiyi Lu }; 605acddfc2cSWeiyi Lu 606acddfc2cSWeiyi Lu static const char * const apll_i2s4_parents[] = { 607acddfc2cSWeiyi Lu "aud_1_sel", 608acddfc2cSWeiyi Lu "aud_2_sel" 609acddfc2cSWeiyi Lu }; 610acddfc2cSWeiyi Lu 611acddfc2cSWeiyi Lu static const char * const apll_i2s5_parents[] = { 612acddfc2cSWeiyi Lu "aud_1_sel", 613acddfc2cSWeiyi Lu "aud_2_sel" 614acddfc2cSWeiyi Lu }; 615acddfc2cSWeiyi Lu 616acddfc2cSWeiyi Lu static struct mtk_composite top_aud_muxes[] = { 617acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 618acddfc2cSWeiyi Lu 0x320, 8, 1), 619acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 620acddfc2cSWeiyi Lu 0x320, 9, 1), 621acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 622acddfc2cSWeiyi Lu 0x320, 10, 1), 623acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 624acddfc2cSWeiyi Lu 0x320, 11, 1), 625acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 626acddfc2cSWeiyi Lu 0x320, 12, 1), 627acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 628acddfc2cSWeiyi Lu 0x328, 20, 1), 629acddfc2cSWeiyi Lu }; 630acddfc2cSWeiyi Lu 631acddfc2cSWeiyi Lu static const char * const mcu_mp0_parents[] = { 632acddfc2cSWeiyi Lu "clk26m", 633acddfc2cSWeiyi Lu "armpll_ll", 634acddfc2cSWeiyi Lu "armpll_div_pll1", 635acddfc2cSWeiyi Lu "armpll_div_pll2" 636acddfc2cSWeiyi Lu }; 637acddfc2cSWeiyi Lu 638acddfc2cSWeiyi Lu static const char * const mcu_mp2_parents[] = { 639acddfc2cSWeiyi Lu "clk26m", 640acddfc2cSWeiyi Lu "armpll_l", 641acddfc2cSWeiyi Lu "armpll_div_pll1", 642acddfc2cSWeiyi Lu "armpll_div_pll2" 643acddfc2cSWeiyi Lu }; 644acddfc2cSWeiyi Lu 645acddfc2cSWeiyi Lu static const char * const mcu_bus_parents[] = { 646acddfc2cSWeiyi Lu "clk26m", 647acddfc2cSWeiyi Lu "ccipll", 648acddfc2cSWeiyi Lu "armpll_div_pll1", 649acddfc2cSWeiyi Lu "armpll_div_pll2" 650acddfc2cSWeiyi Lu }; 651acddfc2cSWeiyi Lu 652acddfc2cSWeiyi Lu static struct mtk_composite mcu_muxes[] = { 653acddfc2cSWeiyi Lu /* mp0_pll_divider_cfg */ 654acddfc2cSWeiyi Lu MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 655acddfc2cSWeiyi Lu /* mp2_pll_divider_cfg */ 656acddfc2cSWeiyi Lu MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 657acddfc2cSWeiyi Lu /* bus_pll_divider_cfg */ 658acddfc2cSWeiyi Lu MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 659acddfc2cSWeiyi Lu }; 660acddfc2cSWeiyi Lu 661acddfc2cSWeiyi Lu static struct mtk_composite top_aud_divs[] = { 662acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 663acddfc2cSWeiyi Lu 0x320, 2, 0x324, 8, 0), 664acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 665acddfc2cSWeiyi Lu 0x320, 3, 0x324, 8, 8), 666acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 667acddfc2cSWeiyi Lu 0x320, 4, 0x324, 8, 16), 668acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 669acddfc2cSWeiyi Lu 0x320, 5, 0x324, 8, 24), 670acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 671acddfc2cSWeiyi Lu 0x320, 6, 0x328, 8, 0), 672acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 673acddfc2cSWeiyi Lu 0x320, 7, 0x328, 8, 8), 674acddfc2cSWeiyi Lu }; 675acddfc2cSWeiyi Lu 676acddfc2cSWeiyi Lu static const struct mtk_gate_regs top_cg_regs = { 677acddfc2cSWeiyi Lu .set_ofs = 0x104, 678acddfc2cSWeiyi Lu .clr_ofs = 0x104, 679acddfc2cSWeiyi Lu .sta_ofs = 0x104, 680acddfc2cSWeiyi Lu }; 681acddfc2cSWeiyi Lu 682acddfc2cSWeiyi Lu #define GATE_TOP(_id, _name, _parent, _shift) \ 683acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 684acddfc2cSWeiyi Lu &mtk_clk_gate_ops_no_setclr_inv) 685acddfc2cSWeiyi Lu 686acddfc2cSWeiyi Lu static const struct mtk_gate top_clks[] = { 687acddfc2cSWeiyi Lu /* TOP */ 688acddfc2cSWeiyi Lu GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 689acddfc2cSWeiyi Lu GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 690acddfc2cSWeiyi Lu }; 691acddfc2cSWeiyi Lu 692acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra0_cg_regs = { 693acddfc2cSWeiyi Lu .set_ofs = 0x80, 694acddfc2cSWeiyi Lu .clr_ofs = 0x84, 695acddfc2cSWeiyi Lu .sta_ofs = 0x90, 696acddfc2cSWeiyi Lu }; 697acddfc2cSWeiyi Lu 698acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra1_cg_regs = { 699acddfc2cSWeiyi Lu .set_ofs = 0x88, 700acddfc2cSWeiyi Lu .clr_ofs = 0x8c, 701acddfc2cSWeiyi Lu .sta_ofs = 0x94, 702acddfc2cSWeiyi Lu }; 703acddfc2cSWeiyi Lu 704acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra2_cg_regs = { 705acddfc2cSWeiyi Lu .set_ofs = 0xa4, 706acddfc2cSWeiyi Lu .clr_ofs = 0xa8, 707acddfc2cSWeiyi Lu .sta_ofs = 0xac, 708acddfc2cSWeiyi Lu }; 709acddfc2cSWeiyi Lu 710acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra3_cg_regs = { 711acddfc2cSWeiyi Lu .set_ofs = 0xc0, 712acddfc2cSWeiyi Lu .clr_ofs = 0xc4, 713acddfc2cSWeiyi Lu .sta_ofs = 0xc8, 714acddfc2cSWeiyi Lu }; 715acddfc2cSWeiyi Lu 716acddfc2cSWeiyi Lu #define GATE_INFRA0(_id, _name, _parent, _shift) \ 717acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 718acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 719acddfc2cSWeiyi Lu 720acddfc2cSWeiyi Lu #define GATE_INFRA1(_id, _name, _parent, _shift) \ 721acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 722acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 723acddfc2cSWeiyi Lu 724acddfc2cSWeiyi Lu #define GATE_INFRA2(_id, _name, _parent, _shift) \ 725acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 726acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 727acddfc2cSWeiyi Lu 728acddfc2cSWeiyi Lu #define GATE_INFRA3(_id, _name, _parent, _shift) \ 729acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 730acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 731acddfc2cSWeiyi Lu 732acddfc2cSWeiyi Lu static const struct mtk_gate infra_clks[] = { 733acddfc2cSWeiyi Lu /* INFRA0 */ 734acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 735acddfc2cSWeiyi Lu "axi_sel", 0), 736acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 737acddfc2cSWeiyi Lu "axi_sel", 1), 738acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 739acddfc2cSWeiyi Lu "axi_sel", 2), 740acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", 741acddfc2cSWeiyi Lu "axi_sel", 3), 742acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", 743acddfc2cSWeiyi Lu "scp_sel", 4), 744acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", 745acddfc2cSWeiyi Lu "f_f26m_ck", 5), 746acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", 747acddfc2cSWeiyi Lu "axi_sel", 6), 748acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", 749acddfc2cSWeiyi Lu "axi_sel", 8), 750acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", 751acddfc2cSWeiyi Lu "axi_sel", 9), 752acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", 753acddfc2cSWeiyi Lu "axi_sel", 10), 754acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", 755acddfc2cSWeiyi Lu "i2c_sel", 11), 756acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", 757acddfc2cSWeiyi Lu "i2c_sel", 12), 758acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", 759acddfc2cSWeiyi Lu "i2c_sel", 13), 760acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", 761acddfc2cSWeiyi Lu "i2c_sel", 14), 762acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", 763acddfc2cSWeiyi Lu "axi_sel", 15), 764acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", 765acddfc2cSWeiyi Lu "i2c_sel", 16), 766acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", 767acddfc2cSWeiyi Lu "i2c_sel", 17), 768acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", 769acddfc2cSWeiyi Lu "i2c_sel", 18), 770acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", 771acddfc2cSWeiyi Lu "i2c_sel", 19), 772acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 773acddfc2cSWeiyi Lu "i2c_sel", 21), 774acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 775acddfc2cSWeiyi Lu "uart_sel", 22), 776acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 777acddfc2cSWeiyi Lu "uart_sel", 23), 778acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", 779acddfc2cSWeiyi Lu "uart_sel", 24), 780acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", 781acddfc2cSWeiyi Lu "uart_sel", 25), 782acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", 783acddfc2cSWeiyi Lu "axi_sel", 27), 784acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", 785acddfc2cSWeiyi Lu "axi_sel", 28), 786acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", 787acddfc2cSWeiyi Lu "axi_sel", 31), 788acddfc2cSWeiyi Lu /* INFRA1 */ 789acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", 790acddfc2cSWeiyi Lu "spi_sel", 1), 791acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", 792acddfc2cSWeiyi Lu "msdc50_hclk_sel", 2), 793acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", 794acddfc2cSWeiyi Lu "axi_sel", 4), 795acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", 796acddfc2cSWeiyi Lu "axi_sel", 5), 797acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", 798acddfc2cSWeiyi Lu "msdc50_0_sel", 6), 799acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", 800acddfc2cSWeiyi Lu "f_f26m_ck", 7), 801acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", 802acddfc2cSWeiyi Lu "axi_sel", 8), 803acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", 804acddfc2cSWeiyi Lu "axi_sel", 9), 805acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", 806acddfc2cSWeiyi Lu "f_f26m_ck", 10), 807acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", 808acddfc2cSWeiyi Lu "axi_sel", 11), 809acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", 810acddfc2cSWeiyi Lu "axi_sel", 12), 811acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", 812acddfc2cSWeiyi Lu "axi_sel", 13), 813acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", 814acddfc2cSWeiyi Lu "f_f26m_ck", 14), 815acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", 816acddfc2cSWeiyi Lu "msdc30_1_sel", 16), 817acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", 818acddfc2cSWeiyi Lu "msdc30_2_sel", 17), 819acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", 820acddfc2cSWeiyi Lu "axi_sel", 18), 821acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", 822acddfc2cSWeiyi Lu "axi_sel", 19), 823acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", 824acddfc2cSWeiyi Lu "axi_sel", 20), 825acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", 826acddfc2cSWeiyi Lu "axi_sel", 23), 827acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", 828acddfc2cSWeiyi Lu "axi_sel", 24), 829acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", 830acddfc2cSWeiyi Lu "axi_sel", 25), 831acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", 832acddfc2cSWeiyi Lu "axi_sel", 26), 833acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", 834acddfc2cSWeiyi Lu "dxcc_sel", 27), 835acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", 836acddfc2cSWeiyi Lu "dxcc_sel", 28), 837acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", 838acddfc2cSWeiyi Lu "axi_sel", 30), 839acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 840acddfc2cSWeiyi Lu "f_f26m_ck", 31), 841acddfc2cSWeiyi Lu /* INFRA2 */ 842acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", 843acddfc2cSWeiyi Lu "f_f26m_ck", 0), 844acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_USB, "infra_usb", 845acddfc2cSWeiyi Lu "usb_top_sel", 1), 846acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", 847acddfc2cSWeiyi Lu "axi_sel", 2), 848acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", 849acddfc2cSWeiyi Lu "axi_sel", 3), 850acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", 851acddfc2cSWeiyi Lu "f_f26m_ck", 4), 852acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", 853acddfc2cSWeiyi Lu "spi_sel", 6), 854acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", 855acddfc2cSWeiyi Lu "i2c_sel", 7), 856acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", 857acddfc2cSWeiyi Lu "f_f26m_ck", 8), 858acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", 859acddfc2cSWeiyi Lu "spi_sel", 9), 860acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", 861acddfc2cSWeiyi Lu "spi_sel", 10), 862acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", 863acddfc2cSWeiyi Lu "ssusb_top_xhci_sel", 11), 864acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", 865acddfc2cSWeiyi Lu "fufs_sel", 12), 866acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", 867acddfc2cSWeiyi Lu "fufs_sel", 13), 868acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", 869acddfc2cSWeiyi Lu "axi_sel", 14), 870acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", 871acddfc2cSWeiyi Lu "axi_sel", 16), 872acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", 873acddfc2cSWeiyi Lu "i2c_sel", 18), 874acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", 875acddfc2cSWeiyi Lu "i2c_sel", 19), 876acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", 877acddfc2cSWeiyi Lu "i2c_sel", 20), 878acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", 879acddfc2cSWeiyi Lu "i2c_sel", 21), 880acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", 881acddfc2cSWeiyi Lu "i2c_sel", 22), 882acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", 883acddfc2cSWeiyi Lu "i2c_sel", 23), 884acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", 885acddfc2cSWeiyi Lu "i2c_sel", 24), 886acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", 887acddfc2cSWeiyi Lu "spi_sel", 25), 888acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", 889acddfc2cSWeiyi Lu "spi_sel", 26), 890acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", 891acddfc2cSWeiyi Lu "axi_sel", 27), 892acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", 893acddfc2cSWeiyi Lu "fufs_sel", 28), 894acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", 895acddfc2cSWeiyi Lu "faes_ufsfde_sel", 29), 896acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", 897acddfc2cSWeiyi Lu "fufs_sel", 30), 898acddfc2cSWeiyi Lu /* INFRA3 */ 899acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", 900acddfc2cSWeiyi Lu "msdc50_0_sel", 0), 901acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", 902acddfc2cSWeiyi Lu "msdc50_0_sel", 1), 903acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", 904acddfc2cSWeiyi Lu "msdc50_0_sel", 2), 905acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", 906acddfc2cSWeiyi Lu "axi_sel", 5), 907acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", 908acddfc2cSWeiyi Lu "i2c_sel", 6), 909acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", 910acddfc2cSWeiyi Lu "msdc50_hclk_sel", 7), 911acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", 912acddfc2cSWeiyi Lu "msdc50_hclk_sel", 8), 913acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", 914acddfc2cSWeiyi Lu "axi_sel", 16), 915acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", 916acddfc2cSWeiyi Lu "axi_sel", 17), 917acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", 918acddfc2cSWeiyi Lu "axi_sel", 18), 919acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", 920acddfc2cSWeiyi Lu "axi_sel", 19), 921acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", 922acddfc2cSWeiyi Lu "f_f26m_ck", 20), 923acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", 924acddfc2cSWeiyi Lu "axi_sel", 21), 925acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", 926acddfc2cSWeiyi Lu "i2c_sel", 22), 927acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", 928acddfc2cSWeiyi Lu "i2c_sel", 23), 929acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", 930acddfc2cSWeiyi Lu "msdc50_0_sel", 24), 931acddfc2cSWeiyi Lu }; 932acddfc2cSWeiyi Lu 933f9e55ac2SChunfeng Yun static const struct mtk_gate_regs peri_cg_regs = { 934f9e55ac2SChunfeng Yun .set_ofs = 0x20c, 935f9e55ac2SChunfeng Yun .clr_ofs = 0x20c, 936f9e55ac2SChunfeng Yun .sta_ofs = 0x20c, 937f9e55ac2SChunfeng Yun }; 938f9e55ac2SChunfeng Yun 939f9e55ac2SChunfeng Yun #define GATE_PERI(_id, _name, _parent, _shift) \ 940f9e55ac2SChunfeng Yun GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ 941f9e55ac2SChunfeng Yun &mtk_clk_gate_ops_no_setclr_inv) 942f9e55ac2SChunfeng Yun 943f9e55ac2SChunfeng Yun static const struct mtk_gate peri_clks[] = { 944f9e55ac2SChunfeng Yun GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), 945f9e55ac2SChunfeng Yun }; 946f9e55ac2SChunfeng Yun 947acddfc2cSWeiyi Lu static const struct mtk_gate_regs apmixed_cg_regs = { 948acddfc2cSWeiyi Lu .set_ofs = 0x20, 949acddfc2cSWeiyi Lu .clr_ofs = 0x20, 950acddfc2cSWeiyi Lu .sta_ofs = 0x20, 951acddfc2cSWeiyi Lu }; 952acddfc2cSWeiyi Lu 953acddfc2cSWeiyi Lu #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ 954acddfc2cSWeiyi Lu GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ 955acddfc2cSWeiyi Lu _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) 956acddfc2cSWeiyi Lu 957acddfc2cSWeiyi Lu #define GATE_APMIXED(_id, _name, _parent, _shift) \ 958acddfc2cSWeiyi Lu GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) 959acddfc2cSWeiyi Lu 960acddfc2cSWeiyi Lu /* 961acddfc2cSWeiyi Lu * CRITICAL CLOCK: 962acddfc2cSWeiyi Lu * apmixed_appll26m is the toppest clock gate of all PLLs. 963acddfc2cSWeiyi Lu */ 964acddfc2cSWeiyi Lu static const struct mtk_gate apmixed_clks[] = { 965acddfc2cSWeiyi Lu /* AUDIO0 */ 966acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", 967acddfc2cSWeiyi Lu "f_f26m_ck", 4), 968acddfc2cSWeiyi Lu GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", 969acddfc2cSWeiyi Lu "f_f26m_ck", 5, CLK_IS_CRITICAL), 970acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", 971acddfc2cSWeiyi Lu "f_f26m_ck", 6), 972acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", 973acddfc2cSWeiyi Lu "f_f26m_ck", 7), 974acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", 975acddfc2cSWeiyi Lu "f_f26m_ck", 8), 976acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", 977acddfc2cSWeiyi Lu "f_f26m_ck", 9), 978acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", 979acddfc2cSWeiyi Lu "f_f26m_ck", 11), 980acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", 981acddfc2cSWeiyi Lu "f_f26m_ck", 13), 982acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 983acddfc2cSWeiyi Lu "f_f26m_ck", 14), 984acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", 985acddfc2cSWeiyi Lu "f_f26m_ck", 16), 986acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", 987acddfc2cSWeiyi Lu "f_f26m_ck", 17), 988acddfc2cSWeiyi Lu }; 989acddfc2cSWeiyi Lu 990acddfc2cSWeiyi Lu #define MT8183_PLL_FMAX (3800UL * MHZ) 991acddfc2cSWeiyi Lu #define MT8183_PLL_FMIN (1500UL * MHZ) 992acddfc2cSWeiyi Lu 993acddfc2cSWeiyi Lu #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 994acddfc2cSWeiyi Lu _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 995acddfc2cSWeiyi Lu _pd_shift, _tuner_reg, _tuner_en_reg, \ 996acddfc2cSWeiyi Lu _tuner_en_bit, _pcw_reg, _pcw_shift, \ 997acddfc2cSWeiyi Lu _pcw_chg_reg, _div_table) { \ 998acddfc2cSWeiyi Lu .id = _id, \ 999acddfc2cSWeiyi Lu .name = _name, \ 1000acddfc2cSWeiyi Lu .reg = _reg, \ 1001acddfc2cSWeiyi Lu .pwr_reg = _pwr_reg, \ 1002acddfc2cSWeiyi Lu .en_mask = _en_mask, \ 1003acddfc2cSWeiyi Lu .flags = _flags, \ 1004acddfc2cSWeiyi Lu .rst_bar_mask = _rst_bar_mask, \ 1005acddfc2cSWeiyi Lu .fmax = MT8183_PLL_FMAX, \ 1006acddfc2cSWeiyi Lu .fmin = MT8183_PLL_FMIN, \ 1007acddfc2cSWeiyi Lu .pcwbits = _pcwbits, \ 1008acddfc2cSWeiyi Lu .pcwibits = _pcwibits, \ 1009acddfc2cSWeiyi Lu .pd_reg = _pd_reg, \ 1010acddfc2cSWeiyi Lu .pd_shift = _pd_shift, \ 1011acddfc2cSWeiyi Lu .tuner_reg = _tuner_reg, \ 1012acddfc2cSWeiyi Lu .tuner_en_reg = _tuner_en_reg, \ 1013acddfc2cSWeiyi Lu .tuner_en_bit = _tuner_en_bit, \ 1014acddfc2cSWeiyi Lu .pcw_reg = _pcw_reg, \ 1015acddfc2cSWeiyi Lu .pcw_shift = _pcw_shift, \ 1016acddfc2cSWeiyi Lu .pcw_chg_reg = _pcw_chg_reg, \ 1017acddfc2cSWeiyi Lu .div_table = _div_table, \ 1018acddfc2cSWeiyi Lu } 1019acddfc2cSWeiyi Lu 1020acddfc2cSWeiyi Lu #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1021acddfc2cSWeiyi Lu _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1022acddfc2cSWeiyi Lu _pd_shift, _tuner_reg, _tuner_en_reg, \ 1023acddfc2cSWeiyi Lu _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1024acddfc2cSWeiyi Lu _pcw_chg_reg) \ 1025acddfc2cSWeiyi Lu PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1026acddfc2cSWeiyi Lu _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1027acddfc2cSWeiyi Lu _pd_shift, _tuner_reg, _tuner_en_reg, \ 1028acddfc2cSWeiyi Lu _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1029acddfc2cSWeiyi Lu _pcw_chg_reg, NULL) 1030acddfc2cSWeiyi Lu 1031acddfc2cSWeiyi Lu static const struct mtk_pll_div_table armpll_div_table[] = { 1032acddfc2cSWeiyi Lu { .div = 0, .freq = MT8183_PLL_FMAX }, 1033acddfc2cSWeiyi Lu { .div = 1, .freq = 1500 * MHZ }, 1034acddfc2cSWeiyi Lu { .div = 2, .freq = 750 * MHZ }, 1035acddfc2cSWeiyi Lu { .div = 3, .freq = 375 * MHZ }, 1036acddfc2cSWeiyi Lu { .div = 4, .freq = 187500000 }, 1037acddfc2cSWeiyi Lu { } /* sentinel */ 1038acddfc2cSWeiyi Lu }; 1039acddfc2cSWeiyi Lu 1040acddfc2cSWeiyi Lu static const struct mtk_pll_div_table mfgpll_div_table[] = { 1041acddfc2cSWeiyi Lu { .div = 0, .freq = MT8183_PLL_FMAX }, 1042acddfc2cSWeiyi Lu { .div = 1, .freq = 1600 * MHZ }, 1043acddfc2cSWeiyi Lu { .div = 2, .freq = 800 * MHZ }, 1044acddfc2cSWeiyi Lu { .div = 3, .freq = 400 * MHZ }, 1045acddfc2cSWeiyi Lu { .div = 4, .freq = 200 * MHZ }, 1046acddfc2cSWeiyi Lu { } /* sentinel */ 1047acddfc2cSWeiyi Lu }; 1048acddfc2cSWeiyi Lu 1049acddfc2cSWeiyi Lu static const struct mtk_pll_data plls[] = { 1050e1fd35f5SChun-Jie Chen PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0, 1051acddfc2cSWeiyi Lu HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, 1052acddfc2cSWeiyi Lu 0x0204, 0, 0, armpll_div_table), 1053e1fd35f5SChun-Jie Chen PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0, 1054acddfc2cSWeiyi Lu HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, 1055acddfc2cSWeiyi Lu 0x0214, 0, 0, armpll_div_table), 1056e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0, 1057acddfc2cSWeiyi Lu HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, 1058acddfc2cSWeiyi Lu 0x0294, 0, 0), 1059e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0, 1060acddfc2cSWeiyi Lu HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, 1061acddfc2cSWeiyi Lu 0x0224, 0, 0), 1062e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0, 1063acddfc2cSWeiyi Lu HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, 1064acddfc2cSWeiyi Lu 0x0234, 0, 0), 1065e1fd35f5SChun-Jie Chen PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0, 1066acddfc2cSWeiyi Lu 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, 1067acddfc2cSWeiyi Lu mfgpll_div_table), 1068e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0, 1069acddfc2cSWeiyi Lu 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), 1070e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0, 1071acddfc2cSWeiyi Lu 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), 1072e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0, 1073acddfc2cSWeiyi Lu HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, 1074acddfc2cSWeiyi Lu 0x0274, 0, 0), 1075e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0, 1076acddfc2cSWeiyi Lu 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), 1077e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0, 1078acddfc2cSWeiyi Lu 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), 1079acddfc2cSWeiyi Lu }; 1080acddfc2cSWeiyi Lu 1081723e3671SRex-BC Chen static u16 infra_rst_ofs[] = { 1082723e3671SRex-BC Chen INFRA_RST0_SET_OFFSET, 1083723e3671SRex-BC Chen INFRA_RST1_SET_OFFSET, 1084723e3671SRex-BC Chen INFRA_RST2_SET_OFFSET, 1085723e3671SRex-BC Chen INFRA_RST3_SET_OFFSET, 1086723e3671SRex-BC Chen }; 1087723e3671SRex-BC Chen 10882d2a2900SRex-BC Chen static const struct mtk_clk_rst_desc clk_rst_desc = { 10892d2a2900SRex-BC Chen .version = MTK_RST_SET_CLR, 1090723e3671SRex-BC Chen .rst_bank_ofs = infra_rst_ofs, 1091723e3671SRex-BC Chen .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), 10922d2a2900SRex-BC Chen }; 10932d2a2900SRex-BC Chen 1094acddfc2cSWeiyi Lu static int clk_mt8183_apmixed_probe(struct platform_device *pdev) 1095acddfc2cSWeiyi Lu { 1096609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data; 1097acddfc2cSWeiyi Lu struct device_node *node = pdev->dev.of_node; 1098acddfc2cSWeiyi Lu 1099acddfc2cSWeiyi Lu clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1100acddfc2cSWeiyi Lu 1101acddfc2cSWeiyi Lu mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1102acddfc2cSWeiyi Lu 110320498d52SAngeloGioacchino Del Regno mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, 110420498d52SAngeloGioacchino Del Regno ARRAY_SIZE(apmixed_clks), clk_data); 1105acddfc2cSWeiyi Lu 1106609cc5e1SChen-Yu Tsai return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1107acddfc2cSWeiyi Lu } 1108acddfc2cSWeiyi Lu 1109609cc5e1SChen-Yu Tsai static struct clk_hw_onecell_data *top_clk_data; 1110c93d059aSWeiyi Lu 1111c93d059aSWeiyi Lu static void clk_mt8183_top_init_early(struct device_node *node) 1112c93d059aSWeiyi Lu { 1113c93d059aSWeiyi Lu int i; 1114c93d059aSWeiyi Lu 1115c93d059aSWeiyi Lu top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1116c93d059aSWeiyi Lu 1117c93d059aSWeiyi Lu for (i = 0; i < CLK_TOP_NR_CLK; i++) 1118609cc5e1SChen-Yu Tsai top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 1119c93d059aSWeiyi Lu 1120c93d059aSWeiyi Lu mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1121c93d059aSWeiyi Lu top_clk_data); 1122c93d059aSWeiyi Lu 1123609cc5e1SChen-Yu Tsai of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); 1124c93d059aSWeiyi Lu } 1125c93d059aSWeiyi Lu 1126c93d059aSWeiyi Lu CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", 1127c93d059aSWeiyi Lu clk_mt8183_top_init_early); 1128c93d059aSWeiyi Lu 1129ae333e63SChen-Yu Tsai /* Register mux notifier for MFG mux */ 1130ae333e63SChen-Yu Tsai static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) 1131ae333e63SChen-Yu Tsai { 1132ae333e63SChen-Yu Tsai struct mtk_mux_nb *mfg_mux_nb; 1133ae333e63SChen-Yu Tsai int i; 1134ae333e63SChen-Yu Tsai 1135ae333e63SChen-Yu Tsai mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); 1136ae333e63SChen-Yu Tsai if (!mfg_mux_nb) 1137ae333e63SChen-Yu Tsai return -ENOMEM; 1138ae333e63SChen-Yu Tsai 1139ae333e63SChen-Yu Tsai for (i = 0; i < ARRAY_SIZE(top_muxes); i++) 1140ae333e63SChen-Yu Tsai if (top_muxes[i].id == CLK_TOP_MUX_MFG) 1141ae333e63SChen-Yu Tsai break; 1142ae333e63SChen-Yu Tsai if (i == ARRAY_SIZE(top_muxes)) 1143ae333e63SChen-Yu Tsai return -EINVAL; 1144ae333e63SChen-Yu Tsai 1145ae333e63SChen-Yu Tsai mfg_mux_nb->ops = top_muxes[i].ops; 1146ae333e63SChen-Yu Tsai mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */ 1147ae333e63SChen-Yu Tsai 1148ae333e63SChen-Yu Tsai return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); 1149ae333e63SChen-Yu Tsai } 1150ae333e63SChen-Yu Tsai 1151acddfc2cSWeiyi Lu static int clk_mt8183_top_probe(struct platform_device *pdev) 1152acddfc2cSWeiyi Lu { 1153acddfc2cSWeiyi Lu void __iomem *base; 1154acddfc2cSWeiyi Lu struct device_node *node = pdev->dev.of_node; 1155ae333e63SChen-Yu Tsai int ret; 1156acddfc2cSWeiyi Lu 1157067de0a6SYueHaibing base = devm_platform_ioremap_resource(pdev, 0); 1158acddfc2cSWeiyi Lu if (IS_ERR(base)) 1159acddfc2cSWeiyi Lu return PTR_ERR(base); 1160acddfc2cSWeiyi Lu 1161acddfc2cSWeiyi Lu mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 1162c93d059aSWeiyi Lu top_clk_data); 1163acddfc2cSWeiyi Lu 1164c93d059aSWeiyi Lu mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1165c93d059aSWeiyi Lu top_clk_data); 1166c93d059aSWeiyi Lu 1167c93d059aSWeiyi Lu mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); 1168acddfc2cSWeiyi Lu 1169*d3d6bd5eSAngeloGioacchino Del Regno mtk_clk_register_muxes(&pdev->dev, top_muxes, 1170*d3d6bd5eSAngeloGioacchino Del Regno ARRAY_SIZE(top_muxes), node, 1171*d3d6bd5eSAngeloGioacchino Del Regno &mt8183_clk_lock, top_clk_data); 1172acddfc2cSWeiyi Lu 117301a6c1abSAngeloGioacchino Del Regno mtk_clk_register_composites(&pdev->dev, top_aud_muxes, 117401a6c1abSAngeloGioacchino Del Regno ARRAY_SIZE(top_aud_muxes), base, 117501a6c1abSAngeloGioacchino Del Regno &mt8183_clk_lock, top_clk_data); 1176acddfc2cSWeiyi Lu 117701a6c1abSAngeloGioacchino Del Regno mtk_clk_register_composites(&pdev->dev, top_aud_divs, 117801a6c1abSAngeloGioacchino Del Regno ARRAY_SIZE(top_aud_divs), base, 117901a6c1abSAngeloGioacchino Del Regno &mt8183_clk_lock, top_clk_data); 1180acddfc2cSWeiyi Lu 118120498d52SAngeloGioacchino Del Regno mtk_clk_register_gates(&pdev->dev, node, top_clks, 118220498d52SAngeloGioacchino Del Regno ARRAY_SIZE(top_clks), top_clk_data); 1183acddfc2cSWeiyi Lu 1184ae333e63SChen-Yu Tsai ret = clk_mt8183_reg_mfg_mux_notifier(&pdev->dev, 1185ae333e63SChen-Yu Tsai top_clk_data->hws[CLK_TOP_MUX_MFG]->clk); 1186ae333e63SChen-Yu Tsai if (ret) 1187ae333e63SChen-Yu Tsai return ret; 1188ae333e63SChen-Yu Tsai 1189609cc5e1SChen-Yu Tsai return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 1190609cc5e1SChen-Yu Tsai top_clk_data); 1191acddfc2cSWeiyi Lu } 1192acddfc2cSWeiyi Lu 1193acddfc2cSWeiyi Lu static int clk_mt8183_infra_probe(struct platform_device *pdev) 1194acddfc2cSWeiyi Lu { 1195609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data; 1196acddfc2cSWeiyi Lu struct device_node *node = pdev->dev.of_node; 119764ebb57aSyong.liang int r; 1198acddfc2cSWeiyi Lu 1199acddfc2cSWeiyi Lu clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1200acddfc2cSWeiyi Lu 120120498d52SAngeloGioacchino Del Regno mtk_clk_register_gates(&pdev->dev, node, infra_clks, 120220498d52SAngeloGioacchino Del Regno ARRAY_SIZE(infra_clks), clk_data); 1203acddfc2cSWeiyi Lu 1204609cc5e1SChen-Yu Tsai r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 120564ebb57aSyong.liang if (r) { 120664ebb57aSyong.liang dev_err(&pdev->dev, 120764ebb57aSyong.liang "%s(): could not register clock provider: %d\n", 120864ebb57aSyong.liang __func__, r); 120964ebb57aSyong.liang return r; 121064ebb57aSyong.liang } 121164ebb57aSyong.liang 1212761bc640SRex-BC Chen mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); 121364ebb57aSyong.liang 121464ebb57aSyong.liang return r; 1215acddfc2cSWeiyi Lu } 1216acddfc2cSWeiyi Lu 1217f9e55ac2SChunfeng Yun static int clk_mt8183_peri_probe(struct platform_device *pdev) 1218f9e55ac2SChunfeng Yun { 1219609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data; 1220f9e55ac2SChunfeng Yun struct device_node *node = pdev->dev.of_node; 1221f9e55ac2SChunfeng Yun 1222f9e55ac2SChunfeng Yun clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 1223f9e55ac2SChunfeng Yun 122420498d52SAngeloGioacchino Del Regno mtk_clk_register_gates(&pdev->dev, node, peri_clks, 122520498d52SAngeloGioacchino Del Regno ARRAY_SIZE(peri_clks), clk_data); 1226f9e55ac2SChunfeng Yun 1227609cc5e1SChen-Yu Tsai return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1228acddfc2cSWeiyi Lu } 1229acddfc2cSWeiyi Lu 1230acddfc2cSWeiyi Lu static int clk_mt8183_mcu_probe(struct platform_device *pdev) 1231acddfc2cSWeiyi Lu { 1232609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data; 1233acddfc2cSWeiyi Lu struct device_node *node = pdev->dev.of_node; 1234acddfc2cSWeiyi Lu void __iomem *base; 1235acddfc2cSWeiyi Lu 1236067de0a6SYueHaibing base = devm_platform_ioremap_resource(pdev, 0); 1237acddfc2cSWeiyi Lu if (IS_ERR(base)) 1238acddfc2cSWeiyi Lu return PTR_ERR(base); 1239acddfc2cSWeiyi Lu 1240acddfc2cSWeiyi Lu clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); 1241acddfc2cSWeiyi Lu 124201a6c1abSAngeloGioacchino Del Regno mtk_clk_register_composites(&pdev->dev, mcu_muxes, 124301a6c1abSAngeloGioacchino Del Regno ARRAY_SIZE(mcu_muxes), base, 1244acddfc2cSWeiyi Lu &mt8183_clk_lock, clk_data); 1245acddfc2cSWeiyi Lu 1246609cc5e1SChen-Yu Tsai return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1247acddfc2cSWeiyi Lu } 1248acddfc2cSWeiyi Lu 1249acddfc2cSWeiyi Lu static const struct of_device_id of_match_clk_mt8183[] = { 1250acddfc2cSWeiyi Lu { 1251acddfc2cSWeiyi Lu .compatible = "mediatek,mt8183-apmixedsys", 1252acddfc2cSWeiyi Lu .data = clk_mt8183_apmixed_probe, 1253acddfc2cSWeiyi Lu }, { 1254acddfc2cSWeiyi Lu .compatible = "mediatek,mt8183-topckgen", 1255acddfc2cSWeiyi Lu .data = clk_mt8183_top_probe, 1256acddfc2cSWeiyi Lu }, { 1257acddfc2cSWeiyi Lu .compatible = "mediatek,mt8183-infracfg", 1258acddfc2cSWeiyi Lu .data = clk_mt8183_infra_probe, 1259acddfc2cSWeiyi Lu }, { 1260f9e55ac2SChunfeng Yun .compatible = "mediatek,mt8183-pericfg", 1261f9e55ac2SChunfeng Yun .data = clk_mt8183_peri_probe, 1262f9e55ac2SChunfeng Yun }, { 1263acddfc2cSWeiyi Lu .compatible = "mediatek,mt8183-mcucfg", 1264acddfc2cSWeiyi Lu .data = clk_mt8183_mcu_probe, 1265acddfc2cSWeiyi Lu }, { 1266acddfc2cSWeiyi Lu /* sentinel */ 1267acddfc2cSWeiyi Lu } 1268acddfc2cSWeiyi Lu }; 1269acddfc2cSWeiyi Lu 1270acddfc2cSWeiyi Lu static int clk_mt8183_probe(struct platform_device *pdev) 1271acddfc2cSWeiyi Lu { 1272acddfc2cSWeiyi Lu int (*clk_probe)(struct platform_device *pdev); 1273acddfc2cSWeiyi Lu int r; 1274acddfc2cSWeiyi Lu 1275acddfc2cSWeiyi Lu clk_probe = of_device_get_match_data(&pdev->dev); 1276acddfc2cSWeiyi Lu if (!clk_probe) 1277acddfc2cSWeiyi Lu return -EINVAL; 1278acddfc2cSWeiyi Lu 1279acddfc2cSWeiyi Lu r = clk_probe(pdev); 1280acddfc2cSWeiyi Lu if (r) 1281acddfc2cSWeiyi Lu dev_err(&pdev->dev, 1282acddfc2cSWeiyi Lu "could not register clock provider: %s: %d\n", 1283acddfc2cSWeiyi Lu pdev->name, r); 1284acddfc2cSWeiyi Lu 1285acddfc2cSWeiyi Lu return r; 1286acddfc2cSWeiyi Lu } 1287acddfc2cSWeiyi Lu 1288acddfc2cSWeiyi Lu static struct platform_driver clk_mt8183_drv = { 1289acddfc2cSWeiyi Lu .probe = clk_mt8183_probe, 1290acddfc2cSWeiyi Lu .driver = { 1291acddfc2cSWeiyi Lu .name = "clk-mt8183", 1292acddfc2cSWeiyi Lu .of_match_table = of_match_clk_mt8183, 1293acddfc2cSWeiyi Lu }, 1294acddfc2cSWeiyi Lu }; 1295acddfc2cSWeiyi Lu 1296acddfc2cSWeiyi Lu static int __init clk_mt8183_init(void) 1297acddfc2cSWeiyi Lu { 1298acddfc2cSWeiyi Lu return platform_driver_register(&clk_mt8183_drv); 1299acddfc2cSWeiyi Lu } 1300acddfc2cSWeiyi Lu 1301acddfc2cSWeiyi Lu arch_initcall(clk_mt8183_init); 1302