1acddfc2cSWeiyi Lu // SPDX-License-Identifier: GPL-2.0
2acddfc2cSWeiyi Lu //
3acddfc2cSWeiyi Lu // Copyright (c) 2018 MediaTek Inc.
4acddfc2cSWeiyi Lu // Author: Weiyi Lu <weiyi.lu@mediatek.com>
5acddfc2cSWeiyi Lu 
6acddfc2cSWeiyi Lu #include <linux/delay.h>
7acddfc2cSWeiyi Lu #include <linux/mfd/syscon.h>
8acddfc2cSWeiyi Lu #include <linux/of.h>
9acddfc2cSWeiyi Lu #include <linux/of_address.h>
10acddfc2cSWeiyi Lu #include <linux/of_device.h>
11acddfc2cSWeiyi Lu #include <linux/platform_device.h>
12acddfc2cSWeiyi Lu #include <linux/slab.h>
13acddfc2cSWeiyi Lu 
1439691fb6SChen-Yu Tsai #include "clk-gate.h"
15acddfc2cSWeiyi Lu #include "clk-mtk.h"
16acddfc2cSWeiyi Lu #include "clk-mux.h"
17acddfc2cSWeiyi Lu 
18acddfc2cSWeiyi Lu #include <dt-bindings/clock/mt8183-clk.h>
19acddfc2cSWeiyi Lu 
20acddfc2cSWeiyi Lu static DEFINE_SPINLOCK(mt8183_clk_lock);
21acddfc2cSWeiyi Lu 
22acddfc2cSWeiyi Lu static const struct mtk_fixed_clk top_fixed_clks[] = {
23acddfc2cSWeiyi Lu 	FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
24acddfc2cSWeiyi Lu 	FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000),
25acddfc2cSWeiyi Lu 	FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
26acddfc2cSWeiyi Lu };
27acddfc2cSWeiyi Lu 
28c93d059aSWeiyi Lu static const struct mtk_fixed_factor top_early_divs[] = {
29c93d059aSWeiyi Lu 	FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
30c93d059aSWeiyi Lu };
31c93d059aSWeiyi Lu 
32acddfc2cSWeiyi Lu static const struct mtk_fixed_factor top_divs[] = {
3323037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
34c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
35c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
36c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
37c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
38c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
39c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
40c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
41c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
42c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
43c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
44c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0),
45c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0),
46c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 4, 0),
47c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0),
48c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 2, 0),
49c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 4, 0),
50c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1, 0),
51c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2, 0),
52c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0),
53c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0),
54c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8, 0),
55c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
56c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0),
57c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0),
58c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0),
59c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
60c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
61c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
62c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
63c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
64c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 1, 0),
65c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 2, 0),
66c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 4, 0),
67c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 8, 0),
68c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 16, 0),
69c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 32, 0),
7023037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
7123037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
7223037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
7323037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
7423037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
7523037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
7623037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
7723037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
7823037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
7923037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
8023037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
8123037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
8223037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
8323037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
8423037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
8523037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
8623037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
8723037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
8823037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
8923037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
9023037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
9123037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
9223037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
9323037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
9423037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
9523037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
9623037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
9723037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
9823037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
9923037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
10023037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
10123037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
10223037ab6SAngeloGioacchino Del Regno 	FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
103c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0),
104c01d64caSAngeloGioacchino Del Regno 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16, 0),
105acddfc2cSWeiyi Lu };
106acddfc2cSWeiyi Lu 
107acddfc2cSWeiyi Lu static const char * const axi_parents[] = {
108acddfc2cSWeiyi Lu 	"clk26m",
109acddfc2cSWeiyi Lu 	"syspll_d2_d4",
110acddfc2cSWeiyi Lu 	"syspll_d7",
111acddfc2cSWeiyi Lu 	"osc_d4"
112acddfc2cSWeiyi Lu };
113acddfc2cSWeiyi Lu 
114acddfc2cSWeiyi Lu static const char * const mm_parents[] = {
115acddfc2cSWeiyi Lu 	"clk26m",
116acddfc2cSWeiyi Lu 	"mmpll_d7",
117acddfc2cSWeiyi Lu 	"syspll_d3",
118acddfc2cSWeiyi Lu 	"univpll_d2_d2",
119acddfc2cSWeiyi Lu 	"syspll_d2_d2",
120acddfc2cSWeiyi Lu 	"syspll_d3_d2"
121acddfc2cSWeiyi Lu };
122acddfc2cSWeiyi Lu 
123acddfc2cSWeiyi Lu static const char * const img_parents[] = {
124acddfc2cSWeiyi Lu 	"clk26m",
125acddfc2cSWeiyi Lu 	"mmpll_d6",
126acddfc2cSWeiyi Lu 	"univpll_d3",
127acddfc2cSWeiyi Lu 	"syspll_d3",
128acddfc2cSWeiyi Lu 	"univpll_d2_d2",
129acddfc2cSWeiyi Lu 	"syspll_d2_d2",
130acddfc2cSWeiyi Lu 	"univpll_d3_d2",
131acddfc2cSWeiyi Lu 	"syspll_d3_d2"
132acddfc2cSWeiyi Lu };
133acddfc2cSWeiyi Lu 
134acddfc2cSWeiyi Lu static const char * const cam_parents[] = {
135acddfc2cSWeiyi Lu 	"clk26m",
136acddfc2cSWeiyi Lu 	"syspll_d2",
137acddfc2cSWeiyi Lu 	"mmpll_d6",
138acddfc2cSWeiyi Lu 	"syspll_d3",
139acddfc2cSWeiyi Lu 	"mmpll_d7",
140acddfc2cSWeiyi Lu 	"univpll_d3",
141acddfc2cSWeiyi Lu 	"univpll_d2_d2",
142acddfc2cSWeiyi Lu 	"syspll_d2_d2",
143acddfc2cSWeiyi Lu 	"syspll_d3_d2",
144acddfc2cSWeiyi Lu 	"univpll_d3_d2"
145acddfc2cSWeiyi Lu };
146acddfc2cSWeiyi Lu 
147acddfc2cSWeiyi Lu static const char * const dsp_parents[] = {
148acddfc2cSWeiyi Lu 	"clk26m",
149acddfc2cSWeiyi Lu 	"mmpll_d6",
150acddfc2cSWeiyi Lu 	"mmpll_d7",
151acddfc2cSWeiyi Lu 	"univpll_d3",
152acddfc2cSWeiyi Lu 	"syspll_d3",
153acddfc2cSWeiyi Lu 	"univpll_d2_d2",
154acddfc2cSWeiyi Lu 	"syspll_d2_d2",
155acddfc2cSWeiyi Lu 	"univpll_d3_d2",
156acddfc2cSWeiyi Lu 	"syspll_d3_d2"
157acddfc2cSWeiyi Lu };
158acddfc2cSWeiyi Lu 
159acddfc2cSWeiyi Lu static const char * const dsp1_parents[] = {
160acddfc2cSWeiyi Lu 	"clk26m",
161acddfc2cSWeiyi Lu 	"mmpll_d6",
162acddfc2cSWeiyi Lu 	"mmpll_d7",
163acddfc2cSWeiyi Lu 	"univpll_d3",
164acddfc2cSWeiyi Lu 	"syspll_d3",
165acddfc2cSWeiyi Lu 	"univpll_d2_d2",
166acddfc2cSWeiyi Lu 	"syspll_d2_d2",
167acddfc2cSWeiyi Lu 	"univpll_d3_d2",
168acddfc2cSWeiyi Lu 	"syspll_d3_d2"
169acddfc2cSWeiyi Lu };
170acddfc2cSWeiyi Lu 
171acddfc2cSWeiyi Lu static const char * const dsp2_parents[] = {
172acddfc2cSWeiyi Lu 	"clk26m",
173acddfc2cSWeiyi Lu 	"mmpll_d6",
174acddfc2cSWeiyi Lu 	"mmpll_d7",
175acddfc2cSWeiyi Lu 	"univpll_d3",
176acddfc2cSWeiyi Lu 	"syspll_d3",
177acddfc2cSWeiyi Lu 	"univpll_d2_d2",
178acddfc2cSWeiyi Lu 	"syspll_d2_d2",
179acddfc2cSWeiyi Lu 	"univpll_d3_d2",
180acddfc2cSWeiyi Lu 	"syspll_d3_d2"
181acddfc2cSWeiyi Lu };
182acddfc2cSWeiyi Lu 
183acddfc2cSWeiyi Lu static const char * const ipu_if_parents[] = {
184acddfc2cSWeiyi Lu 	"clk26m",
185acddfc2cSWeiyi Lu 	"mmpll_d6",
186acddfc2cSWeiyi Lu 	"mmpll_d7",
187acddfc2cSWeiyi Lu 	"univpll_d3",
188acddfc2cSWeiyi Lu 	"syspll_d3",
189acddfc2cSWeiyi Lu 	"univpll_d2_d2",
190acddfc2cSWeiyi Lu 	"syspll_d2_d2",
191acddfc2cSWeiyi Lu 	"univpll_d3_d2",
192acddfc2cSWeiyi Lu 	"syspll_d3_d2"
193acddfc2cSWeiyi Lu };
194acddfc2cSWeiyi Lu 
195acddfc2cSWeiyi Lu static const char * const mfg_parents[] = {
196acddfc2cSWeiyi Lu 	"clk26m",
197acddfc2cSWeiyi Lu 	"mfgpll_ck",
198acddfc2cSWeiyi Lu 	"univpll_d3",
199acddfc2cSWeiyi Lu 	"syspll_d3"
200acddfc2cSWeiyi Lu };
201acddfc2cSWeiyi Lu 
202acddfc2cSWeiyi Lu static const char * const f52m_mfg_parents[] = {
203acddfc2cSWeiyi Lu 	"clk26m",
204acddfc2cSWeiyi Lu 	"univpll_d3_d2",
205acddfc2cSWeiyi Lu 	"univpll_d3_d4",
206acddfc2cSWeiyi Lu 	"univpll_d3_d8"
207acddfc2cSWeiyi Lu };
208acddfc2cSWeiyi Lu 
209acddfc2cSWeiyi Lu static const char * const camtg_parents[] = {
210acddfc2cSWeiyi Lu 	"clk26m",
211acddfc2cSWeiyi Lu 	"univ_192m_d8",
212acddfc2cSWeiyi Lu 	"univpll_d3_d8",
213acddfc2cSWeiyi Lu 	"univ_192m_d4",
214acddfc2cSWeiyi Lu 	"univpll_d3_d16",
215acddfc2cSWeiyi Lu 	"csw_f26m_ck_d2",
216acddfc2cSWeiyi Lu 	"univ_192m_d16",
217acddfc2cSWeiyi Lu 	"univ_192m_d32"
218acddfc2cSWeiyi Lu };
219acddfc2cSWeiyi Lu 
220acddfc2cSWeiyi Lu static const char * const camtg2_parents[] = {
221acddfc2cSWeiyi Lu 	"clk26m",
222acddfc2cSWeiyi Lu 	"univ_192m_d8",
223acddfc2cSWeiyi Lu 	"univpll_d3_d8",
224acddfc2cSWeiyi Lu 	"univ_192m_d4",
225acddfc2cSWeiyi Lu 	"univpll_d3_d16",
226acddfc2cSWeiyi Lu 	"csw_f26m_ck_d2",
227acddfc2cSWeiyi Lu 	"univ_192m_d16",
228acddfc2cSWeiyi Lu 	"univ_192m_d32"
229acddfc2cSWeiyi Lu };
230acddfc2cSWeiyi Lu 
231acddfc2cSWeiyi Lu static const char * const camtg3_parents[] = {
232acddfc2cSWeiyi Lu 	"clk26m",
233acddfc2cSWeiyi Lu 	"univ_192m_d8",
234acddfc2cSWeiyi Lu 	"univpll_d3_d8",
235acddfc2cSWeiyi Lu 	"univ_192m_d4",
236acddfc2cSWeiyi Lu 	"univpll_d3_d16",
237acddfc2cSWeiyi Lu 	"csw_f26m_ck_d2",
238acddfc2cSWeiyi Lu 	"univ_192m_d16",
239acddfc2cSWeiyi Lu 	"univ_192m_d32"
240acddfc2cSWeiyi Lu };
241acddfc2cSWeiyi Lu 
242acddfc2cSWeiyi Lu static const char * const camtg4_parents[] = {
243acddfc2cSWeiyi Lu 	"clk26m",
244acddfc2cSWeiyi Lu 	"univ_192m_d8",
245acddfc2cSWeiyi Lu 	"univpll_d3_d8",
246acddfc2cSWeiyi Lu 	"univ_192m_d4",
247acddfc2cSWeiyi Lu 	"univpll_d3_d16",
248acddfc2cSWeiyi Lu 	"csw_f26m_ck_d2",
249acddfc2cSWeiyi Lu 	"univ_192m_d16",
250acddfc2cSWeiyi Lu 	"univ_192m_d32"
251acddfc2cSWeiyi Lu };
252acddfc2cSWeiyi Lu 
253acddfc2cSWeiyi Lu static const char * const uart_parents[] = {
254acddfc2cSWeiyi Lu 	"clk26m",
255acddfc2cSWeiyi Lu 	"univpll_d3_d8"
256acddfc2cSWeiyi Lu };
257acddfc2cSWeiyi Lu 
258acddfc2cSWeiyi Lu static const char * const spi_parents[] = {
259acddfc2cSWeiyi Lu 	"clk26m",
260acddfc2cSWeiyi Lu 	"syspll_d5_d2",
261acddfc2cSWeiyi Lu 	"syspll_d3_d4",
262acddfc2cSWeiyi Lu 	"msdcpll_d4"
263acddfc2cSWeiyi Lu };
264acddfc2cSWeiyi Lu 
265acddfc2cSWeiyi Lu static const char * const msdc50_hclk_parents[] = {
266acddfc2cSWeiyi Lu 	"clk26m",
267acddfc2cSWeiyi Lu 	"syspll_d2_d2",
268acddfc2cSWeiyi Lu 	"syspll_d3_d2"
269acddfc2cSWeiyi Lu };
270acddfc2cSWeiyi Lu 
271acddfc2cSWeiyi Lu static const char * const msdc50_0_parents[] = {
272acddfc2cSWeiyi Lu 	"clk26m",
273acddfc2cSWeiyi Lu 	"msdcpll_ck",
274acddfc2cSWeiyi Lu 	"msdcpll_d2",
275acddfc2cSWeiyi Lu 	"univpll_d2_d4",
276acddfc2cSWeiyi Lu 	"syspll_d3_d2",
277acddfc2cSWeiyi Lu 	"univpll_d2_d2"
278acddfc2cSWeiyi Lu };
279acddfc2cSWeiyi Lu 
280acddfc2cSWeiyi Lu static const char * const msdc30_1_parents[] = {
281acddfc2cSWeiyi Lu 	"clk26m",
282acddfc2cSWeiyi Lu 	"univpll_d3_d2",
283acddfc2cSWeiyi Lu 	"syspll_d3_d2",
284acddfc2cSWeiyi Lu 	"syspll_d7",
285acddfc2cSWeiyi Lu 	"msdcpll_d2"
286acddfc2cSWeiyi Lu };
287acddfc2cSWeiyi Lu 
288acddfc2cSWeiyi Lu static const char * const msdc30_2_parents[] = {
289acddfc2cSWeiyi Lu 	"clk26m",
290acddfc2cSWeiyi Lu 	"univpll_d3_d2",
291acddfc2cSWeiyi Lu 	"syspll_d3_d2",
292acddfc2cSWeiyi Lu 	"syspll_d7",
293acddfc2cSWeiyi Lu 	"msdcpll_d2"
294acddfc2cSWeiyi Lu };
295acddfc2cSWeiyi Lu 
296acddfc2cSWeiyi Lu static const char * const audio_parents[] = {
297acddfc2cSWeiyi Lu 	"clk26m",
298acddfc2cSWeiyi Lu 	"syspll_d5_d4",
299acddfc2cSWeiyi Lu 	"syspll_d7_d4",
300acddfc2cSWeiyi Lu 	"syspll_d2_d16"
301acddfc2cSWeiyi Lu };
302acddfc2cSWeiyi Lu 
303acddfc2cSWeiyi Lu static const char * const aud_intbus_parents[] = {
304acddfc2cSWeiyi Lu 	"clk26m",
305acddfc2cSWeiyi Lu 	"syspll_d2_d4",
306acddfc2cSWeiyi Lu 	"syspll_d7_d2"
307acddfc2cSWeiyi Lu };
308acddfc2cSWeiyi Lu 
309acddfc2cSWeiyi Lu static const char * const pmicspi_parents[] = {
310acddfc2cSWeiyi Lu 	"clk26m",
311acddfc2cSWeiyi Lu 	"syspll_d2_d8",
312acddfc2cSWeiyi Lu 	"osc_d8"
313acddfc2cSWeiyi Lu };
314acddfc2cSWeiyi Lu 
315acddfc2cSWeiyi Lu static const char * const fpwrap_ulposc_parents[] = {
316acddfc2cSWeiyi Lu 	"clk26m",
317acddfc2cSWeiyi Lu 	"osc_d16",
318acddfc2cSWeiyi Lu 	"osc_d4",
319acddfc2cSWeiyi Lu 	"osc_d8"
320acddfc2cSWeiyi Lu };
321acddfc2cSWeiyi Lu 
322acddfc2cSWeiyi Lu static const char * const atb_parents[] = {
323acddfc2cSWeiyi Lu 	"clk26m",
324acddfc2cSWeiyi Lu 	"syspll_d2_d2",
325acddfc2cSWeiyi Lu 	"syspll_d5"
326acddfc2cSWeiyi Lu };
327acddfc2cSWeiyi Lu 
328acddfc2cSWeiyi Lu static const char * const dpi0_parents[] = {
329acddfc2cSWeiyi Lu 	"clk26m",
330acddfc2cSWeiyi Lu 	"tvdpll_d2",
331acddfc2cSWeiyi Lu 	"tvdpll_d4",
332acddfc2cSWeiyi Lu 	"tvdpll_d8",
333acddfc2cSWeiyi Lu 	"tvdpll_d16",
334acddfc2cSWeiyi Lu 	"univpll_d5_d2",
335acddfc2cSWeiyi Lu 	"univpll_d3_d4",
336acddfc2cSWeiyi Lu 	"syspll_d3_d4",
337acddfc2cSWeiyi Lu 	"univpll_d3_d8"
338acddfc2cSWeiyi Lu };
339acddfc2cSWeiyi Lu 
340acddfc2cSWeiyi Lu static const char * const scam_parents[] = {
341acddfc2cSWeiyi Lu 	"clk26m",
342acddfc2cSWeiyi Lu 	"syspll_d5_d2"
343acddfc2cSWeiyi Lu };
344acddfc2cSWeiyi Lu 
345acddfc2cSWeiyi Lu static const char * const disppwm_parents[] = {
346acddfc2cSWeiyi Lu 	"clk26m",
347acddfc2cSWeiyi Lu 	"univpll_d3_d4",
348acddfc2cSWeiyi Lu 	"osc_d2",
349acddfc2cSWeiyi Lu 	"osc_d4",
350acddfc2cSWeiyi Lu 	"osc_d16"
351acddfc2cSWeiyi Lu };
352acddfc2cSWeiyi Lu 
353acddfc2cSWeiyi Lu static const char * const usb_top_parents[] = {
354acddfc2cSWeiyi Lu 	"clk26m",
355acddfc2cSWeiyi Lu 	"univpll_d5_d4",
356acddfc2cSWeiyi Lu 	"univpll_d3_d4",
357acddfc2cSWeiyi Lu 	"univpll_d5_d2"
358acddfc2cSWeiyi Lu };
359acddfc2cSWeiyi Lu 
360acddfc2cSWeiyi Lu 
361acddfc2cSWeiyi Lu static const char * const ssusb_top_xhci_parents[] = {
362acddfc2cSWeiyi Lu 	"clk26m",
363acddfc2cSWeiyi Lu 	"univpll_d5_d4",
364acddfc2cSWeiyi Lu 	"univpll_d3_d4",
365acddfc2cSWeiyi Lu 	"univpll_d5_d2"
366acddfc2cSWeiyi Lu };
367acddfc2cSWeiyi Lu 
368acddfc2cSWeiyi Lu static const char * const spm_parents[] = {
369acddfc2cSWeiyi Lu 	"clk26m",
370acddfc2cSWeiyi Lu 	"syspll_d2_d8"
371acddfc2cSWeiyi Lu };
372acddfc2cSWeiyi Lu 
373acddfc2cSWeiyi Lu static const char * const i2c_parents[] = {
374acddfc2cSWeiyi Lu 	"clk26m",
375acddfc2cSWeiyi Lu 	"syspll_d2_d8",
376acddfc2cSWeiyi Lu 	"univpll_d5_d2"
377acddfc2cSWeiyi Lu };
378acddfc2cSWeiyi Lu 
379acddfc2cSWeiyi Lu static const char * const scp_parents[] = {
380acddfc2cSWeiyi Lu 	"clk26m",
381acddfc2cSWeiyi Lu 	"univpll_d2_d8",
382acddfc2cSWeiyi Lu 	"syspll_d5",
383acddfc2cSWeiyi Lu 	"syspll_d2_d2",
384acddfc2cSWeiyi Lu 	"univpll_d2_d2",
385acddfc2cSWeiyi Lu 	"syspll_d3",
386acddfc2cSWeiyi Lu 	"univpll_d3"
387acddfc2cSWeiyi Lu };
388acddfc2cSWeiyi Lu 
389acddfc2cSWeiyi Lu static const char * const seninf_parents[] = {
390acddfc2cSWeiyi Lu 	"clk26m",
391acddfc2cSWeiyi Lu 	"univpll_d2_d2",
392acddfc2cSWeiyi Lu 	"univpll_d3_d2",
393acddfc2cSWeiyi Lu 	"univpll_d2_d4"
394acddfc2cSWeiyi Lu };
395acddfc2cSWeiyi Lu 
396acddfc2cSWeiyi Lu static const char * const dxcc_parents[] = {
397acddfc2cSWeiyi Lu 	"clk26m",
398acddfc2cSWeiyi Lu 	"syspll_d2_d2",
399acddfc2cSWeiyi Lu 	"syspll_d2_d4",
400acddfc2cSWeiyi Lu 	"syspll_d2_d8"
401acddfc2cSWeiyi Lu };
402acddfc2cSWeiyi Lu 
403acddfc2cSWeiyi Lu static const char * const aud_engen1_parents[] = {
404acddfc2cSWeiyi Lu 	"clk26m",
405acddfc2cSWeiyi Lu 	"apll1_d2",
406acddfc2cSWeiyi Lu 	"apll1_d4",
407acddfc2cSWeiyi Lu 	"apll1_d8"
408acddfc2cSWeiyi Lu };
409acddfc2cSWeiyi Lu 
410acddfc2cSWeiyi Lu static const char * const aud_engen2_parents[] = {
411acddfc2cSWeiyi Lu 	"clk26m",
412acddfc2cSWeiyi Lu 	"apll2_d2",
413acddfc2cSWeiyi Lu 	"apll2_d4",
414acddfc2cSWeiyi Lu 	"apll2_d8"
415acddfc2cSWeiyi Lu };
416acddfc2cSWeiyi Lu 
417acddfc2cSWeiyi Lu static const char * const faes_ufsfde_parents[] = {
418acddfc2cSWeiyi Lu 	"clk26m",
419acddfc2cSWeiyi Lu 	"syspll_d2",
420acddfc2cSWeiyi Lu 	"syspll_d2_d2",
421acddfc2cSWeiyi Lu 	"syspll_d3",
422acddfc2cSWeiyi Lu 	"syspll_d2_d4",
423acddfc2cSWeiyi Lu 	"univpll_d3"
424acddfc2cSWeiyi Lu };
425acddfc2cSWeiyi Lu 
426acddfc2cSWeiyi Lu static const char * const fufs_parents[] = {
427acddfc2cSWeiyi Lu 	"clk26m",
428acddfc2cSWeiyi Lu 	"syspll_d2_d4",
429acddfc2cSWeiyi Lu 	"syspll_d2_d8",
430acddfc2cSWeiyi Lu 	"syspll_d2_d16"
431acddfc2cSWeiyi Lu };
432acddfc2cSWeiyi Lu 
433acddfc2cSWeiyi Lu static const char * const aud_1_parents[] = {
434acddfc2cSWeiyi Lu 	"clk26m",
435acddfc2cSWeiyi Lu 	"apll1_ck"
436acddfc2cSWeiyi Lu };
437acddfc2cSWeiyi Lu 
438acddfc2cSWeiyi Lu static const char * const aud_2_parents[] = {
439acddfc2cSWeiyi Lu 	"clk26m",
440acddfc2cSWeiyi Lu 	"apll2_ck"
441acddfc2cSWeiyi Lu };
442acddfc2cSWeiyi Lu 
443acddfc2cSWeiyi Lu /*
444acddfc2cSWeiyi Lu  * CRITICAL CLOCK:
445acddfc2cSWeiyi Lu  * axi_sel is the main bus clock of whole SOC.
446acddfc2cSWeiyi Lu  * spm_sel is the clock of the always-on co-processor.
447acddfc2cSWeiyi Lu  */
448acddfc2cSWeiyi Lu static const struct mtk_mux top_muxes[] = {
449acddfc2cSWeiyi Lu 	/* CLK_CFG_0 */
450acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
451*2f140dabSAngeloGioacchino Del Regno 		axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
452acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
453*2f140dabSAngeloGioacchino Del Regno 		mm_parents, 0x40, 0x44, 0x48, 8, 3, 15, 0x004, 1),
454acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
455*2f140dabSAngeloGioacchino Del Regno 		img_parents, 0x40, 0x44, 0x48, 16, 3, 23, 0x004, 2),
456acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
457*2f140dabSAngeloGioacchino Del Regno 		cam_parents, 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 3),
458acddfc2cSWeiyi Lu 	/* CLK_CFG_1 */
459acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
460*2f140dabSAngeloGioacchino Del Regno 		dsp_parents, 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 4),
461acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
462*2f140dabSAngeloGioacchino Del Regno 		dsp1_parents, 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 5),
463acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
464*2f140dabSAngeloGioacchino Del Regno 		dsp2_parents, 0x50, 0x54, 0x58, 16, 4, 23, 0x004, 6),
465acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
466*2f140dabSAngeloGioacchino Del Regno 		ipu_if_parents, 0x50, 0x54, 0x58, 24, 4, 31, 0x004, 7),
467acddfc2cSWeiyi Lu 	/* CLK_CFG_2 */
468acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
469*2f140dabSAngeloGioacchino Del Regno 		mfg_parents, 0x60, 0x64, 0x68, 0, 2, 7, 0x004, 8),
470acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
471*2f140dabSAngeloGioacchino Del Regno 		f52m_mfg_parents, 0x60, 0x64, 0x68, 8, 2, 15, 0x004, 9),
472acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
473*2f140dabSAngeloGioacchino Del Regno 		camtg_parents, 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 10),
474acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel",
475*2f140dabSAngeloGioacchino Del Regno 		camtg2_parents, 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 11),
476acddfc2cSWeiyi Lu 	/* CLK_CFG_3 */
477acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel",
478*2f140dabSAngeloGioacchino Del Regno 		camtg3_parents, 0x70, 0x74, 0x78, 0, 3, 7, 0x004, 12),
479acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel",
480*2f140dabSAngeloGioacchino Del Regno 		camtg4_parents, 0x70, 0x74, 0x78, 8, 3, 15, 0x004, 13),
481acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
482*2f140dabSAngeloGioacchino Del Regno 		uart_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x004, 14),
483acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
484*2f140dabSAngeloGioacchino Del Regno 		spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15),
485acddfc2cSWeiyi Lu 	/* CLK_CFG_4 */
486acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
487*2f140dabSAngeloGioacchino Del Regno 		msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16),
488acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
489*2f140dabSAngeloGioacchino Del Regno 		msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17),
490acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
491*2f140dabSAngeloGioacchino Del Regno 		msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18),
492acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
493*2f140dabSAngeloGioacchino Del Regno 		msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19),
494acddfc2cSWeiyi Lu 	/* CLK_CFG_5 */
495acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
496*2f140dabSAngeloGioacchino Del Regno 		audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20),
497acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel",
498*2f140dabSAngeloGioacchino Del Regno 		aud_intbus_parents, 0x90, 0x94, 0x98, 8, 2, 15, 0x004, 21),
499acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel",
500*2f140dabSAngeloGioacchino Del Regno 		pmicspi_parents, 0x90, 0x94, 0x98, 16, 2, 23, 0x004, 22),
501acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
502*2f140dabSAngeloGioacchino Del Regno 		fpwrap_ulposc_parents, 0x90, 0x94, 0x98, 24, 2, 31, 0x004, 23),
503acddfc2cSWeiyi Lu 	/* CLK_CFG_6 */
504acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
505*2f140dabSAngeloGioacchino Del Regno 		atb_parents, 0xa0, 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
506acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
507*2f140dabSAngeloGioacchino Del Regno 		dpi0_parents, 0xa0, 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
508acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
509*2f140dabSAngeloGioacchino Del Regno 		scam_parents, 0xa0, 0xa4, 0xa8, 24, 1, 31, 0x004, 27),
510acddfc2cSWeiyi Lu 	/* CLK_CFG_7 */
511acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel",
512*2f140dabSAngeloGioacchino Del Regno 		disppwm_parents, 0xb0, 0xb4, 0xb8, 0, 3, 7, 0x004, 28),
513acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel",
514*2f140dabSAngeloGioacchino Del Regno 		usb_top_parents, 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x004, 29),
515acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
516*2f140dabSAngeloGioacchino Del Regno 		ssusb_top_xhci_parents, 0xb0, 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
517acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
518*2f140dabSAngeloGioacchino Del Regno 		spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL),
519acddfc2cSWeiyi Lu 	/* CLK_CFG_8 */
520acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
521*2f140dabSAngeloGioacchino Del Regno 		i2c_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
522acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel",
523*2f140dabSAngeloGioacchino Del Regno 		scp_parents, 0xc0, 0xc4, 0xc8, 8, 3, 15, 0x008, 2),
524acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel",
525*2f140dabSAngeloGioacchino Del Regno 		seninf_parents, 0xc0, 0xc4, 0xc8, 16, 2, 23, 0x008, 3),
526acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel",
527*2f140dabSAngeloGioacchino Del Regno 		dxcc_parents, 0xc0, 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
528acddfc2cSWeiyi Lu 	/* CLK_CFG_9 */
529acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel",
530*2f140dabSAngeloGioacchino Del Regno 		aud_engen1_parents, 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 5),
531acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel",
532*2f140dabSAngeloGioacchino Del Regno 		aud_engen2_parents, 0xd0, 0xd4, 0xd8, 8, 2, 15, 0x008, 6),
533acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel",
534*2f140dabSAngeloGioacchino Del Regno 		faes_ufsfde_parents, 0xd0, 0xd4, 0xd8, 16, 3, 23, 0x008, 7),
535acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel",
536*2f140dabSAngeloGioacchino Del Regno 		fufs_parents, 0xd0, 0xd4, 0xd8, 24, 2, 31, 0x008, 8),
537acddfc2cSWeiyi Lu 	/* CLK_CFG_10 */
538acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
539*2f140dabSAngeloGioacchino Del Regno 		aud_1_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
540acddfc2cSWeiyi Lu 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
541*2f140dabSAngeloGioacchino Del Regno 		aud_2_parents, 0xe0, 0xe4, 0xe8, 8, 1, 15, 0x008, 10),
542acddfc2cSWeiyi Lu };
543acddfc2cSWeiyi Lu 
544acddfc2cSWeiyi Lu static const char * const apll_i2s0_parents[] = {
545acddfc2cSWeiyi Lu 	"aud_1_sel",
546acddfc2cSWeiyi Lu 	"aud_2_sel"
547acddfc2cSWeiyi Lu };
548acddfc2cSWeiyi Lu 
549acddfc2cSWeiyi Lu static const char * const apll_i2s1_parents[] = {
550acddfc2cSWeiyi Lu 	"aud_1_sel",
551acddfc2cSWeiyi Lu 	"aud_2_sel"
552acddfc2cSWeiyi Lu };
553acddfc2cSWeiyi Lu 
554acddfc2cSWeiyi Lu static const char * const apll_i2s2_parents[] = {
555acddfc2cSWeiyi Lu 	"aud_1_sel",
556acddfc2cSWeiyi Lu 	"aud_2_sel"
557acddfc2cSWeiyi Lu };
558acddfc2cSWeiyi Lu 
559acddfc2cSWeiyi Lu static const char * const apll_i2s3_parents[] = {
560acddfc2cSWeiyi Lu 	"aud_1_sel",
561acddfc2cSWeiyi Lu 	"aud_2_sel"
562acddfc2cSWeiyi Lu };
563acddfc2cSWeiyi Lu 
564acddfc2cSWeiyi Lu static const char * const apll_i2s4_parents[] = {
565acddfc2cSWeiyi Lu 	"aud_1_sel",
566acddfc2cSWeiyi Lu 	"aud_2_sel"
567acddfc2cSWeiyi Lu };
568acddfc2cSWeiyi Lu 
569acddfc2cSWeiyi Lu static const char * const apll_i2s5_parents[] = {
570acddfc2cSWeiyi Lu 	"aud_1_sel",
571acddfc2cSWeiyi Lu 	"aud_2_sel"
572acddfc2cSWeiyi Lu };
573acddfc2cSWeiyi Lu 
574acddfc2cSWeiyi Lu static const char * const mcu_mp0_parents[] = {
575acddfc2cSWeiyi Lu 	"clk26m",
576acddfc2cSWeiyi Lu 	"armpll_ll",
577acddfc2cSWeiyi Lu 	"armpll_div_pll1",
578acddfc2cSWeiyi Lu 	"armpll_div_pll2"
579acddfc2cSWeiyi Lu };
580acddfc2cSWeiyi Lu 
581acddfc2cSWeiyi Lu static const char * const mcu_mp2_parents[] = {
582acddfc2cSWeiyi Lu 	"clk26m",
583acddfc2cSWeiyi Lu 	"armpll_l",
584acddfc2cSWeiyi Lu 	"armpll_div_pll1",
585acddfc2cSWeiyi Lu 	"armpll_div_pll2"
586acddfc2cSWeiyi Lu };
587acddfc2cSWeiyi Lu 
588acddfc2cSWeiyi Lu static const char * const mcu_bus_parents[] = {
589acddfc2cSWeiyi Lu 	"clk26m",
590acddfc2cSWeiyi Lu 	"ccipll",
591acddfc2cSWeiyi Lu 	"armpll_div_pll1",
592acddfc2cSWeiyi Lu 	"armpll_div_pll2"
593acddfc2cSWeiyi Lu };
594acddfc2cSWeiyi Lu 
595acddfc2cSWeiyi Lu static struct mtk_composite mcu_muxes[] = {
596acddfc2cSWeiyi Lu 	/* mp0_pll_divider_cfg */
597acddfc2cSWeiyi Lu 	MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
598acddfc2cSWeiyi Lu 	/* mp2_pll_divider_cfg */
599acddfc2cSWeiyi Lu 	MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2),
600acddfc2cSWeiyi Lu 	/* bus_pll_divider_cfg */
601acddfc2cSWeiyi Lu 	MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
602acddfc2cSWeiyi Lu };
603acddfc2cSWeiyi Lu 
604d7595ddeSAngeloGioacchino Del Regno static struct mtk_composite top_aud_comp[] = {
605*2f140dabSAngeloGioacchino Del Regno 	MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 0x320, 8, 1),
606*2f140dabSAngeloGioacchino Del Regno 	MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 0x320, 9, 1),
607*2f140dabSAngeloGioacchino Del Regno 	MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 0x320, 10, 1),
608*2f140dabSAngeloGioacchino Del Regno 	MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 0x320, 11, 1),
609*2f140dabSAngeloGioacchino Del Regno 	MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 0x320, 12, 1),
610*2f140dabSAngeloGioacchino Del Regno 	MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 0x328, 20, 1),
611*2f140dabSAngeloGioacchino Del Regno 	DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 0x320, 2, 0x324, 8, 0),
612*2f140dabSAngeloGioacchino Del Regno 	DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 0x320, 3, 0x324, 8, 8),
613*2f140dabSAngeloGioacchino Del Regno 	DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 0x320, 4, 0x324, 8, 16),
614*2f140dabSAngeloGioacchino Del Regno 	DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 0x320, 5, 0x324, 8, 24),
615*2f140dabSAngeloGioacchino Del Regno 	DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 0x320, 6, 0x328, 8, 0),
616*2f140dabSAngeloGioacchino Del Regno 	DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 7, 0x328, 8, 8),
617acddfc2cSWeiyi Lu };
618acddfc2cSWeiyi Lu 
619acddfc2cSWeiyi Lu static const struct mtk_gate_regs top_cg_regs = {
620acddfc2cSWeiyi Lu 	.set_ofs = 0x104,
621acddfc2cSWeiyi Lu 	.clr_ofs = 0x104,
622acddfc2cSWeiyi Lu 	.sta_ofs = 0x104,
623acddfc2cSWeiyi Lu };
624acddfc2cSWeiyi Lu 
625acddfc2cSWeiyi Lu #define GATE_TOP(_id, _name, _parent, _shift)			\
626acddfc2cSWeiyi Lu 	GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift,	\
627acddfc2cSWeiyi Lu 		&mtk_clk_gate_ops_no_setclr_inv)
628acddfc2cSWeiyi Lu 
629acddfc2cSWeiyi Lu static const struct mtk_gate top_clks[] = {
630acddfc2cSWeiyi Lu 	/* TOP */
631acddfc2cSWeiyi Lu 	GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),
632acddfc2cSWeiyi Lu 	GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5),
633acddfc2cSWeiyi Lu };
634acddfc2cSWeiyi Lu 
635acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra0_cg_regs = {
636acddfc2cSWeiyi Lu 	.set_ofs = 0x80,
637acddfc2cSWeiyi Lu 	.clr_ofs = 0x84,
638acddfc2cSWeiyi Lu 	.sta_ofs = 0x90,
639acddfc2cSWeiyi Lu };
640acddfc2cSWeiyi Lu 
641acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra1_cg_regs = {
642acddfc2cSWeiyi Lu 	.set_ofs = 0x88,
643acddfc2cSWeiyi Lu 	.clr_ofs = 0x8c,
644acddfc2cSWeiyi Lu 	.sta_ofs = 0x94,
645acddfc2cSWeiyi Lu };
646acddfc2cSWeiyi Lu 
647acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra2_cg_regs = {
648acddfc2cSWeiyi Lu 	.set_ofs = 0xa4,
649acddfc2cSWeiyi Lu 	.clr_ofs = 0xa8,
650acddfc2cSWeiyi Lu 	.sta_ofs = 0xac,
651acddfc2cSWeiyi Lu };
652acddfc2cSWeiyi Lu 
653acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra3_cg_regs = {
654acddfc2cSWeiyi Lu 	.set_ofs = 0xc0,
655acddfc2cSWeiyi Lu 	.clr_ofs = 0xc4,
656acddfc2cSWeiyi Lu 	.sta_ofs = 0xc8,
657acddfc2cSWeiyi Lu };
658acddfc2cSWeiyi Lu 
659acddfc2cSWeiyi Lu #define GATE_INFRA0(_id, _name, _parent, _shift)		\
660acddfc2cSWeiyi Lu 	GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift,	\
661acddfc2cSWeiyi Lu 		&mtk_clk_gate_ops_setclr)
662acddfc2cSWeiyi Lu 
663acddfc2cSWeiyi Lu #define GATE_INFRA1(_id, _name, _parent, _shift)		\
664acddfc2cSWeiyi Lu 	GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift,	\
665acddfc2cSWeiyi Lu 		&mtk_clk_gate_ops_setclr)
666acddfc2cSWeiyi Lu 
667acddfc2cSWeiyi Lu #define GATE_INFRA2(_id, _name, _parent, _shift)		\
668acddfc2cSWeiyi Lu 	GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift,	\
669acddfc2cSWeiyi Lu 		&mtk_clk_gate_ops_setclr)
670acddfc2cSWeiyi Lu 
671acddfc2cSWeiyi Lu #define GATE_INFRA3(_id, _name, _parent, _shift)		\
672acddfc2cSWeiyi Lu 	GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift,	\
673acddfc2cSWeiyi Lu 		&mtk_clk_gate_ops_setclr)
674acddfc2cSWeiyi Lu 
675acddfc2cSWeiyi Lu static const struct mtk_gate infra_clks[] = {
676acddfc2cSWeiyi Lu 	/* INFRA0 */
677*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0),
678*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "axi_sel", 1),
679*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "axi_sel", 2),
680*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "axi_sel", 3),
681*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", "scp_sel", 4),
682*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "f_f26m_ck", 5),
683*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
684*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", "axi_sel", 8),
685*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
686*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
687*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11),
688*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", "i2c_sel", 12),
689*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13),
690*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14),
691*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
692*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "i2c_sel", 16),
693*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "i2c_sel", 17),
694*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "i2c_sel", 18),
695*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "i2c_sel", 19),
696*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "i2c_sel", 21),
697*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
698*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
699*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
700*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
701*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27),
702*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", "axi_sel", 28),
703*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
704acddfc2cSWeiyi Lu 	/* INFRA1 */
705*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1),
706*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_hclk_sel", 2),
707*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "axi_sel", 4),
708*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "axi_sel", 5),
709*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", "msdc50_0_sel", 6),
710*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", "f_f26m_ck", 7),
711*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
712*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
713*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "f_f26m_ck", 10),
714*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
715*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12),
716*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13),
717*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "f_f26m_ck", 14),
718*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", "msdc30_1_sel", 16),
719*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", "msdc30_2_sel", 17),
720*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", "axi_sel", 18),
721*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", "axi_sel", 19),
722*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
723*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
724*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24),
725*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
726*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
727*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27),
728*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28),
729*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", "axi_sel", 30),
730*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "f_f26m_ck", 31),
731acddfc2cSWeiyi Lu 	/* INFRA2 */
732*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "f_f26m_ck", 0),
733*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_USB, "infra_usb", "usb_top_sel", 1),
734*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", "axi_sel", 2),
735*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", "axi_sel", 3),
736*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", "f_f26m_ck", 4),
737*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6),
738*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7),
739*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", "f_f26m_ck", 8),
740*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9),
741*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10),
742*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", "ssusb_top_xhci_sel", 11),
743*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "fufs_sel", 12),
744*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", "fufs_sel", 13),
745*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14),
746*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16),
747*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18),
748*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19),
749*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20),
750*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21),
751*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22),
752*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23),
753*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24),
754*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25),
755*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26),
756*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", "axi_sel", 27),
757*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "fufs_sel", 28),
758*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "faes_ufsfde_sel", 29),
759*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "fufs_sel", 30),
760acddfc2cSWeiyi Lu 	/* INFRA3 */
761*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0),
762*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1),
763*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2),
764*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5),
765*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6),
766*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_hclk_sel", 7),
767*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_hclk_sel", 8),
768*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16),
769*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17),
770*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18),
771*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19),
772*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "f_f26m_ck", 20),
773*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", "axi_sel", 21),
774*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22),
775*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23),
776*2f140dabSAngeloGioacchino Del Regno 	GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24),
777acddfc2cSWeiyi Lu };
778acddfc2cSWeiyi Lu 
779f9e55ac2SChunfeng Yun static const struct mtk_gate_regs peri_cg_regs = {
780f9e55ac2SChunfeng Yun 	.set_ofs = 0x20c,
781f9e55ac2SChunfeng Yun 	.clr_ofs = 0x20c,
782f9e55ac2SChunfeng Yun 	.sta_ofs = 0x20c,
783f9e55ac2SChunfeng Yun };
784f9e55ac2SChunfeng Yun 
785f9e55ac2SChunfeng Yun #define GATE_PERI(_id, _name, _parent, _shift)			\
786f9e55ac2SChunfeng Yun 	GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift,	\
787f9e55ac2SChunfeng Yun 		&mtk_clk_gate_ops_no_setclr_inv)
788f9e55ac2SChunfeng Yun 
789f9e55ac2SChunfeng Yun static const struct mtk_gate peri_clks[] = {
790f9e55ac2SChunfeng Yun 	GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
791f9e55ac2SChunfeng Yun };
792f9e55ac2SChunfeng Yun 
793723e3671SRex-BC Chen static u16 infra_rst_ofs[] = {
794723e3671SRex-BC Chen 	INFRA_RST0_SET_OFFSET,
795723e3671SRex-BC Chen 	INFRA_RST1_SET_OFFSET,
796723e3671SRex-BC Chen 	INFRA_RST2_SET_OFFSET,
797723e3671SRex-BC Chen 	INFRA_RST3_SET_OFFSET,
798723e3671SRex-BC Chen };
799723e3671SRex-BC Chen 
8002d2a2900SRex-BC Chen static const struct mtk_clk_rst_desc clk_rst_desc = {
8012d2a2900SRex-BC Chen 	.version = MTK_RST_SET_CLR,
802723e3671SRex-BC Chen 	.rst_bank_ofs = infra_rst_ofs,
803723e3671SRex-BC Chen 	.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
8042d2a2900SRex-BC Chen };
8052d2a2900SRex-BC Chen 
806609cc5e1SChen-Yu Tsai static struct clk_hw_onecell_data *top_clk_data;
807c93d059aSWeiyi Lu 
808c93d059aSWeiyi Lu static void clk_mt8183_top_init_early(struct device_node *node)
809c93d059aSWeiyi Lu {
810c93d059aSWeiyi Lu 	int i;
811c93d059aSWeiyi Lu 
812c93d059aSWeiyi Lu 	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
813c93d059aSWeiyi Lu 
814c93d059aSWeiyi Lu 	for (i = 0; i < CLK_TOP_NR_CLK; i++)
815609cc5e1SChen-Yu Tsai 		top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
816c93d059aSWeiyi Lu 
817c93d059aSWeiyi Lu 	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
818c93d059aSWeiyi Lu 			top_clk_data);
819c93d059aSWeiyi Lu 
820609cc5e1SChen-Yu Tsai 	of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
821c93d059aSWeiyi Lu }
822c93d059aSWeiyi Lu 
823c93d059aSWeiyi Lu CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
824c93d059aSWeiyi Lu 			clk_mt8183_top_init_early);
825c93d059aSWeiyi Lu 
826ae333e63SChen-Yu Tsai /* Register mux notifier for MFG mux */
827ae333e63SChen-Yu Tsai static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
828ae333e63SChen-Yu Tsai {
829ae333e63SChen-Yu Tsai 	struct mtk_mux_nb *mfg_mux_nb;
830ae333e63SChen-Yu Tsai 	int i;
831ae333e63SChen-Yu Tsai 
832ae333e63SChen-Yu Tsai 	mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
833ae333e63SChen-Yu Tsai 	if (!mfg_mux_nb)
834ae333e63SChen-Yu Tsai 		return -ENOMEM;
835ae333e63SChen-Yu Tsai 
836ae333e63SChen-Yu Tsai 	for (i = 0; i < ARRAY_SIZE(top_muxes); i++)
837ae333e63SChen-Yu Tsai 		if (top_muxes[i].id == CLK_TOP_MUX_MFG)
838ae333e63SChen-Yu Tsai 			break;
839ae333e63SChen-Yu Tsai 	if (i == ARRAY_SIZE(top_muxes))
840ae333e63SChen-Yu Tsai 		return -EINVAL;
841ae333e63SChen-Yu Tsai 
842ae333e63SChen-Yu Tsai 	mfg_mux_nb->ops = top_muxes[i].ops;
843ae333e63SChen-Yu Tsai 	mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
844ae333e63SChen-Yu Tsai 
845ae333e63SChen-Yu Tsai 	return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
846ae333e63SChen-Yu Tsai }
847ae333e63SChen-Yu Tsai 
848acddfc2cSWeiyi Lu static int clk_mt8183_top_probe(struct platform_device *pdev)
849acddfc2cSWeiyi Lu {
850acddfc2cSWeiyi Lu 	void __iomem *base;
851acddfc2cSWeiyi Lu 	struct device_node *node = pdev->dev.of_node;
852ae333e63SChen-Yu Tsai 	int ret;
853acddfc2cSWeiyi Lu 
854067de0a6SYueHaibing 	base = devm_platform_ioremap_resource(pdev, 0);
855acddfc2cSWeiyi Lu 	if (IS_ERR(base))
856acddfc2cSWeiyi Lu 		return PTR_ERR(base);
857acddfc2cSWeiyi Lu 
858acddfc2cSWeiyi Lu 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
859c93d059aSWeiyi Lu 		top_clk_data);
860acddfc2cSWeiyi Lu 
861c93d059aSWeiyi Lu 	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
862c93d059aSWeiyi Lu 		top_clk_data);
863c93d059aSWeiyi Lu 
864c93d059aSWeiyi Lu 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
865acddfc2cSWeiyi Lu 
866d3d6bd5eSAngeloGioacchino Del Regno 	mtk_clk_register_muxes(&pdev->dev, top_muxes,
867d3d6bd5eSAngeloGioacchino Del Regno 			       ARRAY_SIZE(top_muxes), node,
868d3d6bd5eSAngeloGioacchino Del Regno 			       &mt8183_clk_lock, top_clk_data);
869acddfc2cSWeiyi Lu 
870d7595ddeSAngeloGioacchino Del Regno 	mtk_clk_register_composites(&pdev->dev, top_aud_comp,
871d7595ddeSAngeloGioacchino Del Regno 				    ARRAY_SIZE(top_aud_comp), base,
87201a6c1abSAngeloGioacchino Del Regno 				    &mt8183_clk_lock, top_clk_data);
873acddfc2cSWeiyi Lu 
87420498d52SAngeloGioacchino Del Regno 	mtk_clk_register_gates(&pdev->dev, node, top_clks,
87520498d52SAngeloGioacchino Del Regno 			       ARRAY_SIZE(top_clks), top_clk_data);
876acddfc2cSWeiyi Lu 
877ae333e63SChen-Yu Tsai 	ret = clk_mt8183_reg_mfg_mux_notifier(&pdev->dev,
878ae333e63SChen-Yu Tsai 					      top_clk_data->hws[CLK_TOP_MUX_MFG]->clk);
879ae333e63SChen-Yu Tsai 	if (ret)
880ae333e63SChen-Yu Tsai 		return ret;
881ae333e63SChen-Yu Tsai 
882609cc5e1SChen-Yu Tsai 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
883609cc5e1SChen-Yu Tsai 				      top_clk_data);
884acddfc2cSWeiyi Lu }
885acddfc2cSWeiyi Lu 
886acddfc2cSWeiyi Lu static int clk_mt8183_mcu_probe(struct platform_device *pdev)
887acddfc2cSWeiyi Lu {
888609cc5e1SChen-Yu Tsai 	struct clk_hw_onecell_data *clk_data;
889acddfc2cSWeiyi Lu 	struct device_node *node = pdev->dev.of_node;
890acddfc2cSWeiyi Lu 	void __iomem *base;
891acddfc2cSWeiyi Lu 
892067de0a6SYueHaibing 	base = devm_platform_ioremap_resource(pdev, 0);
893acddfc2cSWeiyi Lu 	if (IS_ERR(base))
894acddfc2cSWeiyi Lu 		return PTR_ERR(base);
895acddfc2cSWeiyi Lu 
896acddfc2cSWeiyi Lu 	clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
897acddfc2cSWeiyi Lu 
89801a6c1abSAngeloGioacchino Del Regno 	mtk_clk_register_composites(&pdev->dev, mcu_muxes,
89901a6c1abSAngeloGioacchino Del Regno 				    ARRAY_SIZE(mcu_muxes), base,
900acddfc2cSWeiyi Lu 				    &mt8183_clk_lock, clk_data);
901acddfc2cSWeiyi Lu 
902609cc5e1SChen-Yu Tsai 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
903acddfc2cSWeiyi Lu }
904acddfc2cSWeiyi Lu 
905acddfc2cSWeiyi Lu static const struct of_device_id of_match_clk_mt8183[] = {
906acddfc2cSWeiyi Lu 	{
907acddfc2cSWeiyi Lu 		.compatible = "mediatek,mt8183-topckgen",
908acddfc2cSWeiyi Lu 		.data = clk_mt8183_top_probe,
909acddfc2cSWeiyi Lu 	}, {
910acddfc2cSWeiyi Lu 		.compatible = "mediatek,mt8183-mcucfg",
911acddfc2cSWeiyi Lu 		.data = clk_mt8183_mcu_probe,
912acddfc2cSWeiyi Lu 	}, {
913acddfc2cSWeiyi Lu 		/* sentinel */
914acddfc2cSWeiyi Lu 	}
915acddfc2cSWeiyi Lu };
916acddfc2cSWeiyi Lu 
917acddfc2cSWeiyi Lu static int clk_mt8183_probe(struct platform_device *pdev)
918acddfc2cSWeiyi Lu {
919acddfc2cSWeiyi Lu 	int (*clk_probe)(struct platform_device *pdev);
920acddfc2cSWeiyi Lu 	int r;
921acddfc2cSWeiyi Lu 
922acddfc2cSWeiyi Lu 	clk_probe = of_device_get_match_data(&pdev->dev);
923acddfc2cSWeiyi Lu 	if (!clk_probe)
924acddfc2cSWeiyi Lu 		return -EINVAL;
925acddfc2cSWeiyi Lu 
926acddfc2cSWeiyi Lu 	r = clk_probe(pdev);
927acddfc2cSWeiyi Lu 	if (r)
928acddfc2cSWeiyi Lu 		dev_err(&pdev->dev,
929acddfc2cSWeiyi Lu 			"could not register clock provider: %s: %d\n",
930acddfc2cSWeiyi Lu 			pdev->name, r);
931acddfc2cSWeiyi Lu 
932acddfc2cSWeiyi Lu 	return r;
933acddfc2cSWeiyi Lu }
934acddfc2cSWeiyi Lu 
9350f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc infra_desc = {
9360f69a423SAngeloGioacchino Del Regno 	.clks = infra_clks,
9370f69a423SAngeloGioacchino Del Regno 	.num_clks = ARRAY_SIZE(infra_clks),
9380f69a423SAngeloGioacchino Del Regno 	.rst_desc = &clk_rst_desc,
9390f69a423SAngeloGioacchino Del Regno };
9400f69a423SAngeloGioacchino Del Regno 
9410f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc peri_desc = {
9420f69a423SAngeloGioacchino Del Regno 	.clks = peri_clks,
9430f69a423SAngeloGioacchino Del Regno 	.num_clks = ARRAY_SIZE(peri_clks),
9440f69a423SAngeloGioacchino Del Regno };
9450f69a423SAngeloGioacchino Del Regno 
9460f69a423SAngeloGioacchino Del Regno static const struct of_device_id of_match_clk_mt8183_simple[] = {
9470f69a423SAngeloGioacchino Del Regno 	{ .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc },
9480f69a423SAngeloGioacchino Del Regno 	{ .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, },
9490f69a423SAngeloGioacchino Del Regno 	{ /* sentinel */ }
9500f69a423SAngeloGioacchino Del Regno };
9510f69a423SAngeloGioacchino Del Regno 
9520f69a423SAngeloGioacchino Del Regno static struct platform_driver clk_mt8183_simple_drv = {
9530f69a423SAngeloGioacchino Del Regno 	.probe = mtk_clk_simple_probe,
9540f69a423SAngeloGioacchino Del Regno 	.remove = mtk_clk_simple_remove,
9550f69a423SAngeloGioacchino Del Regno 	.driver = {
9560f69a423SAngeloGioacchino Del Regno 		.name = "clk-mt8183-simple",
9570f69a423SAngeloGioacchino Del Regno 		.of_match_table = of_match_clk_mt8183_simple,
9580f69a423SAngeloGioacchino Del Regno 	},
9590f69a423SAngeloGioacchino Del Regno };
9600f69a423SAngeloGioacchino Del Regno 
961acddfc2cSWeiyi Lu static struct platform_driver clk_mt8183_drv = {
962acddfc2cSWeiyi Lu 	.probe = clk_mt8183_probe,
963acddfc2cSWeiyi Lu 	.driver = {
964acddfc2cSWeiyi Lu 		.name = "clk-mt8183",
965acddfc2cSWeiyi Lu 		.of_match_table = of_match_clk_mt8183,
966acddfc2cSWeiyi Lu 	},
967acddfc2cSWeiyi Lu };
968acddfc2cSWeiyi Lu 
969acddfc2cSWeiyi Lu static int __init clk_mt8183_init(void)
970acddfc2cSWeiyi Lu {
9710f69a423SAngeloGioacchino Del Regno 	int ret = platform_driver_register(&clk_mt8183_drv);
9720f69a423SAngeloGioacchino Del Regno 
9730f69a423SAngeloGioacchino Del Regno 	if (ret)
9740f69a423SAngeloGioacchino Del Regno 		return ret;
9750f69a423SAngeloGioacchino Del Regno 	return platform_driver_register(&clk_mt8183_simple_drv);
976acddfc2cSWeiyi Lu }
977acddfc2cSWeiyi Lu 
978acddfc2cSWeiyi Lu arch_initcall(clk_mt8183_init);
979