1acddfc2cSWeiyi Lu // SPDX-License-Identifier: GPL-2.0 2acddfc2cSWeiyi Lu // 3acddfc2cSWeiyi Lu // Copyright (c) 2018 MediaTek Inc. 4acddfc2cSWeiyi Lu // Author: Weiyi Lu <weiyi.lu@mediatek.com> 5acddfc2cSWeiyi Lu 6acddfc2cSWeiyi Lu #include <linux/delay.h> 7acddfc2cSWeiyi Lu #include <linux/mfd/syscon.h> 8acddfc2cSWeiyi Lu #include <linux/of.h> 9acddfc2cSWeiyi Lu #include <linux/of_address.h> 10acddfc2cSWeiyi Lu #include <linux/of_device.h> 11acddfc2cSWeiyi Lu #include <linux/platform_device.h> 12acddfc2cSWeiyi Lu #include <linux/slab.h> 13acddfc2cSWeiyi Lu 14acddfc2cSWeiyi Lu #include "clk-mtk.h" 15acddfc2cSWeiyi Lu #include "clk-mux.h" 16acddfc2cSWeiyi Lu #include "clk-gate.h" 17acddfc2cSWeiyi Lu 18acddfc2cSWeiyi Lu #include <dt-bindings/clock/mt8183-clk.h> 19acddfc2cSWeiyi Lu 2064ebb57aSyong.liang /* Infra global controller reset set register */ 2164ebb57aSyong.liang #define INFRA_RST0_SET_OFFSET 0x120 2264ebb57aSyong.liang 23acddfc2cSWeiyi Lu static DEFINE_SPINLOCK(mt8183_clk_lock); 24acddfc2cSWeiyi Lu 25acddfc2cSWeiyi Lu static const struct mtk_fixed_clk top_fixed_clks[] = { 26acddfc2cSWeiyi Lu FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000), 27acddfc2cSWeiyi Lu FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000), 28acddfc2cSWeiyi Lu FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), 29acddfc2cSWeiyi Lu }; 30acddfc2cSWeiyi Lu 31c93d059aSWeiyi Lu static const struct mtk_fixed_factor top_early_divs[] = { 32c93d059aSWeiyi Lu FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), 33c93d059aSWeiyi Lu }; 34c93d059aSWeiyi Lu 35acddfc2cSWeiyi Lu static const struct mtk_fixed_factor top_divs[] = { 36acddfc2cSWeiyi Lu FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 37acddfc2cSWeiyi Lu 2), 38acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 39acddfc2cSWeiyi Lu 1), 40acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 41acddfc2cSWeiyi Lu 2), 42acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 43acddfc2cSWeiyi Lu 2), 44acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 45acddfc2cSWeiyi Lu 4), 46acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 47acddfc2cSWeiyi Lu 8), 48acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 49acddfc2cSWeiyi Lu 16), 50acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 51acddfc2cSWeiyi Lu 3), 52acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 53acddfc2cSWeiyi Lu 2), 54acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 55acddfc2cSWeiyi Lu 4), 56acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 57acddfc2cSWeiyi Lu 8), 58acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 59acddfc2cSWeiyi Lu 5), 60acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 61acddfc2cSWeiyi Lu 2), 62acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 63acddfc2cSWeiyi Lu 4), 64acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 65acddfc2cSWeiyi Lu 7), 66acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 67acddfc2cSWeiyi Lu 2), 68acddfc2cSWeiyi Lu FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 69acddfc2cSWeiyi Lu 4), 70acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 71acddfc2cSWeiyi Lu 1), 72acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 73acddfc2cSWeiyi Lu 2), 74acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 75acddfc2cSWeiyi Lu 2), 76acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 77acddfc2cSWeiyi Lu 4), 78acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 79acddfc2cSWeiyi Lu 8), 80acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 81acddfc2cSWeiyi Lu 3), 82acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 83acddfc2cSWeiyi Lu 2), 84acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 85acddfc2cSWeiyi Lu 4), 86acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 87acddfc2cSWeiyi Lu 8), 88acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 89acddfc2cSWeiyi Lu 5), 90acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 91acddfc2cSWeiyi Lu 2), 92acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 93acddfc2cSWeiyi Lu 4), 94acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 95acddfc2cSWeiyi Lu 8), 96acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 97acddfc2cSWeiyi Lu 7), 98acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 99acddfc2cSWeiyi Lu 1), 100acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 101acddfc2cSWeiyi Lu 2), 102acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 103acddfc2cSWeiyi Lu 4), 104acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 105acddfc2cSWeiyi Lu 8), 106acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 107acddfc2cSWeiyi Lu 16), 108acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 109acddfc2cSWeiyi Lu 32), 110acddfc2cSWeiyi Lu FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 111acddfc2cSWeiyi Lu 1), 112acddfc2cSWeiyi Lu FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 113acddfc2cSWeiyi Lu 2), 114acddfc2cSWeiyi Lu FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 115acddfc2cSWeiyi Lu 4), 116acddfc2cSWeiyi Lu FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 117acddfc2cSWeiyi Lu 8), 118acddfc2cSWeiyi Lu FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 119acddfc2cSWeiyi Lu 1), 120acddfc2cSWeiyi Lu FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 121acddfc2cSWeiyi Lu 2), 122acddfc2cSWeiyi Lu FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 123acddfc2cSWeiyi Lu 4), 124acddfc2cSWeiyi Lu FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 125acddfc2cSWeiyi Lu 8), 126acddfc2cSWeiyi Lu FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 127acddfc2cSWeiyi Lu 1), 128acddfc2cSWeiyi Lu FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 129acddfc2cSWeiyi Lu 2), 130acddfc2cSWeiyi Lu FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 131acddfc2cSWeiyi Lu 4), 132acddfc2cSWeiyi Lu FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 133acddfc2cSWeiyi Lu 8), 134acddfc2cSWeiyi Lu FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 135acddfc2cSWeiyi Lu 16), 136acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 137acddfc2cSWeiyi Lu 1), 138acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 139acddfc2cSWeiyi Lu 4), 140acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 141acddfc2cSWeiyi Lu 2), 142acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 143acddfc2cSWeiyi Lu 4), 144acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 145acddfc2cSWeiyi Lu 5), 146acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 147acddfc2cSWeiyi Lu 2), 148acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 149acddfc2cSWeiyi Lu 4), 150acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 151acddfc2cSWeiyi Lu 6), 152acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 153acddfc2cSWeiyi Lu 7), 154acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 155acddfc2cSWeiyi Lu 1), 156acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 157acddfc2cSWeiyi Lu 1), 158acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 159acddfc2cSWeiyi Lu 2), 160acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 161acddfc2cSWeiyi Lu 4), 162acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 163acddfc2cSWeiyi Lu 8), 164acddfc2cSWeiyi Lu FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 165acddfc2cSWeiyi Lu 16), 166acddfc2cSWeiyi Lu FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 167acddfc2cSWeiyi Lu 1), 168acddfc2cSWeiyi Lu FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 169acddfc2cSWeiyi Lu 2), 170acddfc2cSWeiyi Lu FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 171acddfc2cSWeiyi Lu 4), 172acddfc2cSWeiyi Lu FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 173acddfc2cSWeiyi Lu 8), 174acddfc2cSWeiyi Lu FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 175acddfc2cSWeiyi Lu 16), 176acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 177acddfc2cSWeiyi Lu 2), 178acddfc2cSWeiyi Lu FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 179acddfc2cSWeiyi Lu 16), 180acddfc2cSWeiyi Lu }; 181acddfc2cSWeiyi Lu 182acddfc2cSWeiyi Lu static const char * const axi_parents[] = { 183acddfc2cSWeiyi Lu "clk26m", 184acddfc2cSWeiyi Lu "syspll_d2_d4", 185acddfc2cSWeiyi Lu "syspll_d7", 186acddfc2cSWeiyi Lu "osc_d4" 187acddfc2cSWeiyi Lu }; 188acddfc2cSWeiyi Lu 189acddfc2cSWeiyi Lu static const char * const mm_parents[] = { 190acddfc2cSWeiyi Lu "clk26m", 191acddfc2cSWeiyi Lu "mmpll_d7", 192acddfc2cSWeiyi Lu "syspll_d3", 193acddfc2cSWeiyi Lu "univpll_d2_d2", 194acddfc2cSWeiyi Lu "syspll_d2_d2", 195acddfc2cSWeiyi Lu "syspll_d3_d2" 196acddfc2cSWeiyi Lu }; 197acddfc2cSWeiyi Lu 198acddfc2cSWeiyi Lu static const char * const img_parents[] = { 199acddfc2cSWeiyi Lu "clk26m", 200acddfc2cSWeiyi Lu "mmpll_d6", 201acddfc2cSWeiyi Lu "univpll_d3", 202acddfc2cSWeiyi Lu "syspll_d3", 203acddfc2cSWeiyi Lu "univpll_d2_d2", 204acddfc2cSWeiyi Lu "syspll_d2_d2", 205acddfc2cSWeiyi Lu "univpll_d3_d2", 206acddfc2cSWeiyi Lu "syspll_d3_d2" 207acddfc2cSWeiyi Lu }; 208acddfc2cSWeiyi Lu 209acddfc2cSWeiyi Lu static const char * const cam_parents[] = { 210acddfc2cSWeiyi Lu "clk26m", 211acddfc2cSWeiyi Lu "syspll_d2", 212acddfc2cSWeiyi Lu "mmpll_d6", 213acddfc2cSWeiyi Lu "syspll_d3", 214acddfc2cSWeiyi Lu "mmpll_d7", 215acddfc2cSWeiyi Lu "univpll_d3", 216acddfc2cSWeiyi Lu "univpll_d2_d2", 217acddfc2cSWeiyi Lu "syspll_d2_d2", 218acddfc2cSWeiyi Lu "syspll_d3_d2", 219acddfc2cSWeiyi Lu "univpll_d3_d2" 220acddfc2cSWeiyi Lu }; 221acddfc2cSWeiyi Lu 222acddfc2cSWeiyi Lu static const char * const dsp_parents[] = { 223acddfc2cSWeiyi Lu "clk26m", 224acddfc2cSWeiyi Lu "mmpll_d6", 225acddfc2cSWeiyi Lu "mmpll_d7", 226acddfc2cSWeiyi Lu "univpll_d3", 227acddfc2cSWeiyi Lu "syspll_d3", 228acddfc2cSWeiyi Lu "univpll_d2_d2", 229acddfc2cSWeiyi Lu "syspll_d2_d2", 230acddfc2cSWeiyi Lu "univpll_d3_d2", 231acddfc2cSWeiyi Lu "syspll_d3_d2" 232acddfc2cSWeiyi Lu }; 233acddfc2cSWeiyi Lu 234acddfc2cSWeiyi Lu static const char * const dsp1_parents[] = { 235acddfc2cSWeiyi Lu "clk26m", 236acddfc2cSWeiyi Lu "mmpll_d6", 237acddfc2cSWeiyi Lu "mmpll_d7", 238acddfc2cSWeiyi Lu "univpll_d3", 239acddfc2cSWeiyi Lu "syspll_d3", 240acddfc2cSWeiyi Lu "univpll_d2_d2", 241acddfc2cSWeiyi Lu "syspll_d2_d2", 242acddfc2cSWeiyi Lu "univpll_d3_d2", 243acddfc2cSWeiyi Lu "syspll_d3_d2" 244acddfc2cSWeiyi Lu }; 245acddfc2cSWeiyi Lu 246acddfc2cSWeiyi Lu static const char * const dsp2_parents[] = { 247acddfc2cSWeiyi Lu "clk26m", 248acddfc2cSWeiyi Lu "mmpll_d6", 249acddfc2cSWeiyi Lu "mmpll_d7", 250acddfc2cSWeiyi Lu "univpll_d3", 251acddfc2cSWeiyi Lu "syspll_d3", 252acddfc2cSWeiyi Lu "univpll_d2_d2", 253acddfc2cSWeiyi Lu "syspll_d2_d2", 254acddfc2cSWeiyi Lu "univpll_d3_d2", 255acddfc2cSWeiyi Lu "syspll_d3_d2" 256acddfc2cSWeiyi Lu }; 257acddfc2cSWeiyi Lu 258acddfc2cSWeiyi Lu static const char * const ipu_if_parents[] = { 259acddfc2cSWeiyi Lu "clk26m", 260acddfc2cSWeiyi Lu "mmpll_d6", 261acddfc2cSWeiyi Lu "mmpll_d7", 262acddfc2cSWeiyi Lu "univpll_d3", 263acddfc2cSWeiyi Lu "syspll_d3", 264acddfc2cSWeiyi Lu "univpll_d2_d2", 265acddfc2cSWeiyi Lu "syspll_d2_d2", 266acddfc2cSWeiyi Lu "univpll_d3_d2", 267acddfc2cSWeiyi Lu "syspll_d3_d2" 268acddfc2cSWeiyi Lu }; 269acddfc2cSWeiyi Lu 270acddfc2cSWeiyi Lu static const char * const mfg_parents[] = { 271acddfc2cSWeiyi Lu "clk26m", 272acddfc2cSWeiyi Lu "mfgpll_ck", 273acddfc2cSWeiyi Lu "univpll_d3", 274acddfc2cSWeiyi Lu "syspll_d3" 275acddfc2cSWeiyi Lu }; 276acddfc2cSWeiyi Lu 277acddfc2cSWeiyi Lu static const char * const f52m_mfg_parents[] = { 278acddfc2cSWeiyi Lu "clk26m", 279acddfc2cSWeiyi Lu "univpll_d3_d2", 280acddfc2cSWeiyi Lu "univpll_d3_d4", 281acddfc2cSWeiyi Lu "univpll_d3_d8" 282acddfc2cSWeiyi Lu }; 283acddfc2cSWeiyi Lu 284acddfc2cSWeiyi Lu static const char * const camtg_parents[] = { 285acddfc2cSWeiyi Lu "clk26m", 286acddfc2cSWeiyi Lu "univ_192m_d8", 287acddfc2cSWeiyi Lu "univpll_d3_d8", 288acddfc2cSWeiyi Lu "univ_192m_d4", 289acddfc2cSWeiyi Lu "univpll_d3_d16", 290acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 291acddfc2cSWeiyi Lu "univ_192m_d16", 292acddfc2cSWeiyi Lu "univ_192m_d32" 293acddfc2cSWeiyi Lu }; 294acddfc2cSWeiyi Lu 295acddfc2cSWeiyi Lu static const char * const camtg2_parents[] = { 296acddfc2cSWeiyi Lu "clk26m", 297acddfc2cSWeiyi Lu "univ_192m_d8", 298acddfc2cSWeiyi Lu "univpll_d3_d8", 299acddfc2cSWeiyi Lu "univ_192m_d4", 300acddfc2cSWeiyi Lu "univpll_d3_d16", 301acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 302acddfc2cSWeiyi Lu "univ_192m_d16", 303acddfc2cSWeiyi Lu "univ_192m_d32" 304acddfc2cSWeiyi Lu }; 305acddfc2cSWeiyi Lu 306acddfc2cSWeiyi Lu static const char * const camtg3_parents[] = { 307acddfc2cSWeiyi Lu "clk26m", 308acddfc2cSWeiyi Lu "univ_192m_d8", 309acddfc2cSWeiyi Lu "univpll_d3_d8", 310acddfc2cSWeiyi Lu "univ_192m_d4", 311acddfc2cSWeiyi Lu "univpll_d3_d16", 312acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 313acddfc2cSWeiyi Lu "univ_192m_d16", 314acddfc2cSWeiyi Lu "univ_192m_d32" 315acddfc2cSWeiyi Lu }; 316acddfc2cSWeiyi Lu 317acddfc2cSWeiyi Lu static const char * const camtg4_parents[] = { 318acddfc2cSWeiyi Lu "clk26m", 319acddfc2cSWeiyi Lu "univ_192m_d8", 320acddfc2cSWeiyi Lu "univpll_d3_d8", 321acddfc2cSWeiyi Lu "univ_192m_d4", 322acddfc2cSWeiyi Lu "univpll_d3_d16", 323acddfc2cSWeiyi Lu "csw_f26m_ck_d2", 324acddfc2cSWeiyi Lu "univ_192m_d16", 325acddfc2cSWeiyi Lu "univ_192m_d32" 326acddfc2cSWeiyi Lu }; 327acddfc2cSWeiyi Lu 328acddfc2cSWeiyi Lu static const char * const uart_parents[] = { 329acddfc2cSWeiyi Lu "clk26m", 330acddfc2cSWeiyi Lu "univpll_d3_d8" 331acddfc2cSWeiyi Lu }; 332acddfc2cSWeiyi Lu 333acddfc2cSWeiyi Lu static const char * const spi_parents[] = { 334acddfc2cSWeiyi Lu "clk26m", 335acddfc2cSWeiyi Lu "syspll_d5_d2", 336acddfc2cSWeiyi Lu "syspll_d3_d4", 337acddfc2cSWeiyi Lu "msdcpll_d4" 338acddfc2cSWeiyi Lu }; 339acddfc2cSWeiyi Lu 340acddfc2cSWeiyi Lu static const char * const msdc50_hclk_parents[] = { 341acddfc2cSWeiyi Lu "clk26m", 342acddfc2cSWeiyi Lu "syspll_d2_d2", 343acddfc2cSWeiyi Lu "syspll_d3_d2" 344acddfc2cSWeiyi Lu }; 345acddfc2cSWeiyi Lu 346acddfc2cSWeiyi Lu static const char * const msdc50_0_parents[] = { 347acddfc2cSWeiyi Lu "clk26m", 348acddfc2cSWeiyi Lu "msdcpll_ck", 349acddfc2cSWeiyi Lu "msdcpll_d2", 350acddfc2cSWeiyi Lu "univpll_d2_d4", 351acddfc2cSWeiyi Lu "syspll_d3_d2", 352acddfc2cSWeiyi Lu "univpll_d2_d2" 353acddfc2cSWeiyi Lu }; 354acddfc2cSWeiyi Lu 355acddfc2cSWeiyi Lu static const char * const msdc30_1_parents[] = { 356acddfc2cSWeiyi Lu "clk26m", 357acddfc2cSWeiyi Lu "univpll_d3_d2", 358acddfc2cSWeiyi Lu "syspll_d3_d2", 359acddfc2cSWeiyi Lu "syspll_d7", 360acddfc2cSWeiyi Lu "msdcpll_d2" 361acddfc2cSWeiyi Lu }; 362acddfc2cSWeiyi Lu 363acddfc2cSWeiyi Lu static const char * const msdc30_2_parents[] = { 364acddfc2cSWeiyi Lu "clk26m", 365acddfc2cSWeiyi Lu "univpll_d3_d2", 366acddfc2cSWeiyi Lu "syspll_d3_d2", 367acddfc2cSWeiyi Lu "syspll_d7", 368acddfc2cSWeiyi Lu "msdcpll_d2" 369acddfc2cSWeiyi Lu }; 370acddfc2cSWeiyi Lu 371acddfc2cSWeiyi Lu static const char * const audio_parents[] = { 372acddfc2cSWeiyi Lu "clk26m", 373acddfc2cSWeiyi Lu "syspll_d5_d4", 374acddfc2cSWeiyi Lu "syspll_d7_d4", 375acddfc2cSWeiyi Lu "syspll_d2_d16" 376acddfc2cSWeiyi Lu }; 377acddfc2cSWeiyi Lu 378acddfc2cSWeiyi Lu static const char * const aud_intbus_parents[] = { 379acddfc2cSWeiyi Lu "clk26m", 380acddfc2cSWeiyi Lu "syspll_d2_d4", 381acddfc2cSWeiyi Lu "syspll_d7_d2" 382acddfc2cSWeiyi Lu }; 383acddfc2cSWeiyi Lu 384acddfc2cSWeiyi Lu static const char * const pmicspi_parents[] = { 385acddfc2cSWeiyi Lu "clk26m", 386acddfc2cSWeiyi Lu "syspll_d2_d8", 387acddfc2cSWeiyi Lu "osc_d8" 388acddfc2cSWeiyi Lu }; 389acddfc2cSWeiyi Lu 390acddfc2cSWeiyi Lu static const char * const fpwrap_ulposc_parents[] = { 391acddfc2cSWeiyi Lu "clk26m", 392acddfc2cSWeiyi Lu "osc_d16", 393acddfc2cSWeiyi Lu "osc_d4", 394acddfc2cSWeiyi Lu "osc_d8" 395acddfc2cSWeiyi Lu }; 396acddfc2cSWeiyi Lu 397acddfc2cSWeiyi Lu static const char * const atb_parents[] = { 398acddfc2cSWeiyi Lu "clk26m", 399acddfc2cSWeiyi Lu "syspll_d2_d2", 400acddfc2cSWeiyi Lu "syspll_d5" 401acddfc2cSWeiyi Lu }; 402acddfc2cSWeiyi Lu 403acddfc2cSWeiyi Lu static const char * const dpi0_parents[] = { 404acddfc2cSWeiyi Lu "clk26m", 405acddfc2cSWeiyi Lu "tvdpll_d2", 406acddfc2cSWeiyi Lu "tvdpll_d4", 407acddfc2cSWeiyi Lu "tvdpll_d8", 408acddfc2cSWeiyi Lu "tvdpll_d16", 409acddfc2cSWeiyi Lu "univpll_d5_d2", 410acddfc2cSWeiyi Lu "univpll_d3_d4", 411acddfc2cSWeiyi Lu "syspll_d3_d4", 412acddfc2cSWeiyi Lu "univpll_d3_d8" 413acddfc2cSWeiyi Lu }; 414acddfc2cSWeiyi Lu 415acddfc2cSWeiyi Lu static const char * const scam_parents[] = { 416acddfc2cSWeiyi Lu "clk26m", 417acddfc2cSWeiyi Lu "syspll_d5_d2" 418acddfc2cSWeiyi Lu }; 419acddfc2cSWeiyi Lu 420acddfc2cSWeiyi Lu static const char * const disppwm_parents[] = { 421acddfc2cSWeiyi Lu "clk26m", 422acddfc2cSWeiyi Lu "univpll_d3_d4", 423acddfc2cSWeiyi Lu "osc_d2", 424acddfc2cSWeiyi Lu "osc_d4", 425acddfc2cSWeiyi Lu "osc_d16" 426acddfc2cSWeiyi Lu }; 427acddfc2cSWeiyi Lu 428acddfc2cSWeiyi Lu static const char * const usb_top_parents[] = { 429acddfc2cSWeiyi Lu "clk26m", 430acddfc2cSWeiyi Lu "univpll_d5_d4", 431acddfc2cSWeiyi Lu "univpll_d3_d4", 432acddfc2cSWeiyi Lu "univpll_d5_d2" 433acddfc2cSWeiyi Lu }; 434acddfc2cSWeiyi Lu 435acddfc2cSWeiyi Lu 436acddfc2cSWeiyi Lu static const char * const ssusb_top_xhci_parents[] = { 437acddfc2cSWeiyi Lu "clk26m", 438acddfc2cSWeiyi Lu "univpll_d5_d4", 439acddfc2cSWeiyi Lu "univpll_d3_d4", 440acddfc2cSWeiyi Lu "univpll_d5_d2" 441acddfc2cSWeiyi Lu }; 442acddfc2cSWeiyi Lu 443acddfc2cSWeiyi Lu static const char * const spm_parents[] = { 444acddfc2cSWeiyi Lu "clk26m", 445acddfc2cSWeiyi Lu "syspll_d2_d8" 446acddfc2cSWeiyi Lu }; 447acddfc2cSWeiyi Lu 448acddfc2cSWeiyi Lu static const char * const i2c_parents[] = { 449acddfc2cSWeiyi Lu "clk26m", 450acddfc2cSWeiyi Lu "syspll_d2_d8", 451acddfc2cSWeiyi Lu "univpll_d5_d2" 452acddfc2cSWeiyi Lu }; 453acddfc2cSWeiyi Lu 454acddfc2cSWeiyi Lu static const char * const scp_parents[] = { 455acddfc2cSWeiyi Lu "clk26m", 456acddfc2cSWeiyi Lu "univpll_d2_d8", 457acddfc2cSWeiyi Lu "syspll_d5", 458acddfc2cSWeiyi Lu "syspll_d2_d2", 459acddfc2cSWeiyi Lu "univpll_d2_d2", 460acddfc2cSWeiyi Lu "syspll_d3", 461acddfc2cSWeiyi Lu "univpll_d3" 462acddfc2cSWeiyi Lu }; 463acddfc2cSWeiyi Lu 464acddfc2cSWeiyi Lu static const char * const seninf_parents[] = { 465acddfc2cSWeiyi Lu "clk26m", 466acddfc2cSWeiyi Lu "univpll_d2_d2", 467acddfc2cSWeiyi Lu "univpll_d3_d2", 468acddfc2cSWeiyi Lu "univpll_d2_d4" 469acddfc2cSWeiyi Lu }; 470acddfc2cSWeiyi Lu 471acddfc2cSWeiyi Lu static const char * const dxcc_parents[] = { 472acddfc2cSWeiyi Lu "clk26m", 473acddfc2cSWeiyi Lu "syspll_d2_d2", 474acddfc2cSWeiyi Lu "syspll_d2_d4", 475acddfc2cSWeiyi Lu "syspll_d2_d8" 476acddfc2cSWeiyi Lu }; 477acddfc2cSWeiyi Lu 478acddfc2cSWeiyi Lu static const char * const aud_engen1_parents[] = { 479acddfc2cSWeiyi Lu "clk26m", 480acddfc2cSWeiyi Lu "apll1_d2", 481acddfc2cSWeiyi Lu "apll1_d4", 482acddfc2cSWeiyi Lu "apll1_d8" 483acddfc2cSWeiyi Lu }; 484acddfc2cSWeiyi Lu 485acddfc2cSWeiyi Lu static const char * const aud_engen2_parents[] = { 486acddfc2cSWeiyi Lu "clk26m", 487acddfc2cSWeiyi Lu "apll2_d2", 488acddfc2cSWeiyi Lu "apll2_d4", 489acddfc2cSWeiyi Lu "apll2_d8" 490acddfc2cSWeiyi Lu }; 491acddfc2cSWeiyi Lu 492acddfc2cSWeiyi Lu static const char * const faes_ufsfde_parents[] = { 493acddfc2cSWeiyi Lu "clk26m", 494acddfc2cSWeiyi Lu "syspll_d2", 495acddfc2cSWeiyi Lu "syspll_d2_d2", 496acddfc2cSWeiyi Lu "syspll_d3", 497acddfc2cSWeiyi Lu "syspll_d2_d4", 498acddfc2cSWeiyi Lu "univpll_d3" 499acddfc2cSWeiyi Lu }; 500acddfc2cSWeiyi Lu 501acddfc2cSWeiyi Lu static const char * const fufs_parents[] = { 502acddfc2cSWeiyi Lu "clk26m", 503acddfc2cSWeiyi Lu "syspll_d2_d4", 504acddfc2cSWeiyi Lu "syspll_d2_d8", 505acddfc2cSWeiyi Lu "syspll_d2_d16" 506acddfc2cSWeiyi Lu }; 507acddfc2cSWeiyi Lu 508acddfc2cSWeiyi Lu static const char * const aud_1_parents[] = { 509acddfc2cSWeiyi Lu "clk26m", 510acddfc2cSWeiyi Lu "apll1_ck" 511acddfc2cSWeiyi Lu }; 512acddfc2cSWeiyi Lu 513acddfc2cSWeiyi Lu static const char * const aud_2_parents[] = { 514acddfc2cSWeiyi Lu "clk26m", 515acddfc2cSWeiyi Lu "apll2_ck" 516acddfc2cSWeiyi Lu }; 517acddfc2cSWeiyi Lu 518acddfc2cSWeiyi Lu /* 519acddfc2cSWeiyi Lu * CRITICAL CLOCK: 520acddfc2cSWeiyi Lu * axi_sel is the main bus clock of whole SOC. 521acddfc2cSWeiyi Lu * spm_sel is the clock of the always-on co-processor. 522acddfc2cSWeiyi Lu */ 523acddfc2cSWeiyi Lu static const struct mtk_mux top_muxes[] = { 524acddfc2cSWeiyi Lu /* CLK_CFG_0 */ 525acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", 526acddfc2cSWeiyi Lu axi_parents, 0x40, 527acddfc2cSWeiyi Lu 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), 528acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", 529acddfc2cSWeiyi Lu mm_parents, 0x40, 530acddfc2cSWeiyi Lu 0x44, 0x48, 8, 3, 15, 0x004, 1), 531acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", 532acddfc2cSWeiyi Lu img_parents, 0x40, 533acddfc2cSWeiyi Lu 0x44, 0x48, 16, 3, 23, 0x004, 2), 534acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", 535acddfc2cSWeiyi Lu cam_parents, 0x40, 536acddfc2cSWeiyi Lu 0x44, 0x48, 24, 4, 31, 0x004, 3), 537acddfc2cSWeiyi Lu /* CLK_CFG_1 */ 538acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", 539acddfc2cSWeiyi Lu dsp_parents, 0x50, 540acddfc2cSWeiyi Lu 0x54, 0x58, 0, 4, 7, 0x004, 4), 541acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", 542acddfc2cSWeiyi Lu dsp1_parents, 0x50, 543acddfc2cSWeiyi Lu 0x54, 0x58, 8, 4, 15, 0x004, 5), 544acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", 545acddfc2cSWeiyi Lu dsp2_parents, 0x50, 546acddfc2cSWeiyi Lu 0x54, 0x58, 16, 4, 23, 0x004, 6), 547acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", 548acddfc2cSWeiyi Lu ipu_if_parents, 0x50, 549acddfc2cSWeiyi Lu 0x54, 0x58, 24, 4, 31, 0x004, 7), 550acddfc2cSWeiyi Lu /* CLK_CFG_2 */ 551acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", 552acddfc2cSWeiyi Lu mfg_parents, 0x60, 553acddfc2cSWeiyi Lu 0x64, 0x68, 0, 2, 7, 0x004, 8), 554acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", 555acddfc2cSWeiyi Lu f52m_mfg_parents, 0x60, 556acddfc2cSWeiyi Lu 0x64, 0x68, 8, 2, 15, 0x004, 9), 557acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", 558acddfc2cSWeiyi Lu camtg_parents, 0x60, 559acddfc2cSWeiyi Lu 0x64, 0x68, 16, 3, 23, 0x004, 10), 560acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", 561acddfc2cSWeiyi Lu camtg2_parents, 0x60, 562acddfc2cSWeiyi Lu 0x64, 0x68, 24, 3, 31, 0x004, 11), 563acddfc2cSWeiyi Lu /* CLK_CFG_3 */ 564acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", 565acddfc2cSWeiyi Lu camtg3_parents, 0x70, 566acddfc2cSWeiyi Lu 0x74, 0x78, 0, 3, 7, 0x004, 12), 567acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", 568acddfc2cSWeiyi Lu camtg4_parents, 0x70, 569acddfc2cSWeiyi Lu 0x74, 0x78, 8, 3, 15, 0x004, 13), 570acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", 571acddfc2cSWeiyi Lu uart_parents, 0x70, 572acddfc2cSWeiyi Lu 0x74, 0x78, 16, 1, 23, 0x004, 14), 573acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", 574acddfc2cSWeiyi Lu spi_parents, 0x70, 575acddfc2cSWeiyi Lu 0x74, 0x78, 24, 2, 31, 0x004, 15), 576acddfc2cSWeiyi Lu /* CLK_CFG_4 */ 577acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", 578acddfc2cSWeiyi Lu msdc50_hclk_parents, 0x80, 579acddfc2cSWeiyi Lu 0x84, 0x88, 0, 2, 7, 0x004, 16), 580acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", 581acddfc2cSWeiyi Lu msdc50_0_parents, 0x80, 582acddfc2cSWeiyi Lu 0x84, 0x88, 8, 3, 15, 0x004, 17), 583acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", 584acddfc2cSWeiyi Lu msdc30_1_parents, 0x80, 585acddfc2cSWeiyi Lu 0x84, 0x88, 16, 3, 23, 0x004, 18), 586acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", 587acddfc2cSWeiyi Lu msdc30_2_parents, 0x80, 588acddfc2cSWeiyi Lu 0x84, 0x88, 24, 3, 31, 0x004, 19), 589acddfc2cSWeiyi Lu /* CLK_CFG_5 */ 590acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", 591acddfc2cSWeiyi Lu audio_parents, 0x90, 592acddfc2cSWeiyi Lu 0x94, 0x98, 0, 2, 7, 0x004, 20), 593acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", 594acddfc2cSWeiyi Lu aud_intbus_parents, 0x90, 595acddfc2cSWeiyi Lu 0x94, 0x98, 8, 2, 15, 0x004, 21), 596acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", 597acddfc2cSWeiyi Lu pmicspi_parents, 0x90, 598acddfc2cSWeiyi Lu 0x94, 0x98, 16, 2, 23, 0x004, 22), 599acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", 600acddfc2cSWeiyi Lu fpwrap_ulposc_parents, 0x90, 601acddfc2cSWeiyi Lu 0x94, 0x98, 24, 2, 31, 0x004, 23), 602acddfc2cSWeiyi Lu /* CLK_CFG_6 */ 603acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", 604acddfc2cSWeiyi Lu atb_parents, 0xa0, 605acddfc2cSWeiyi Lu 0xa4, 0xa8, 0, 2, 7, 0x004, 24), 606acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", 607acddfc2cSWeiyi Lu dpi0_parents, 0xa0, 608acddfc2cSWeiyi Lu 0xa4, 0xa8, 16, 4, 23, 0x004, 26), 609acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", 610acddfc2cSWeiyi Lu scam_parents, 0xa0, 611acddfc2cSWeiyi Lu 0xa4, 0xa8, 24, 1, 31, 0x004, 27), 612acddfc2cSWeiyi Lu /* CLK_CFG_7 */ 613acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", 614acddfc2cSWeiyi Lu disppwm_parents, 0xb0, 615acddfc2cSWeiyi Lu 0xb4, 0xb8, 0, 3, 7, 0x004, 28), 616acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", 617acddfc2cSWeiyi Lu usb_top_parents, 0xb0, 618acddfc2cSWeiyi Lu 0xb4, 0xb8, 8, 2, 15, 0x004, 29), 619acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", 620acddfc2cSWeiyi Lu ssusb_top_xhci_parents, 0xb0, 621acddfc2cSWeiyi Lu 0xb4, 0xb8, 16, 2, 23, 0x004, 30), 622acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", 623acddfc2cSWeiyi Lu spm_parents, 0xb0, 624acddfc2cSWeiyi Lu 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), 625acddfc2cSWeiyi Lu /* CLK_CFG_8 */ 626acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", 627acddfc2cSWeiyi Lu i2c_parents, 0xc0, 628acddfc2cSWeiyi Lu 0xc4, 0xc8, 0, 2, 7, 0x008, 1), 629acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", 630acddfc2cSWeiyi Lu scp_parents, 0xc0, 631acddfc2cSWeiyi Lu 0xc4, 0xc8, 8, 3, 15, 0x008, 2), 632acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", 633acddfc2cSWeiyi Lu seninf_parents, 0xc0, 634acddfc2cSWeiyi Lu 0xc4, 0xc8, 16, 2, 23, 0x008, 3), 635acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", 636acddfc2cSWeiyi Lu dxcc_parents, 0xc0, 637acddfc2cSWeiyi Lu 0xc4, 0xc8, 24, 2, 31, 0x008, 4), 638acddfc2cSWeiyi Lu /* CLK_CFG_9 */ 639acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", 640acddfc2cSWeiyi Lu aud_engen1_parents, 0xd0, 641acddfc2cSWeiyi Lu 0xd4, 0xd8, 0, 2, 7, 0x008, 5), 642acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", 643acddfc2cSWeiyi Lu aud_engen2_parents, 0xd0, 644acddfc2cSWeiyi Lu 0xd4, 0xd8, 8, 2, 15, 0x008, 6), 645acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", 646acddfc2cSWeiyi Lu faes_ufsfde_parents, 0xd0, 647acddfc2cSWeiyi Lu 0xd4, 0xd8, 16, 3, 23, 0x008, 7), 648acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", 649acddfc2cSWeiyi Lu fufs_parents, 0xd0, 650acddfc2cSWeiyi Lu 0xd4, 0xd8, 24, 2, 31, 0x008, 8), 651acddfc2cSWeiyi Lu /* CLK_CFG_10 */ 652acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", 653acddfc2cSWeiyi Lu aud_1_parents, 0xe0, 654acddfc2cSWeiyi Lu 0xe4, 0xe8, 0, 1, 7, 0x008, 9), 655acddfc2cSWeiyi Lu MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", 656acddfc2cSWeiyi Lu aud_2_parents, 0xe0, 657acddfc2cSWeiyi Lu 0xe4, 0xe8, 8, 1, 15, 0x008, 10), 658acddfc2cSWeiyi Lu }; 659acddfc2cSWeiyi Lu 660acddfc2cSWeiyi Lu static const char * const apll_i2s0_parents[] = { 661acddfc2cSWeiyi Lu "aud_1_sel", 662acddfc2cSWeiyi Lu "aud_2_sel" 663acddfc2cSWeiyi Lu }; 664acddfc2cSWeiyi Lu 665acddfc2cSWeiyi Lu static const char * const apll_i2s1_parents[] = { 666acddfc2cSWeiyi Lu "aud_1_sel", 667acddfc2cSWeiyi Lu "aud_2_sel" 668acddfc2cSWeiyi Lu }; 669acddfc2cSWeiyi Lu 670acddfc2cSWeiyi Lu static const char * const apll_i2s2_parents[] = { 671acddfc2cSWeiyi Lu "aud_1_sel", 672acddfc2cSWeiyi Lu "aud_2_sel" 673acddfc2cSWeiyi Lu }; 674acddfc2cSWeiyi Lu 675acddfc2cSWeiyi Lu static const char * const apll_i2s3_parents[] = { 676acddfc2cSWeiyi Lu "aud_1_sel", 677acddfc2cSWeiyi Lu "aud_2_sel" 678acddfc2cSWeiyi Lu }; 679acddfc2cSWeiyi Lu 680acddfc2cSWeiyi Lu static const char * const apll_i2s4_parents[] = { 681acddfc2cSWeiyi Lu "aud_1_sel", 682acddfc2cSWeiyi Lu "aud_2_sel" 683acddfc2cSWeiyi Lu }; 684acddfc2cSWeiyi Lu 685acddfc2cSWeiyi Lu static const char * const apll_i2s5_parents[] = { 686acddfc2cSWeiyi Lu "aud_1_sel", 687acddfc2cSWeiyi Lu "aud_2_sel" 688acddfc2cSWeiyi Lu }; 689acddfc2cSWeiyi Lu 690acddfc2cSWeiyi Lu static struct mtk_composite top_aud_muxes[] = { 691acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 692acddfc2cSWeiyi Lu 0x320, 8, 1), 693acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 694acddfc2cSWeiyi Lu 0x320, 9, 1), 695acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 696acddfc2cSWeiyi Lu 0x320, 10, 1), 697acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 698acddfc2cSWeiyi Lu 0x320, 11, 1), 699acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 700acddfc2cSWeiyi Lu 0x320, 12, 1), 701acddfc2cSWeiyi Lu MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 702acddfc2cSWeiyi Lu 0x328, 20, 1), 703acddfc2cSWeiyi Lu }; 704acddfc2cSWeiyi Lu 705acddfc2cSWeiyi Lu static const char * const mcu_mp0_parents[] = { 706acddfc2cSWeiyi Lu "clk26m", 707acddfc2cSWeiyi Lu "armpll_ll", 708acddfc2cSWeiyi Lu "armpll_div_pll1", 709acddfc2cSWeiyi Lu "armpll_div_pll2" 710acddfc2cSWeiyi Lu }; 711acddfc2cSWeiyi Lu 712acddfc2cSWeiyi Lu static const char * const mcu_mp2_parents[] = { 713acddfc2cSWeiyi Lu "clk26m", 714acddfc2cSWeiyi Lu "armpll_l", 715acddfc2cSWeiyi Lu "armpll_div_pll1", 716acddfc2cSWeiyi Lu "armpll_div_pll2" 717acddfc2cSWeiyi Lu }; 718acddfc2cSWeiyi Lu 719acddfc2cSWeiyi Lu static const char * const mcu_bus_parents[] = { 720acddfc2cSWeiyi Lu "clk26m", 721acddfc2cSWeiyi Lu "ccipll", 722acddfc2cSWeiyi Lu "armpll_div_pll1", 723acddfc2cSWeiyi Lu "armpll_div_pll2" 724acddfc2cSWeiyi Lu }; 725acddfc2cSWeiyi Lu 726acddfc2cSWeiyi Lu static struct mtk_composite mcu_muxes[] = { 727acddfc2cSWeiyi Lu /* mp0_pll_divider_cfg */ 728acddfc2cSWeiyi Lu MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2), 729acddfc2cSWeiyi Lu /* mp2_pll_divider_cfg */ 730acddfc2cSWeiyi Lu MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2), 731acddfc2cSWeiyi Lu /* bus_pll_divider_cfg */ 732acddfc2cSWeiyi Lu MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), 733acddfc2cSWeiyi Lu }; 734acddfc2cSWeiyi Lu 735acddfc2cSWeiyi Lu static struct mtk_composite top_aud_divs[] = { 736acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 737acddfc2cSWeiyi Lu 0x320, 2, 0x324, 8, 0), 738acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 739acddfc2cSWeiyi Lu 0x320, 3, 0x324, 8, 8), 740acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 741acddfc2cSWeiyi Lu 0x320, 4, 0x324, 8, 16), 742acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 743acddfc2cSWeiyi Lu 0x320, 5, 0x324, 8, 24), 744acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 745acddfc2cSWeiyi Lu 0x320, 6, 0x328, 8, 0), 746acddfc2cSWeiyi Lu DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 747acddfc2cSWeiyi Lu 0x320, 7, 0x328, 8, 8), 748acddfc2cSWeiyi Lu }; 749acddfc2cSWeiyi Lu 750acddfc2cSWeiyi Lu static const struct mtk_gate_regs top_cg_regs = { 751acddfc2cSWeiyi Lu .set_ofs = 0x104, 752acddfc2cSWeiyi Lu .clr_ofs = 0x104, 753acddfc2cSWeiyi Lu .sta_ofs = 0x104, 754acddfc2cSWeiyi Lu }; 755acddfc2cSWeiyi Lu 756acddfc2cSWeiyi Lu #define GATE_TOP(_id, _name, _parent, _shift) \ 757acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \ 758acddfc2cSWeiyi Lu &mtk_clk_gate_ops_no_setclr_inv) 759acddfc2cSWeiyi Lu 760acddfc2cSWeiyi Lu static const struct mtk_gate top_clks[] = { 761acddfc2cSWeiyi Lu /* TOP */ 762acddfc2cSWeiyi Lu GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4), 763acddfc2cSWeiyi Lu GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5), 764acddfc2cSWeiyi Lu }; 765acddfc2cSWeiyi Lu 766acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra0_cg_regs = { 767acddfc2cSWeiyi Lu .set_ofs = 0x80, 768acddfc2cSWeiyi Lu .clr_ofs = 0x84, 769acddfc2cSWeiyi Lu .sta_ofs = 0x90, 770acddfc2cSWeiyi Lu }; 771acddfc2cSWeiyi Lu 772acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra1_cg_regs = { 773acddfc2cSWeiyi Lu .set_ofs = 0x88, 774acddfc2cSWeiyi Lu .clr_ofs = 0x8c, 775acddfc2cSWeiyi Lu .sta_ofs = 0x94, 776acddfc2cSWeiyi Lu }; 777acddfc2cSWeiyi Lu 778acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra2_cg_regs = { 779acddfc2cSWeiyi Lu .set_ofs = 0xa4, 780acddfc2cSWeiyi Lu .clr_ofs = 0xa8, 781acddfc2cSWeiyi Lu .sta_ofs = 0xac, 782acddfc2cSWeiyi Lu }; 783acddfc2cSWeiyi Lu 784acddfc2cSWeiyi Lu static const struct mtk_gate_regs infra3_cg_regs = { 785acddfc2cSWeiyi Lu .set_ofs = 0xc0, 786acddfc2cSWeiyi Lu .clr_ofs = 0xc4, 787acddfc2cSWeiyi Lu .sta_ofs = 0xc8, 788acddfc2cSWeiyi Lu }; 789acddfc2cSWeiyi Lu 790acddfc2cSWeiyi Lu #define GATE_INFRA0(_id, _name, _parent, _shift) \ 791acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \ 792acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 793acddfc2cSWeiyi Lu 794acddfc2cSWeiyi Lu #define GATE_INFRA1(_id, _name, _parent, _shift) \ 795acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \ 796acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 797acddfc2cSWeiyi Lu 798acddfc2cSWeiyi Lu #define GATE_INFRA2(_id, _name, _parent, _shift) \ 799acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \ 800acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 801acddfc2cSWeiyi Lu 802acddfc2cSWeiyi Lu #define GATE_INFRA3(_id, _name, _parent, _shift) \ 803acddfc2cSWeiyi Lu GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \ 804acddfc2cSWeiyi Lu &mtk_clk_gate_ops_setclr) 805acddfc2cSWeiyi Lu 806acddfc2cSWeiyi Lu static const struct mtk_gate infra_clks[] = { 807acddfc2cSWeiyi Lu /* INFRA0 */ 808acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", 809acddfc2cSWeiyi Lu "axi_sel", 0), 810acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", 811acddfc2cSWeiyi Lu "axi_sel", 1), 812acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", 813acddfc2cSWeiyi Lu "axi_sel", 2), 814acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", 815acddfc2cSWeiyi Lu "axi_sel", 3), 816acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", 817acddfc2cSWeiyi Lu "scp_sel", 4), 818acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", 819acddfc2cSWeiyi Lu "f_f26m_ck", 5), 820acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", 821acddfc2cSWeiyi Lu "axi_sel", 6), 822acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", 823acddfc2cSWeiyi Lu "axi_sel", 8), 824acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", 825acddfc2cSWeiyi Lu "axi_sel", 9), 826acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", 827acddfc2cSWeiyi Lu "axi_sel", 10), 828acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", 829acddfc2cSWeiyi Lu "i2c_sel", 11), 830acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", 831acddfc2cSWeiyi Lu "i2c_sel", 12), 832acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", 833acddfc2cSWeiyi Lu "i2c_sel", 13), 834acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", 835acddfc2cSWeiyi Lu "i2c_sel", 14), 836acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", 837acddfc2cSWeiyi Lu "axi_sel", 15), 838acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", 839acddfc2cSWeiyi Lu "i2c_sel", 16), 840acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", 841acddfc2cSWeiyi Lu "i2c_sel", 17), 842acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", 843acddfc2cSWeiyi Lu "i2c_sel", 18), 844acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", 845acddfc2cSWeiyi Lu "i2c_sel", 19), 846acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", 847acddfc2cSWeiyi Lu "i2c_sel", 21), 848acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", 849acddfc2cSWeiyi Lu "uart_sel", 22), 850acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", 851acddfc2cSWeiyi Lu "uart_sel", 23), 852acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", 853acddfc2cSWeiyi Lu "uart_sel", 24), 854acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", 855acddfc2cSWeiyi Lu "uart_sel", 25), 856acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", 857acddfc2cSWeiyi Lu "axi_sel", 27), 858acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", 859acddfc2cSWeiyi Lu "axi_sel", 28), 860acddfc2cSWeiyi Lu GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", 861acddfc2cSWeiyi Lu "axi_sel", 31), 862acddfc2cSWeiyi Lu /* INFRA1 */ 863acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", 864acddfc2cSWeiyi Lu "spi_sel", 1), 865acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", 866acddfc2cSWeiyi Lu "msdc50_hclk_sel", 2), 867acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", 868acddfc2cSWeiyi Lu "axi_sel", 4), 869acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", 870acddfc2cSWeiyi Lu "axi_sel", 5), 871acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", 872acddfc2cSWeiyi Lu "msdc50_0_sel", 6), 873acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", 874acddfc2cSWeiyi Lu "f_f26m_ck", 7), 875acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", 876acddfc2cSWeiyi Lu "axi_sel", 8), 877acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", 878acddfc2cSWeiyi Lu "axi_sel", 9), 879acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", 880acddfc2cSWeiyi Lu "f_f26m_ck", 10), 881acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", 882acddfc2cSWeiyi Lu "axi_sel", 11), 883acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", 884acddfc2cSWeiyi Lu "axi_sel", 12), 885acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", 886acddfc2cSWeiyi Lu "axi_sel", 13), 887acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", 888acddfc2cSWeiyi Lu "f_f26m_ck", 14), 889acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", 890acddfc2cSWeiyi Lu "msdc30_1_sel", 16), 891acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", 892acddfc2cSWeiyi Lu "msdc30_2_sel", 17), 893acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", 894acddfc2cSWeiyi Lu "axi_sel", 18), 895acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", 896acddfc2cSWeiyi Lu "axi_sel", 19), 897acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", 898acddfc2cSWeiyi Lu "axi_sel", 20), 899acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", 900acddfc2cSWeiyi Lu "axi_sel", 23), 901acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", 902acddfc2cSWeiyi Lu "axi_sel", 24), 903acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", 904acddfc2cSWeiyi Lu "axi_sel", 25), 905acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", 906acddfc2cSWeiyi Lu "axi_sel", 26), 907acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", 908acddfc2cSWeiyi Lu "dxcc_sel", 27), 909acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", 910acddfc2cSWeiyi Lu "dxcc_sel", 28), 911acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", 912acddfc2cSWeiyi Lu "axi_sel", 30), 913acddfc2cSWeiyi Lu GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", 914acddfc2cSWeiyi Lu "f_f26m_ck", 31), 915acddfc2cSWeiyi Lu /* INFRA2 */ 916acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", 917acddfc2cSWeiyi Lu "f_f26m_ck", 0), 918acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_USB, "infra_usb", 919acddfc2cSWeiyi Lu "usb_top_sel", 1), 920acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", 921acddfc2cSWeiyi Lu "axi_sel", 2), 922acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", 923acddfc2cSWeiyi Lu "axi_sel", 3), 924acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", 925acddfc2cSWeiyi Lu "f_f26m_ck", 4), 926acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", 927acddfc2cSWeiyi Lu "spi_sel", 6), 928acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", 929acddfc2cSWeiyi Lu "i2c_sel", 7), 930acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", 931acddfc2cSWeiyi Lu "f_f26m_ck", 8), 932acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", 933acddfc2cSWeiyi Lu "spi_sel", 9), 934acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", 935acddfc2cSWeiyi Lu "spi_sel", 10), 936acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", 937acddfc2cSWeiyi Lu "ssusb_top_xhci_sel", 11), 938acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", 939acddfc2cSWeiyi Lu "fufs_sel", 12), 940acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", 941acddfc2cSWeiyi Lu "fufs_sel", 13), 942acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", 943acddfc2cSWeiyi Lu "axi_sel", 14), 944acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", 945acddfc2cSWeiyi Lu "axi_sel", 16), 946acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", 947acddfc2cSWeiyi Lu "i2c_sel", 18), 948acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", 949acddfc2cSWeiyi Lu "i2c_sel", 19), 950acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", 951acddfc2cSWeiyi Lu "i2c_sel", 20), 952acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", 953acddfc2cSWeiyi Lu "i2c_sel", 21), 954acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", 955acddfc2cSWeiyi Lu "i2c_sel", 22), 956acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", 957acddfc2cSWeiyi Lu "i2c_sel", 23), 958acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", 959acddfc2cSWeiyi Lu "i2c_sel", 24), 960acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", 961acddfc2cSWeiyi Lu "spi_sel", 25), 962acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", 963acddfc2cSWeiyi Lu "spi_sel", 26), 964acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", 965acddfc2cSWeiyi Lu "axi_sel", 27), 966acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", 967acddfc2cSWeiyi Lu "fufs_sel", 28), 968acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", 969acddfc2cSWeiyi Lu "faes_ufsfde_sel", 29), 970acddfc2cSWeiyi Lu GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", 971acddfc2cSWeiyi Lu "fufs_sel", 30), 972acddfc2cSWeiyi Lu /* INFRA3 */ 973acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", 974acddfc2cSWeiyi Lu "msdc50_0_sel", 0), 975acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", 976acddfc2cSWeiyi Lu "msdc50_0_sel", 1), 977acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", 978acddfc2cSWeiyi Lu "msdc50_0_sel", 2), 979acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", 980acddfc2cSWeiyi Lu "axi_sel", 5), 981acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", 982acddfc2cSWeiyi Lu "i2c_sel", 6), 983acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", 984acddfc2cSWeiyi Lu "msdc50_hclk_sel", 7), 985acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", 986acddfc2cSWeiyi Lu "msdc50_hclk_sel", 8), 987acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", 988acddfc2cSWeiyi Lu "axi_sel", 16), 989acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", 990acddfc2cSWeiyi Lu "axi_sel", 17), 991acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", 992acddfc2cSWeiyi Lu "axi_sel", 18), 993acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", 994acddfc2cSWeiyi Lu "axi_sel", 19), 995acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", 996acddfc2cSWeiyi Lu "f_f26m_ck", 20), 997acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", 998acddfc2cSWeiyi Lu "axi_sel", 21), 999acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", 1000acddfc2cSWeiyi Lu "i2c_sel", 22), 1001acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", 1002acddfc2cSWeiyi Lu "i2c_sel", 23), 1003acddfc2cSWeiyi Lu GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", 1004acddfc2cSWeiyi Lu "msdc50_0_sel", 24), 1005acddfc2cSWeiyi Lu }; 1006acddfc2cSWeiyi Lu 1007f9e55ac2SChunfeng Yun static const struct mtk_gate_regs peri_cg_regs = { 1008f9e55ac2SChunfeng Yun .set_ofs = 0x20c, 1009f9e55ac2SChunfeng Yun .clr_ofs = 0x20c, 1010f9e55ac2SChunfeng Yun .sta_ofs = 0x20c, 1011f9e55ac2SChunfeng Yun }; 1012f9e55ac2SChunfeng Yun 1013f9e55ac2SChunfeng Yun #define GATE_PERI(_id, _name, _parent, _shift) \ 1014f9e55ac2SChunfeng Yun GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ 1015f9e55ac2SChunfeng Yun &mtk_clk_gate_ops_no_setclr_inv) 1016f9e55ac2SChunfeng Yun 1017f9e55ac2SChunfeng Yun static const struct mtk_gate peri_clks[] = { 1018f9e55ac2SChunfeng Yun GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), 1019f9e55ac2SChunfeng Yun }; 1020f9e55ac2SChunfeng Yun 1021acddfc2cSWeiyi Lu static const struct mtk_gate_regs apmixed_cg_regs = { 1022acddfc2cSWeiyi Lu .set_ofs = 0x20, 1023acddfc2cSWeiyi Lu .clr_ofs = 0x20, 1024acddfc2cSWeiyi Lu .sta_ofs = 0x20, 1025acddfc2cSWeiyi Lu }; 1026acddfc2cSWeiyi Lu 1027acddfc2cSWeiyi Lu #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ 1028acddfc2cSWeiyi Lu GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ 1029acddfc2cSWeiyi Lu _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) 1030acddfc2cSWeiyi Lu 1031acddfc2cSWeiyi Lu #define GATE_APMIXED(_id, _name, _parent, _shift) \ 1032acddfc2cSWeiyi Lu GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) 1033acddfc2cSWeiyi Lu 1034acddfc2cSWeiyi Lu /* 1035acddfc2cSWeiyi Lu * CRITICAL CLOCK: 1036acddfc2cSWeiyi Lu * apmixed_appll26m is the toppest clock gate of all PLLs. 1037acddfc2cSWeiyi Lu */ 1038acddfc2cSWeiyi Lu static const struct mtk_gate apmixed_clks[] = { 1039acddfc2cSWeiyi Lu /* AUDIO0 */ 1040acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", 1041acddfc2cSWeiyi Lu "f_f26m_ck", 4), 1042acddfc2cSWeiyi Lu GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", 1043acddfc2cSWeiyi Lu "f_f26m_ck", 5, CLK_IS_CRITICAL), 1044acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", 1045acddfc2cSWeiyi Lu "f_f26m_ck", 6), 1046acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", 1047acddfc2cSWeiyi Lu "f_f26m_ck", 7), 1048acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", 1049acddfc2cSWeiyi Lu "f_f26m_ck", 8), 1050acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", 1051acddfc2cSWeiyi Lu "f_f26m_ck", 9), 1052acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", 1053acddfc2cSWeiyi Lu "f_f26m_ck", 11), 1054acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", 1055acddfc2cSWeiyi Lu "f_f26m_ck", 13), 1056acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", 1057acddfc2cSWeiyi Lu "f_f26m_ck", 14), 1058acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", 1059acddfc2cSWeiyi Lu "f_f26m_ck", 16), 1060acddfc2cSWeiyi Lu GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", 1061acddfc2cSWeiyi Lu "f_f26m_ck", 17), 1062acddfc2cSWeiyi Lu }; 1063acddfc2cSWeiyi Lu 1064acddfc2cSWeiyi Lu #define MT8183_PLL_FMAX (3800UL * MHZ) 1065acddfc2cSWeiyi Lu #define MT8183_PLL_FMIN (1500UL * MHZ) 1066acddfc2cSWeiyi Lu 1067acddfc2cSWeiyi Lu #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1068acddfc2cSWeiyi Lu _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1069acddfc2cSWeiyi Lu _pd_shift, _tuner_reg, _tuner_en_reg, \ 1070acddfc2cSWeiyi Lu _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1071acddfc2cSWeiyi Lu _pcw_chg_reg, _div_table) { \ 1072acddfc2cSWeiyi Lu .id = _id, \ 1073acddfc2cSWeiyi Lu .name = _name, \ 1074acddfc2cSWeiyi Lu .reg = _reg, \ 1075acddfc2cSWeiyi Lu .pwr_reg = _pwr_reg, \ 1076acddfc2cSWeiyi Lu .en_mask = _en_mask, \ 1077acddfc2cSWeiyi Lu .flags = _flags, \ 1078acddfc2cSWeiyi Lu .rst_bar_mask = _rst_bar_mask, \ 1079acddfc2cSWeiyi Lu .fmax = MT8183_PLL_FMAX, \ 1080acddfc2cSWeiyi Lu .fmin = MT8183_PLL_FMIN, \ 1081acddfc2cSWeiyi Lu .pcwbits = _pcwbits, \ 1082acddfc2cSWeiyi Lu .pcwibits = _pcwibits, \ 1083acddfc2cSWeiyi Lu .pd_reg = _pd_reg, \ 1084acddfc2cSWeiyi Lu .pd_shift = _pd_shift, \ 1085acddfc2cSWeiyi Lu .tuner_reg = _tuner_reg, \ 1086acddfc2cSWeiyi Lu .tuner_en_reg = _tuner_en_reg, \ 1087acddfc2cSWeiyi Lu .tuner_en_bit = _tuner_en_bit, \ 1088acddfc2cSWeiyi Lu .pcw_reg = _pcw_reg, \ 1089acddfc2cSWeiyi Lu .pcw_shift = _pcw_shift, \ 1090acddfc2cSWeiyi Lu .pcw_chg_reg = _pcw_chg_reg, \ 1091acddfc2cSWeiyi Lu .div_table = _div_table, \ 1092acddfc2cSWeiyi Lu } 1093acddfc2cSWeiyi Lu 1094acddfc2cSWeiyi Lu #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1095acddfc2cSWeiyi Lu _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1096acddfc2cSWeiyi Lu _pd_shift, _tuner_reg, _tuner_en_reg, \ 1097acddfc2cSWeiyi Lu _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1098acddfc2cSWeiyi Lu _pcw_chg_reg) \ 1099acddfc2cSWeiyi Lu PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1100acddfc2cSWeiyi Lu _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ 1101acddfc2cSWeiyi Lu _pd_shift, _tuner_reg, _tuner_en_reg, \ 1102acddfc2cSWeiyi Lu _tuner_en_bit, _pcw_reg, _pcw_shift, \ 1103acddfc2cSWeiyi Lu _pcw_chg_reg, NULL) 1104acddfc2cSWeiyi Lu 1105acddfc2cSWeiyi Lu static const struct mtk_pll_div_table armpll_div_table[] = { 1106acddfc2cSWeiyi Lu { .div = 0, .freq = MT8183_PLL_FMAX }, 1107acddfc2cSWeiyi Lu { .div = 1, .freq = 1500 * MHZ }, 1108acddfc2cSWeiyi Lu { .div = 2, .freq = 750 * MHZ }, 1109acddfc2cSWeiyi Lu { .div = 3, .freq = 375 * MHZ }, 1110acddfc2cSWeiyi Lu { .div = 4, .freq = 187500000 }, 1111acddfc2cSWeiyi Lu { } /* sentinel */ 1112acddfc2cSWeiyi Lu }; 1113acddfc2cSWeiyi Lu 1114acddfc2cSWeiyi Lu static const struct mtk_pll_div_table mfgpll_div_table[] = { 1115acddfc2cSWeiyi Lu { .div = 0, .freq = MT8183_PLL_FMAX }, 1116acddfc2cSWeiyi Lu { .div = 1, .freq = 1600 * MHZ }, 1117acddfc2cSWeiyi Lu { .div = 2, .freq = 800 * MHZ }, 1118acddfc2cSWeiyi Lu { .div = 3, .freq = 400 * MHZ }, 1119acddfc2cSWeiyi Lu { .div = 4, .freq = 200 * MHZ }, 1120acddfc2cSWeiyi Lu { } /* sentinel */ 1121acddfc2cSWeiyi Lu }; 1122acddfc2cSWeiyi Lu 1123acddfc2cSWeiyi Lu static const struct mtk_pll_data plls[] = { 1124acddfc2cSWeiyi Lu PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001, 1125acddfc2cSWeiyi Lu HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, 1126acddfc2cSWeiyi Lu 0x0204, 0, 0, armpll_div_table), 1127acddfc2cSWeiyi Lu PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001, 1128acddfc2cSWeiyi Lu HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, 1129acddfc2cSWeiyi Lu 0x0214, 0, 0, armpll_div_table), 1130acddfc2cSWeiyi Lu PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001, 1131acddfc2cSWeiyi Lu HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, 1132acddfc2cSWeiyi Lu 0x0294, 0, 0), 1133acddfc2cSWeiyi Lu PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001, 1134acddfc2cSWeiyi Lu HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, 1135acddfc2cSWeiyi Lu 0x0224, 0, 0), 1136acddfc2cSWeiyi Lu PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001, 1137acddfc2cSWeiyi Lu HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, 1138acddfc2cSWeiyi Lu 0x0234, 0, 0), 1139acddfc2cSWeiyi Lu PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001, 1140acddfc2cSWeiyi Lu 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, 1141acddfc2cSWeiyi Lu mfgpll_div_table), 1142acddfc2cSWeiyi Lu PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001, 1143acddfc2cSWeiyi Lu 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), 1144acddfc2cSWeiyi Lu PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001, 1145acddfc2cSWeiyi Lu 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), 1146acddfc2cSWeiyi Lu PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001, 1147acddfc2cSWeiyi Lu HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, 1148acddfc2cSWeiyi Lu 0x0274, 0, 0), 1149acddfc2cSWeiyi Lu PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001, 1150acddfc2cSWeiyi Lu 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), 1151acddfc2cSWeiyi Lu PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001, 1152acddfc2cSWeiyi Lu 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), 1153acddfc2cSWeiyi Lu }; 1154acddfc2cSWeiyi Lu 1155acddfc2cSWeiyi Lu static int clk_mt8183_apmixed_probe(struct platform_device *pdev) 1156acddfc2cSWeiyi Lu { 1157acddfc2cSWeiyi Lu struct clk_onecell_data *clk_data; 1158acddfc2cSWeiyi Lu struct device_node *node = pdev->dev.of_node; 1159acddfc2cSWeiyi Lu 1160acddfc2cSWeiyi Lu clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1161acddfc2cSWeiyi Lu 1162acddfc2cSWeiyi Lu mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1163acddfc2cSWeiyi Lu 1164acddfc2cSWeiyi Lu mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), 1165acddfc2cSWeiyi Lu clk_data); 1166acddfc2cSWeiyi Lu 1167acddfc2cSWeiyi Lu return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1168acddfc2cSWeiyi Lu } 1169acddfc2cSWeiyi Lu 1170c93d059aSWeiyi Lu static struct clk_onecell_data *top_clk_data; 1171c93d059aSWeiyi Lu 1172c93d059aSWeiyi Lu static void clk_mt8183_top_init_early(struct device_node *node) 1173c93d059aSWeiyi Lu { 1174c93d059aSWeiyi Lu int i; 1175c93d059aSWeiyi Lu 1176c93d059aSWeiyi Lu top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1177c93d059aSWeiyi Lu 1178c93d059aSWeiyi Lu for (i = 0; i < CLK_TOP_NR_CLK; i++) 1179c93d059aSWeiyi Lu top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); 1180c93d059aSWeiyi Lu 1181c93d059aSWeiyi Lu mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1182c93d059aSWeiyi Lu top_clk_data); 1183c93d059aSWeiyi Lu 1184c93d059aSWeiyi Lu of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); 1185c93d059aSWeiyi Lu } 1186c93d059aSWeiyi Lu 1187c93d059aSWeiyi Lu CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", 1188c93d059aSWeiyi Lu clk_mt8183_top_init_early); 1189c93d059aSWeiyi Lu 1190acddfc2cSWeiyi Lu static int clk_mt8183_top_probe(struct platform_device *pdev) 1191acddfc2cSWeiyi Lu { 1192acddfc2cSWeiyi Lu void __iomem *base; 1193acddfc2cSWeiyi Lu struct device_node *node = pdev->dev.of_node; 1194acddfc2cSWeiyi Lu 1195067de0a6SYueHaibing base = devm_platform_ioremap_resource(pdev, 0); 1196acddfc2cSWeiyi Lu if (IS_ERR(base)) 1197acddfc2cSWeiyi Lu return PTR_ERR(base); 1198acddfc2cSWeiyi Lu 1199acddfc2cSWeiyi Lu mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 1200c93d059aSWeiyi Lu top_clk_data); 1201acddfc2cSWeiyi Lu 1202c93d059aSWeiyi Lu mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), 1203c93d059aSWeiyi Lu top_clk_data); 1204c93d059aSWeiyi Lu 1205c93d059aSWeiyi Lu mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); 1206acddfc2cSWeiyi Lu 1207acddfc2cSWeiyi Lu mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), 1208c93d059aSWeiyi Lu node, &mt8183_clk_lock, top_clk_data); 1209acddfc2cSWeiyi Lu 1210acddfc2cSWeiyi Lu mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), 1211c93d059aSWeiyi Lu base, &mt8183_clk_lock, top_clk_data); 1212acddfc2cSWeiyi Lu 1213acddfc2cSWeiyi Lu mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), 1214c93d059aSWeiyi Lu base, &mt8183_clk_lock, top_clk_data); 1215acddfc2cSWeiyi Lu 1216acddfc2cSWeiyi Lu mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 1217c93d059aSWeiyi Lu top_clk_data); 1218acddfc2cSWeiyi Lu 1219c93d059aSWeiyi Lu return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); 1220acddfc2cSWeiyi Lu } 1221acddfc2cSWeiyi Lu 1222acddfc2cSWeiyi Lu static int clk_mt8183_infra_probe(struct platform_device *pdev) 1223acddfc2cSWeiyi Lu { 1224acddfc2cSWeiyi Lu struct clk_onecell_data *clk_data; 1225acddfc2cSWeiyi Lu struct device_node *node = pdev->dev.of_node; 122664ebb57aSyong.liang int r; 1227acddfc2cSWeiyi Lu 1228acddfc2cSWeiyi Lu clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1229acddfc2cSWeiyi Lu 1230acddfc2cSWeiyi Lu mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1231acddfc2cSWeiyi Lu clk_data); 1232acddfc2cSWeiyi Lu 123364ebb57aSyong.liang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 123464ebb57aSyong.liang if (r) { 123564ebb57aSyong.liang dev_err(&pdev->dev, 123664ebb57aSyong.liang "%s(): could not register clock provider: %d\n", 123764ebb57aSyong.liang __func__, r); 123864ebb57aSyong.liang return r; 123964ebb57aSyong.liang } 124064ebb57aSyong.liang 124164ebb57aSyong.liang mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET); 124264ebb57aSyong.liang 124364ebb57aSyong.liang return r; 1244acddfc2cSWeiyi Lu } 1245acddfc2cSWeiyi Lu 1246f9e55ac2SChunfeng Yun static int clk_mt8183_peri_probe(struct platform_device *pdev) 1247f9e55ac2SChunfeng Yun { 1248f9e55ac2SChunfeng Yun struct clk_onecell_data *clk_data; 1249f9e55ac2SChunfeng Yun struct device_node *node = pdev->dev.of_node; 1250f9e55ac2SChunfeng Yun 1251f9e55ac2SChunfeng Yun clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 1252f9e55ac2SChunfeng Yun 1253f9e55ac2SChunfeng Yun mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), 1254f9e55ac2SChunfeng Yun clk_data); 1255f9e55ac2SChunfeng Yun 1256acddfc2cSWeiyi Lu return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1257acddfc2cSWeiyi Lu } 1258acddfc2cSWeiyi Lu 1259acddfc2cSWeiyi Lu static int clk_mt8183_mcu_probe(struct platform_device *pdev) 1260acddfc2cSWeiyi Lu { 1261acddfc2cSWeiyi Lu struct clk_onecell_data *clk_data; 1262acddfc2cSWeiyi Lu struct device_node *node = pdev->dev.of_node; 1263acddfc2cSWeiyi Lu void __iomem *base; 1264acddfc2cSWeiyi Lu 1265067de0a6SYueHaibing base = devm_platform_ioremap_resource(pdev, 0); 1266acddfc2cSWeiyi Lu if (IS_ERR(base)) 1267acddfc2cSWeiyi Lu return PTR_ERR(base); 1268acddfc2cSWeiyi Lu 1269acddfc2cSWeiyi Lu clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); 1270acddfc2cSWeiyi Lu 1271acddfc2cSWeiyi Lu mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, 1272acddfc2cSWeiyi Lu &mt8183_clk_lock, clk_data); 1273acddfc2cSWeiyi Lu 1274acddfc2cSWeiyi Lu return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1275acddfc2cSWeiyi Lu } 1276acddfc2cSWeiyi Lu 1277acddfc2cSWeiyi Lu static const struct of_device_id of_match_clk_mt8183[] = { 1278acddfc2cSWeiyi Lu { 1279acddfc2cSWeiyi Lu .compatible = "mediatek,mt8183-apmixedsys", 1280acddfc2cSWeiyi Lu .data = clk_mt8183_apmixed_probe, 1281acddfc2cSWeiyi Lu }, { 1282acddfc2cSWeiyi Lu .compatible = "mediatek,mt8183-topckgen", 1283acddfc2cSWeiyi Lu .data = clk_mt8183_top_probe, 1284acddfc2cSWeiyi Lu }, { 1285acddfc2cSWeiyi Lu .compatible = "mediatek,mt8183-infracfg", 1286acddfc2cSWeiyi Lu .data = clk_mt8183_infra_probe, 1287acddfc2cSWeiyi Lu }, { 1288f9e55ac2SChunfeng Yun .compatible = "mediatek,mt8183-pericfg", 1289f9e55ac2SChunfeng Yun .data = clk_mt8183_peri_probe, 1290f9e55ac2SChunfeng Yun }, { 1291acddfc2cSWeiyi Lu .compatible = "mediatek,mt8183-mcucfg", 1292acddfc2cSWeiyi Lu .data = clk_mt8183_mcu_probe, 1293acddfc2cSWeiyi Lu }, { 1294acddfc2cSWeiyi Lu /* sentinel */ 1295acddfc2cSWeiyi Lu } 1296acddfc2cSWeiyi Lu }; 1297acddfc2cSWeiyi Lu 1298acddfc2cSWeiyi Lu static int clk_mt8183_probe(struct platform_device *pdev) 1299acddfc2cSWeiyi Lu { 1300acddfc2cSWeiyi Lu int (*clk_probe)(struct platform_device *pdev); 1301acddfc2cSWeiyi Lu int r; 1302acddfc2cSWeiyi Lu 1303acddfc2cSWeiyi Lu clk_probe = of_device_get_match_data(&pdev->dev); 1304acddfc2cSWeiyi Lu if (!clk_probe) 1305acddfc2cSWeiyi Lu return -EINVAL; 1306acddfc2cSWeiyi Lu 1307acddfc2cSWeiyi Lu r = clk_probe(pdev); 1308acddfc2cSWeiyi Lu if (r) 1309acddfc2cSWeiyi Lu dev_err(&pdev->dev, 1310acddfc2cSWeiyi Lu "could not register clock provider: %s: %d\n", 1311acddfc2cSWeiyi Lu pdev->name, r); 1312acddfc2cSWeiyi Lu 1313acddfc2cSWeiyi Lu return r; 1314acddfc2cSWeiyi Lu } 1315acddfc2cSWeiyi Lu 1316acddfc2cSWeiyi Lu static struct platform_driver clk_mt8183_drv = { 1317acddfc2cSWeiyi Lu .probe = clk_mt8183_probe, 1318acddfc2cSWeiyi Lu .driver = { 1319acddfc2cSWeiyi Lu .name = "clk-mt8183", 1320acddfc2cSWeiyi Lu .of_match_table = of_match_clk_mt8183, 1321acddfc2cSWeiyi Lu }, 1322acddfc2cSWeiyi Lu }; 1323acddfc2cSWeiyi Lu 1324acddfc2cSWeiyi Lu static int __init clk_mt8183_init(void) 1325acddfc2cSWeiyi Lu { 1326acddfc2cSWeiyi Lu return platform_driver_register(&clk_mt8183_drv); 1327acddfc2cSWeiyi Lu } 1328acddfc2cSWeiyi Lu 1329acddfc2cSWeiyi Lu arch_initcall(clk_mt8183_init); 1330