1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2018 MediaTek Inc.
4 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
5 
6 #include <linux/clk-provider.h>
7 #include <linux/platform_device.h>
8 
9 #include "clk-mtk.h"
10 #include "clk-gate.h"
11 
12 #include <dt-bindings/clock/mt8183-clk.h>
13 
14 static const struct mtk_gate_regs vdec0_cg_regs = {
15 	.set_ofs = 0x0,
16 	.clr_ofs = 0x4,
17 	.sta_ofs = 0x0,
18 };
19 
20 static const struct mtk_gate_regs vdec1_cg_regs = {
21 	.set_ofs = 0x8,
22 	.clr_ofs = 0xc,
23 	.sta_ofs = 0x8,
24 };
25 
26 #define GATE_VDEC0_I(_id, _name, _parent, _shift)		\
27 	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift,	\
28 		&mtk_clk_gate_ops_setclr_inv)
29 
30 #define GATE_VDEC1_I(_id, _name, _parent, _shift)		\
31 	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift,	\
32 		&mtk_clk_gate_ops_setclr_inv)
33 
34 static const struct mtk_gate vdec_clks[] = {
35 	/* VDEC0 */
36 	GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0),
37 	/* VDEC1 */
38 	GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
39 };
40 
41 static int clk_mt8183_vdec_probe(struct platform_device *pdev)
42 {
43 	struct clk_hw_onecell_data *clk_data;
44 	struct device_node *node = pdev->dev.of_node;
45 
46 	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
47 
48 	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
49 			clk_data);
50 
51 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
52 }
53 
54 static const struct of_device_id of_match_clk_mt8183_vdec[] = {
55 	{ .compatible = "mediatek,mt8183-vdecsys", },
56 	{}
57 };
58 
59 static struct platform_driver clk_mt8183_vdec_drv = {
60 	.probe = clk_mt8183_vdec_probe,
61 	.driver = {
62 		.name = "clk-mt8183-vdec",
63 		.of_match_table = of_match_clk_mt8183_vdec,
64 	},
65 };
66 
67 builtin_platform_driver(clk_mt8183_vdec_drv);
68