1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2018 MediaTek Inc.
4 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
5 
6 #include <linux/clk-provider.h>
7 #include <linux/platform_device.h>
8 
9 #include "clk-mtk.h"
10 #include "clk-gate.h"
11 
12 #include <dt-bindings/clock/mt8183-clk.h>
13 
14 static const struct mtk_gate_regs img_cg_regs = {
15 	.set_ofs = 0x4,
16 	.clr_ofs = 0x8,
17 	.sta_ofs = 0x0,
18 };
19 
20 #define GATE_IMG(_id, _name, _parent, _shift)			\
21 	GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift,	\
22 		&mtk_clk_gate_ops_setclr)
23 
24 static const struct mtk_gate img_clks[] = {
25 	GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0),
26 	GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1),
27 	GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2),
28 	GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3),
29 	GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4),
30 	GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5),
31 	GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6),
32 	GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7),
33 	GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8),
34 	GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
35 };
36 
37 static int clk_mt8183_img_probe(struct platform_device *pdev)
38 {
39 	struct clk_hw_onecell_data *clk_data;
40 	struct device_node *node = pdev->dev.of_node;
41 
42 	clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
43 
44 	mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
45 			clk_data);
46 
47 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
48 }
49 
50 static const struct of_device_id of_match_clk_mt8183_img[] = {
51 	{ .compatible = "mediatek,mt8183-imgsys", },
52 	{}
53 };
54 
55 static struct platform_driver clk_mt8183_img_drv = {
56 	.probe = clk_mt8183_img_probe,
57 	.driver = {
58 		.name = "clk-mt8183-img",
59 		.of_match_table = of_match_clk_mt8183_img,
60 	},
61 };
62 
63 builtin_platform_driver(clk_mt8183_img_drv);
64