1a6822483SFabien Parent // SPDX-License-Identifier: GPL-2.0 2a6822483SFabien Parent /* 3a6822483SFabien Parent * Copyright (c) 2020 MediaTek Inc. 4a6822483SFabien Parent * Copyright (c) 2020 BayLibre, SAS 5a6822483SFabien Parent * Author: James Liao <jamesjj.liao@mediatek.com> 6a6822483SFabien Parent * Fabien Parent <fparent@baylibre.com> 7a6822483SFabien Parent */ 8a6822483SFabien Parent 9a6822483SFabien Parent #include <linux/delay.h> 10a6822483SFabien Parent #include <linux/of.h> 11a6822483SFabien Parent #include <linux/of_address.h> 12a6822483SFabien Parent #include <linux/slab.h> 13a6822483SFabien Parent #include <linux/mfd/syscon.h> 14a6822483SFabien Parent 15a6822483SFabien Parent #include "clk-gate.h" 1639691fb6SChen-Yu Tsai #include "clk-mtk.h" 1739691fb6SChen-Yu Tsai #include "clk-pll.h" 18a6822483SFabien Parent 19a6822483SFabien Parent #include <dt-bindings/clock/mt8167-clk.h> 20a6822483SFabien Parent 21a6822483SFabien Parent static DEFINE_SPINLOCK(mt8167_clk_lock); 22a6822483SFabien Parent 23a6822483SFabien Parent static const struct mtk_fixed_clk fixed_clks[] __initconst = { 24a6822483SFabien Parent FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), 25a6822483SFabien Parent FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000), 26a6822483SFabien Parent FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000), 27a6822483SFabien Parent FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 75000000), 28a6822483SFabien Parent FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000), 29a6822483SFabien Parent FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000), 30a6822483SFabien Parent }; 31a6822483SFabien Parent 32a6822483SFabien Parent static const struct mtk_fixed_factor top_divs[] __initconst = { 33a6822483SFabien Parent FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 34a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2), 35a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), 36a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8), 37a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16), 38a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11), 39a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22), 40a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), 41a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), 42a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12), 43a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), 44a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10), 45a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20), 46a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40), 47a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), 48a6822483SFabien Parent FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14), 49a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 50a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), 51a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8), 52a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16), 53a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 54a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), 55a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12), 56a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24), 57a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 58a6822483SFabien Parent FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20), 59a6822483SFabien Parent FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1), 60a6822483SFabien Parent FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 61a6822483SFabien Parent FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3), 62a6822483SFabien Parent FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1), 63a6822483SFabien Parent FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 64a6822483SFabien Parent FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 65a6822483SFabien Parent FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 66a6822483SFabien Parent FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26), 67a6822483SFabien Parent FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 68a6822483SFabien Parent FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 69a6822483SFabien Parent FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2), 70a6822483SFabien Parent FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2), 71a6822483SFabien Parent FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 72a6822483SFabien Parent FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 73a6822483SFabien Parent FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2), 74a6822483SFabien Parent FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2), 75a6822483SFabien Parent FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1), 76a6822483SFabien Parent FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2), 77a6822483SFabien Parent FACTOR(CLK_TOP_MIPI_26M, "mipi_26m", "clk26m", 1, 1), 78a6822483SFabien Parent FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 79a6822483SFabien Parent FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 80a6822483SFabien Parent FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4), 81a6822483SFabien Parent FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8), 82a6822483SFabien Parent FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16), 83a6822483SFabien Parent FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2), 84a6822483SFabien Parent FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2), 85a6822483SFabien Parent FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2), 86a6822483SFabien Parent }; 87a6822483SFabien Parent 88a6822483SFabien Parent static const char * const uart0_parents[] __initconst = { 89a6822483SFabien Parent "clk26m_ck", 90a6822483SFabien Parent "univpll_d24" 91a6822483SFabien Parent }; 92a6822483SFabien Parent 93a6822483SFabien Parent static const char * const gfmux_emi1x_parents[] __initconst = { 94a6822483SFabien Parent "clk26m_ck", 95a6822483SFabien Parent "dmpll_ck" 96a6822483SFabien Parent }; 97a6822483SFabien Parent 98a6822483SFabien Parent static const char * const emi_ddrphy_parents[] __initconst = { 99a6822483SFabien Parent "gfmux_emi1x_sel", 100a6822483SFabien Parent "gfmux_emi1x_sel" 101a6822483SFabien Parent }; 102a6822483SFabien Parent 103a6822483SFabien Parent static const char * const ahb_infra_parents[] __initconst = { 104a6822483SFabien Parent "clk_null", 105a6822483SFabien Parent "clk26m_ck", 106a6822483SFabien Parent "mainpll_d11", 107a6822483SFabien Parent "clk_null", 108a6822483SFabien Parent "mainpll_d12", 109a6822483SFabien Parent "clk_null", 110a6822483SFabien Parent "clk_null", 111a6822483SFabien Parent "clk_null", 112a6822483SFabien Parent "clk_null", 113a6822483SFabien Parent "clk_null", 114a6822483SFabien Parent "clk_null", 115a6822483SFabien Parent "clk_null", 116a6822483SFabien Parent "mainpll_d10" 117a6822483SFabien Parent }; 118a6822483SFabien Parent 119a6822483SFabien Parent static const char * const csw_mux_mfg_parents[] __initconst = { 120a6822483SFabien Parent "clk_null", 121a6822483SFabien Parent "clk_null", 122a6822483SFabien Parent "univpll_d3", 123a6822483SFabien Parent "univpll_d2", 124a6822483SFabien Parent "clk26m_ck", 125a6822483SFabien Parent "mainpll_d4", 126a6822483SFabien Parent "univpll_d24", 127a6822483SFabien Parent "mmpll380m" 128a6822483SFabien Parent }; 129a6822483SFabien Parent 130a6822483SFabien Parent static const char * const msdc0_parents[] __initconst = { 131a6822483SFabien Parent "clk26m_ck", 132a6822483SFabien Parent "univpll_d6", 133a6822483SFabien Parent "mainpll_d8", 134a6822483SFabien Parent "univpll_d8", 135a6822483SFabien Parent "mainpll_d16", 136a6822483SFabien Parent "mmpll_200m", 137a6822483SFabien Parent "mainpll_d12", 138a6822483SFabien Parent "mmpll_d2" 139a6822483SFabien Parent }; 140a6822483SFabien Parent 141a6822483SFabien Parent static const char * const camtg_mm_parents[] __initconst = { 142a6822483SFabien Parent "clk_null", 143a6822483SFabien Parent "clk26m_ck", 144a6822483SFabien Parent "usb_phy48m_ck", 145a6822483SFabien Parent "clk_null", 146a6822483SFabien Parent "univpll_d6" 147a6822483SFabien Parent }; 148a6822483SFabien Parent 149a6822483SFabien Parent static const char * const pwm_mm_parents[] __initconst = { 150a6822483SFabien Parent "clk26m_ck", 151a6822483SFabien Parent "univpll_d12" 152a6822483SFabien Parent }; 153a6822483SFabien Parent 154a6822483SFabien Parent static const char * const uart1_parents[] __initconst = { 155a6822483SFabien Parent "clk26m_ck", 156a6822483SFabien Parent "univpll_d24" 157a6822483SFabien Parent }; 158a6822483SFabien Parent 159a6822483SFabien Parent static const char * const msdc1_parents[] __initconst = { 160a6822483SFabien Parent "clk26m_ck", 161a6822483SFabien Parent "univpll_d6", 162a6822483SFabien Parent "mainpll_d8", 163a6822483SFabien Parent "univpll_d8", 164a6822483SFabien Parent "mainpll_d16", 165a6822483SFabien Parent "mmpll_200m", 166a6822483SFabien Parent "mainpll_d12", 167a6822483SFabien Parent "mmpll_d2" 168a6822483SFabien Parent }; 169a6822483SFabien Parent 170a6822483SFabien Parent static const char * const spm_52m_parents[] __initconst = { 171a6822483SFabien Parent "clk26m_ck", 172a6822483SFabien Parent "univpll_d24" 173a6822483SFabien Parent }; 174a6822483SFabien Parent 175a6822483SFabien Parent static const char * const pmicspi_parents[] __initconst = { 176a6822483SFabien Parent "univpll_d20", 177a6822483SFabien Parent "usb_phy48m_ck", 178a6822483SFabien Parent "univpll_d16", 179a6822483SFabien Parent "clk26m_ck" 180a6822483SFabien Parent }; 181a6822483SFabien Parent 182a6822483SFabien Parent static const char * const qaxi_aud26m_parents[] __initconst = { 183a6822483SFabien Parent "clk26m_ck", 184a6822483SFabien Parent "ahb_infra_sel" 185a6822483SFabien Parent }; 186a6822483SFabien Parent 187a6822483SFabien Parent static const char * const aud_intbus_parents[] __initconst = { 188a6822483SFabien Parent "clk_null", 189a6822483SFabien Parent "clk26m_ck", 190a6822483SFabien Parent "mainpll_d22", 191a6822483SFabien Parent "clk_null", 192a6822483SFabien Parent "mainpll_d11" 193a6822483SFabien Parent }; 194a6822483SFabien Parent 195a6822483SFabien Parent static const char * const nfi2x_pad_parents[] __initconst = { 196a6822483SFabien Parent "clk_null", 197a6822483SFabien Parent "clk_null", 198a6822483SFabien Parent "clk_null", 199a6822483SFabien Parent "clk_null", 200a6822483SFabien Parent "clk_null", 201a6822483SFabien Parent "clk_null", 202a6822483SFabien Parent "clk_null", 203a6822483SFabien Parent "clk_null", 204a6822483SFabien Parent "clk26m_ck", 205a6822483SFabien Parent "clk_null", 206a6822483SFabien Parent "clk_null", 207a6822483SFabien Parent "clk_null", 208a6822483SFabien Parent "clk_null", 209a6822483SFabien Parent "clk_null", 210a6822483SFabien Parent "clk_null", 211a6822483SFabien Parent "clk_null", 212a6822483SFabien Parent "clk_null", 213a6822483SFabien Parent "mainpll_d12", 214a6822483SFabien Parent "mainpll_d8", 215a6822483SFabien Parent "clk_null", 216a6822483SFabien Parent "mainpll_d6", 217a6822483SFabien Parent "clk_null", 218a6822483SFabien Parent "clk_null", 219a6822483SFabien Parent "clk_null", 220a6822483SFabien Parent "clk_null", 221a6822483SFabien Parent "clk_null", 222a6822483SFabien Parent "clk_null", 223a6822483SFabien Parent "clk_null", 224a6822483SFabien Parent "clk_null", 225a6822483SFabien Parent "clk_null", 226a6822483SFabien Parent "clk_null", 227a6822483SFabien Parent "clk_null", 228a6822483SFabien Parent "mainpll_d4", 229a6822483SFabien Parent "clk_null", 230a6822483SFabien Parent "clk_null", 231a6822483SFabien Parent "clk_null", 232a6822483SFabien Parent "clk_null", 233a6822483SFabien Parent "clk_null", 234a6822483SFabien Parent "clk_null", 235a6822483SFabien Parent "clk_null", 236a6822483SFabien Parent "clk_null", 237a6822483SFabien Parent "clk_null", 238a6822483SFabien Parent "clk_null", 239a6822483SFabien Parent "clk_null", 240a6822483SFabien Parent "clk_null", 241a6822483SFabien Parent "clk_null", 242a6822483SFabien Parent "clk_null", 243a6822483SFabien Parent "clk_null", 244a6822483SFabien Parent "clk_null", 245a6822483SFabien Parent "clk_null", 246a6822483SFabien Parent "clk_null", 247a6822483SFabien Parent "clk_null", 248a6822483SFabien Parent "clk_null", 249a6822483SFabien Parent "clk_null", 250a6822483SFabien Parent "clk_null", 251a6822483SFabien Parent "clk_null", 252a6822483SFabien Parent "clk_null", 253a6822483SFabien Parent "clk_null", 254a6822483SFabien Parent "clk_null", 255a6822483SFabien Parent "clk_null", 256a6822483SFabien Parent "clk_null", 257a6822483SFabien Parent "clk_null", 258a6822483SFabien Parent "clk_null", 259a6822483SFabien Parent "clk_null", 260a6822483SFabien Parent "clk_null", 261a6822483SFabien Parent "clk_null", 262a6822483SFabien Parent "clk_null", 263a6822483SFabien Parent "clk_null", 264a6822483SFabien Parent "clk_null", 265a6822483SFabien Parent "clk_null", 266a6822483SFabien Parent "clk_null", 267a6822483SFabien Parent "clk_null", 268a6822483SFabien Parent "clk_null", 269a6822483SFabien Parent "clk_null", 270a6822483SFabien Parent "clk_null", 271a6822483SFabien Parent "clk_null", 272a6822483SFabien Parent "clk_null", 273a6822483SFabien Parent "clk_null", 274a6822483SFabien Parent "clk_null", 275a6822483SFabien Parent "clk_null", 276a6822483SFabien Parent "clk_null", 277a6822483SFabien Parent "mainpll_d10", 278a6822483SFabien Parent "mainpll_d7", 279a6822483SFabien Parent "clk_null", 280a6822483SFabien Parent "mainpll_d5" 281a6822483SFabien Parent }; 282a6822483SFabien Parent 283a6822483SFabien Parent static const char * const nfi1x_pad_parents[] __initconst = { 284a6822483SFabien Parent "ahb_infra_sel", 285a6822483SFabien Parent "nfi1x_ck" 286a6822483SFabien Parent }; 287a6822483SFabien Parent 288a6822483SFabien Parent static const char * const mfg_mm_parents[] __initconst = { 289a6822483SFabien Parent "clk_null", 290a6822483SFabien Parent "clk_null", 291a6822483SFabien Parent "clk_null", 292a6822483SFabien Parent "clk_null", 293a6822483SFabien Parent "clk_null", 294a6822483SFabien Parent "clk_null", 295a6822483SFabien Parent "clk_null", 296a6822483SFabien Parent "clk_null", 297a6822483SFabien Parent "csw_mux_mfg_sel", 298a6822483SFabien Parent "clk_null", 299a6822483SFabien Parent "clk_null", 300a6822483SFabien Parent "clk_null", 301a6822483SFabien Parent "clk_null", 302a6822483SFabien Parent "clk_null", 303a6822483SFabien Parent "clk_null", 304a6822483SFabien Parent "clk_null", 305a6822483SFabien Parent "mainpll_d3", 306a6822483SFabien Parent "clk_null", 307a6822483SFabien Parent "clk_null", 308a6822483SFabien Parent "clk_null", 309a6822483SFabien Parent "clk_null", 310a6822483SFabien Parent "clk_null", 311a6822483SFabien Parent "clk_null", 312a6822483SFabien Parent "clk_null", 313a6822483SFabien Parent "clk_null", 314a6822483SFabien Parent "clk_null", 315a6822483SFabien Parent "clk_null", 316a6822483SFabien Parent "clk_null", 317a6822483SFabien Parent "clk_null", 318a6822483SFabien Parent "clk_null", 319a6822483SFabien Parent "clk_null", 320a6822483SFabien Parent "clk_null", 321a6822483SFabien Parent "clk_null", 322a6822483SFabien Parent "mainpll_d5", 323a6822483SFabien Parent "mainpll_d7", 324a6822483SFabien Parent "clk_null", 325a6822483SFabien Parent "mainpll_d14" 326a6822483SFabien Parent }; 327a6822483SFabien Parent 328a6822483SFabien Parent static const char * const ddrphycfg_parents[] __initconst = { 329a6822483SFabien Parent "clk26m_ck", 330a6822483SFabien Parent "mainpll_d16" 331a6822483SFabien Parent }; 332a6822483SFabien Parent 333a6822483SFabien Parent static const char * const smi_mm_parents[] __initconst = { 334a6822483SFabien Parent "clk26m_ck", 335a6822483SFabien Parent "clk_null", 336a6822483SFabien Parent "clk_null", 337a6822483SFabien Parent "clk_null", 338a6822483SFabien Parent "clk_null", 339a6822483SFabien Parent "clk_null", 340a6822483SFabien Parent "clk_null", 341a6822483SFabien Parent "clk_null", 342a6822483SFabien Parent "clk_null", 343a6822483SFabien Parent "univpll_d4", 344a6822483SFabien Parent "mainpll_d7", 345a6822483SFabien Parent "clk_null", 346a6822483SFabien Parent "mainpll_d14" 347a6822483SFabien Parent }; 348a6822483SFabien Parent 349a6822483SFabien Parent static const char * const usb_78m_parents[] __initconst = { 350a6822483SFabien Parent "clk_null", 351a6822483SFabien Parent "clk26m_ck", 352a6822483SFabien Parent "univpll_d16", 353a6822483SFabien Parent "clk_null", 354a6822483SFabien Parent "mainpll_d20" 355a6822483SFabien Parent }; 356a6822483SFabien Parent 357a6822483SFabien Parent static const char * const scam_mm_parents[] __initconst = { 358a6822483SFabien Parent "clk_null", 359a6822483SFabien Parent "clk26m_ck", 360a6822483SFabien Parent "mainpll_d14", 361a6822483SFabien Parent "clk_null", 362a6822483SFabien Parent "mainpll_d12" 363a6822483SFabien Parent }; 364a6822483SFabien Parent 365a6822483SFabien Parent static const char * const spinor_parents[] __initconst = { 366a6822483SFabien Parent "clk26m_d2", 367a6822483SFabien Parent "clk26m_ck", 368a6822483SFabien Parent "mainpll_d40", 369a6822483SFabien Parent "univpll_d24", 370a6822483SFabien Parent "univpll_d20", 371a6822483SFabien Parent "mainpll_d20", 372a6822483SFabien Parent "mainpll_d16", 373a6822483SFabien Parent "univpll_d12" 374a6822483SFabien Parent }; 375a6822483SFabien Parent 376a6822483SFabien Parent static const char * const msdc2_parents[] __initconst = { 377a6822483SFabien Parent "clk26m_ck", 378a6822483SFabien Parent "univpll_d6", 379a6822483SFabien Parent "mainpll_d8", 380a6822483SFabien Parent "univpll_d8", 381a6822483SFabien Parent "mainpll_d16", 382a6822483SFabien Parent "mmpll_200m", 383a6822483SFabien Parent "mainpll_d12", 384a6822483SFabien Parent "mmpll_d2" 385a6822483SFabien Parent }; 386a6822483SFabien Parent 387a6822483SFabien Parent static const char * const eth_parents[] __initconst = { 388a6822483SFabien Parent "clk26m_ck", 389a6822483SFabien Parent "mainpll_d40", 390a6822483SFabien Parent "univpll_d24", 391a6822483SFabien Parent "univpll_d20", 392a6822483SFabien Parent "mainpll_d20" 393a6822483SFabien Parent }; 394a6822483SFabien Parent 395a6822483SFabien Parent static const char * const vdec_mm_parents[] __initconst = { 396a6822483SFabien Parent "clk26m_ck", 397a6822483SFabien Parent "univpll_d4", 398a6822483SFabien Parent "mainpll_d4", 399a6822483SFabien Parent "univpll_d5", 400a6822483SFabien Parent "univpll_d6", 401a6822483SFabien Parent "mainpll_d6" 402a6822483SFabien Parent }; 403a6822483SFabien Parent 404a6822483SFabien Parent static const char * const dpi0_mm_parents[] __initconst = { 405a6822483SFabien Parent "clk26m_ck", 406a6822483SFabien Parent "lvdspll_ck", 407a6822483SFabien Parent "lvdspll_d2", 408a6822483SFabien Parent "lvdspll_d4", 409a6822483SFabien Parent "lvdspll_d8" 410a6822483SFabien Parent }; 411a6822483SFabien Parent 412a6822483SFabien Parent static const char * const dpi1_mm_parents[] __initconst = { 413a6822483SFabien Parent "clk26m_ck", 414a6822483SFabien Parent "tvdpll_d2", 415a6822483SFabien Parent "tvdpll_d4", 416a6822483SFabien Parent "tvdpll_d8", 417a6822483SFabien Parent "tvdpll_d16" 418a6822483SFabien Parent }; 419a6822483SFabien Parent 420a6822483SFabien Parent static const char * const axi_mfg_in_parents[] __initconst = { 421a6822483SFabien Parent "clk26m_ck", 422a6822483SFabien Parent "mainpll_d11", 423a6822483SFabien Parent "univpll_d24", 424a6822483SFabien Parent "mmpll380m" 425a6822483SFabien Parent }; 426a6822483SFabien Parent 427a6822483SFabien Parent static const char * const slow_mfg_parents[] __initconst = { 428a6822483SFabien Parent "clk26m_ck", 429a6822483SFabien Parent "univpll_d12", 430a6822483SFabien Parent "univpll_d24" 431a6822483SFabien Parent }; 432a6822483SFabien Parent 433a6822483SFabien Parent static const char * const aud1_parents[] __initconst = { 434a6822483SFabien Parent "clk26m_ck", 435a6822483SFabien Parent "apll1_ck" 436a6822483SFabien Parent }; 437a6822483SFabien Parent 438a6822483SFabien Parent static const char * const aud2_parents[] __initconst = { 439a6822483SFabien Parent "clk26m_ck", 440a6822483SFabien Parent "apll2_ck" 441a6822483SFabien Parent }; 442a6822483SFabien Parent 443a6822483SFabien Parent static const char * const aud_engen1_parents[] __initconst = { 444a6822483SFabien Parent "clk26m_ck", 445a6822483SFabien Parent "rg_apll1_d2_en", 446a6822483SFabien Parent "rg_apll1_d4_en", 447a6822483SFabien Parent "rg_apll1_d8_en" 448a6822483SFabien Parent }; 449a6822483SFabien Parent 450a6822483SFabien Parent static const char * const aud_engen2_parents[] __initconst = { 451a6822483SFabien Parent "clk26m_ck", 452a6822483SFabien Parent "rg_apll2_d2_en", 453a6822483SFabien Parent "rg_apll2_d4_en", 454a6822483SFabien Parent "rg_apll2_d8_en" 455a6822483SFabien Parent }; 456a6822483SFabien Parent 457a6822483SFabien Parent static const char * const i2c_parents[] __initconst = { 458a6822483SFabien Parent "clk26m_ck", 459a6822483SFabien Parent "univpll_d20", 460a6822483SFabien Parent "univpll_d16", 461a6822483SFabien Parent "univpll_d12" 462a6822483SFabien Parent }; 463a6822483SFabien Parent 464a6822483SFabien Parent static const char * const aud_i2s0_m_parents[] __initconst = { 465a6822483SFabien Parent "rg_aud1", 466a6822483SFabien Parent "rg_aud2" 467a6822483SFabien Parent }; 468a6822483SFabien Parent 469a6822483SFabien Parent static const char * const pwm_parents[] __initconst = { 470a6822483SFabien Parent "clk26m_ck", 471a6822483SFabien Parent "univpll_d12" 472a6822483SFabien Parent }; 473a6822483SFabien Parent 474a6822483SFabien Parent static const char * const spi_parents[] __initconst = { 475a6822483SFabien Parent "clk26m_ck", 476a6822483SFabien Parent "univpll_d12", 477a6822483SFabien Parent "univpll_d8", 478a6822483SFabien Parent "univpll_d6" 479a6822483SFabien Parent }; 480a6822483SFabien Parent 481a6822483SFabien Parent static const char * const aud_spdifin_parents[] __initconst = { 482a6822483SFabien Parent "clk26m_ck", 483a6822483SFabien Parent "univpll_d2" 484a6822483SFabien Parent }; 485a6822483SFabien Parent 486a6822483SFabien Parent static const char * const uart2_parents[] __initconst = { 487a6822483SFabien Parent "clk26m_ck", 488a6822483SFabien Parent "univpll_d24" 489a6822483SFabien Parent }; 490a6822483SFabien Parent 491a6822483SFabien Parent static const char * const bsi_parents[] __initconst = { 492a6822483SFabien Parent "clk26m_ck", 493a6822483SFabien Parent "mainpll_d10", 494a6822483SFabien Parent "mainpll_d12", 495a6822483SFabien Parent "mainpll_d20" 496a6822483SFabien Parent }; 497a6822483SFabien Parent 498a6822483SFabien Parent static const char * const dbg_atclk_parents[] __initconst = { 499a6822483SFabien Parent "clk_null", 500a6822483SFabien Parent "clk26m_ck", 501a6822483SFabien Parent "mainpll_d5", 502a6822483SFabien Parent "clk_null", 503a6822483SFabien Parent "univpll_d5" 504a6822483SFabien Parent }; 505a6822483SFabien Parent 506a6822483SFabien Parent static const char * const csw_nfiecc_parents[] __initconst = { 507a6822483SFabien Parent "clk_null", 508a6822483SFabien Parent "mainpll_d7", 509a6822483SFabien Parent "mainpll_d6", 510a6822483SFabien Parent "clk_null", 511a6822483SFabien Parent "mainpll_d5" 512a6822483SFabien Parent }; 513a6822483SFabien Parent 514a6822483SFabien Parent static const char * const nfiecc_parents[] __initconst = { 515a6822483SFabien Parent "clk_null", 516a6822483SFabien Parent "nfi2x_pad_sel", 517a6822483SFabien Parent "mainpll_d4", 518a6822483SFabien Parent "clk_null", 519a6822483SFabien Parent "csw_nfiecc_sel" 520a6822483SFabien Parent }; 521a6822483SFabien Parent 522a6822483SFabien Parent static struct mtk_composite top_muxes[] __initdata = { 523a6822483SFabien Parent /* CLK_MUX_SEL0 */ 524a6822483SFabien Parent MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents, 525a6822483SFabien Parent 0x000, 0, 1), 526a6822483SFabien Parent MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents, 527a6822483SFabien Parent 0x000, 1, 1), 528a6822483SFabien Parent MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents, 529a6822483SFabien Parent 0x000, 2, 1), 530a6822483SFabien Parent MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents, 531a6822483SFabien Parent 0x000, 4, 4), 532a6822483SFabien Parent MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents, 533a6822483SFabien Parent 0x000, 8, 3), 534a6822483SFabien Parent MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents, 535a6822483SFabien Parent 0x000, 11, 3), 536a6822483SFabien Parent MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents, 537a6822483SFabien Parent 0x000, 15, 3), 538a6822483SFabien Parent MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents, 539a6822483SFabien Parent 0x000, 18, 1), 540a6822483SFabien Parent MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents, 541a6822483SFabien Parent 0x000, 19, 1), 542a6822483SFabien Parent MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents, 543a6822483SFabien Parent 0x000, 20, 3), 544a6822483SFabien Parent MUX(CLK_TOP_SPM_52M_SEL, "spm_52m_sel", spm_52m_parents, 545a6822483SFabien Parent 0x000, 23, 1), 546a6822483SFabien Parent MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 547a6822483SFabien Parent 0x000, 24, 2), 548a6822483SFabien Parent MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents, 549a6822483SFabien Parent 0x000, 26, 1), 550a6822483SFabien Parent MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 551a6822483SFabien Parent 0x000, 27, 3), 552a6822483SFabien Parent /* CLK_MUX_SEL1 */ 553a6822483SFabien Parent MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents, 554a6822483SFabien Parent 0x004, 0, 7), 555a6822483SFabien Parent MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents, 556a6822483SFabien Parent 0x004, 7, 1), 557a6822483SFabien Parent MUX(CLK_TOP_MFG_MM_SEL, "mfg_mm_sel", mfg_mm_parents, 558a6822483SFabien Parent 0x004, 8, 6), 559a6822483SFabien Parent MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 560a6822483SFabien Parent 0x004, 15, 1), 561a6822483SFabien Parent MUX(CLK_TOP_SMI_MM_SEL, "smi_mm_sel", smi_mm_parents, 562a6822483SFabien Parent 0x004, 16, 4), 563a6822483SFabien Parent MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents, 564a6822483SFabien Parent 0x004, 20, 3), 565a6822483SFabien Parent MUX(CLK_TOP_SCAM_MM_SEL, "scam_mm_sel", scam_mm_parents, 566a6822483SFabien Parent 0x004, 23, 3), 567a6822483SFabien Parent /* CLK_MUX_SEL8 */ 568a6822483SFabien Parent MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents, 569a6822483SFabien Parent 0x040, 0, 3), 570a6822483SFabien Parent MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents, 571a6822483SFabien Parent 0x040, 3, 3), 572a6822483SFabien Parent MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 573a6822483SFabien Parent 0x040, 6, 3), 574a6822483SFabien Parent MUX(CLK_TOP_VDEC_MM_SEL, "vdec_mm_sel", vdec_mm_parents, 575a6822483SFabien Parent 0x040, 9, 3), 576a6822483SFabien Parent MUX(CLK_TOP_DPI0_MM_SEL, "dpi0_mm_sel", dpi0_mm_parents, 577a6822483SFabien Parent 0x040, 12, 3), 578a6822483SFabien Parent MUX(CLK_TOP_DPI1_MM_SEL, "dpi1_mm_sel", dpi1_mm_parents, 579a6822483SFabien Parent 0x040, 15, 3), 580a6822483SFabien Parent MUX(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 581a6822483SFabien Parent 0x040, 18, 2), 582a6822483SFabien Parent MUX(CLK_TOP_SLOW_MFG_SEL, "slow_mfg_sel", slow_mfg_parents, 583a6822483SFabien Parent 0x040, 20, 2), 584a6822483SFabien Parent MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, 585a6822483SFabien Parent 0x040, 22, 1), 586a6822483SFabien Parent MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents, 587a6822483SFabien Parent 0x040, 23, 1), 588a6822483SFabien Parent MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents, 589a6822483SFabien Parent 0x040, 24, 2), 590a6822483SFabien Parent MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents, 591a6822483SFabien Parent 0x040, 26, 2), 592a6822483SFabien Parent MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 593a6822483SFabien Parent 0x040, 28, 2), 594a6822483SFabien Parent /* CLK_SEL_9 */ 595a6822483SFabien Parent MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents, 596a6822483SFabien Parent 0x044, 12, 1), 597a6822483SFabien Parent MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents, 598a6822483SFabien Parent 0x044, 13, 1), 599a6822483SFabien Parent MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents, 600a6822483SFabien Parent 0x044, 14, 1), 601a6822483SFabien Parent MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents, 602a6822483SFabien Parent 0x044, 15, 1), 603a6822483SFabien Parent MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents, 604a6822483SFabien Parent 0x044, 16, 1), 605a6822483SFabien Parent MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents, 606a6822483SFabien Parent 0x044, 17, 1), 607a6822483SFabien Parent MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents, 608a6822483SFabien Parent 0x044, 18, 1), 609a6822483SFabien Parent /* CLK_MUX_SEL13 */ 610a6822483SFabien Parent MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 611a6822483SFabien Parent 0x07c, 0, 1), 612a6822483SFabien Parent MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 613a6822483SFabien Parent 0x07c, 1, 2), 614a6822483SFabien Parent MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents, 615a6822483SFabien Parent 0x07c, 3, 1), 616a6822483SFabien Parent MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents, 617a6822483SFabien Parent 0x07c, 4, 1), 618a6822483SFabien Parent MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents, 619a6822483SFabien Parent 0x07c, 5, 2), 620a6822483SFabien Parent MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents, 621a6822483SFabien Parent 0x07c, 7, 3), 622a6822483SFabien Parent MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents, 623a6822483SFabien Parent 0x07c, 10, 3), 624a6822483SFabien Parent MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 625a6822483SFabien Parent 0x07c, 13, 3), 626a6822483SFabien Parent }; 627a6822483SFabien Parent 628a6822483SFabien Parent static const char * const ifr_mux1_parents[] __initconst = { 629a6822483SFabien Parent "clk26m_ck", 630a6822483SFabien Parent "armpll", 631a6822483SFabien Parent "univpll", 632a6822483SFabien Parent "mainpll_d2" 633a6822483SFabien Parent }; 634a6822483SFabien Parent 635a6822483SFabien Parent static const char * const ifr_eth_25m_parents[] __initconst = { 636a6822483SFabien Parent "eth_d2_ck", 637a6822483SFabien Parent "rg_eth" 638a6822483SFabien Parent }; 639a6822483SFabien Parent 640a6822483SFabien Parent static const char * const ifr_i2c0_parents[] __initconst = { 641a6822483SFabien Parent "ahb_infra_d2", 642a6822483SFabien Parent "rg_i2c" 643a6822483SFabien Parent }; 644a6822483SFabien Parent 645a6822483SFabien Parent static const struct mtk_composite ifr_muxes[] __initconst = { 646a6822483SFabien Parent MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000, 647a6822483SFabien Parent 2, 2), 648a6822483SFabien Parent MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080, 649a6822483SFabien Parent 0, 1), 650a6822483SFabien Parent MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080, 651a6822483SFabien Parent 1, 1), 652a6822483SFabien Parent MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080, 653a6822483SFabien Parent 2, 1), 654a6822483SFabien Parent MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080, 655a6822483SFabien Parent 3, 1), 656a6822483SFabien Parent }; 657a6822483SFabien Parent 658a6822483SFabien Parent #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ 659a6822483SFabien Parent .id = _id, \ 660a6822483SFabien Parent .name = _name, \ 661a6822483SFabien Parent .parent_name = _parent, \ 662a6822483SFabien Parent .div_reg = _reg, \ 663a6822483SFabien Parent .div_shift = _shift, \ 664a6822483SFabien Parent .div_width = _width, \ 665a6822483SFabien Parent } 666a6822483SFabien Parent 667a6822483SFabien Parent static const struct mtk_clk_divider top_adj_divs[] = { 668a6822483SFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel", 669a6822483SFabien Parent 0x0048, 0, 8), 670a6822483SFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel", 671a6822483SFabien Parent 0x0048, 8, 8), 672a6822483SFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel", 673a6822483SFabien Parent 0x0048, 16, 8), 674a6822483SFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel", 675a6822483SFabien Parent 0x0048, 24, 8), 676a6822483SFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel", 677a6822483SFabien Parent 0x004c, 0, 8), 678a6822483SFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4", 679a6822483SFabien Parent 0x004c, 8, 8), 680a6822483SFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel", 681a6822483SFabien Parent 0x004c, 16, 8), 682a6822483SFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5", 683a6822483SFabien Parent 0x004c, 24, 8), 684a6822483SFabien Parent DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel", 685a6822483SFabien Parent 0x0078, 0, 8), 686a6822483SFabien Parent }; 687a6822483SFabien Parent 688a6822483SFabien Parent #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ 689a6822483SFabien Parent .id = _id, \ 690a6822483SFabien Parent .name = _name, \ 691a6822483SFabien Parent .parent_name = _parent, \ 692a6822483SFabien Parent .div_reg = _reg, \ 693a6822483SFabien Parent .div_shift = _shift, \ 694a6822483SFabien Parent .div_width = _width, \ 695a6822483SFabien Parent .clk_divider_flags = _flag, \ 696a6822483SFabien Parent } 697a6822483SFabien Parent 698a6822483SFabien Parent static const struct mtk_clk_divider apmixed_adj_divs[] = { 699a6822483SFabien Parent DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 700a6822483SFabien Parent 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO), 701a6822483SFabien Parent }; 702a6822483SFabien Parent 703a6822483SFabien Parent static const struct mtk_gate_regs top0_cg_regs = { 704a6822483SFabien Parent .set_ofs = 0x50, 705a6822483SFabien Parent .clr_ofs = 0x80, 706a6822483SFabien Parent .sta_ofs = 0x20, 707a6822483SFabien Parent }; 708a6822483SFabien Parent 709a6822483SFabien Parent static const struct mtk_gate_regs top1_cg_regs = { 710a6822483SFabien Parent .set_ofs = 0x54, 711a6822483SFabien Parent .clr_ofs = 0x84, 712a6822483SFabien Parent .sta_ofs = 0x24, 713a6822483SFabien Parent }; 714a6822483SFabien Parent 715a6822483SFabien Parent static const struct mtk_gate_regs top2_cg_regs = { 716a6822483SFabien Parent .set_ofs = 0x6c, 717a6822483SFabien Parent .clr_ofs = 0x9c, 718a6822483SFabien Parent .sta_ofs = 0x3c, 719a6822483SFabien Parent }; 720a6822483SFabien Parent 721a6822483SFabien Parent static const struct mtk_gate_regs top3_cg_regs = { 722a6822483SFabien Parent .set_ofs = 0xa0, 723a6822483SFabien Parent .clr_ofs = 0xb0, 724a6822483SFabien Parent .sta_ofs = 0x70, 725a6822483SFabien Parent }; 726a6822483SFabien Parent 727a6822483SFabien Parent static const struct mtk_gate_regs top4_cg_regs = { 728a6822483SFabien Parent .set_ofs = 0xa4, 729a6822483SFabien Parent .clr_ofs = 0xb4, 730a6822483SFabien Parent .sta_ofs = 0x74, 731a6822483SFabien Parent }; 732a6822483SFabien Parent 733a6822483SFabien Parent static const struct mtk_gate_regs top5_cg_regs = { 734a6822483SFabien Parent .set_ofs = 0x44, 735a6822483SFabien Parent .clr_ofs = 0x44, 736a6822483SFabien Parent .sta_ofs = 0x44, 737a6822483SFabien Parent }; 738a6822483SFabien Parent 739a6822483SFabien Parent #define GATE_TOP0(_id, _name, _parent, _shift) { \ 740a6822483SFabien Parent .id = _id, \ 741a6822483SFabien Parent .name = _name, \ 742a6822483SFabien Parent .parent_name = _parent, \ 743a6822483SFabien Parent .regs = &top0_cg_regs, \ 744a6822483SFabien Parent .shift = _shift, \ 745a6822483SFabien Parent .ops = &mtk_clk_gate_ops_setclr, \ 746a6822483SFabien Parent } 747a6822483SFabien Parent 748a6822483SFabien Parent #define GATE_TOP0_I(_id, _name, _parent, _shift) { \ 749a6822483SFabien Parent .id = _id, \ 750a6822483SFabien Parent .name = _name, \ 751a6822483SFabien Parent .parent_name = _parent, \ 752a6822483SFabien Parent .regs = &top0_cg_regs, \ 753a6822483SFabien Parent .shift = _shift, \ 754a6822483SFabien Parent .ops = &mtk_clk_gate_ops_setclr_inv, \ 755a6822483SFabien Parent } 756a6822483SFabien Parent 757a6822483SFabien Parent #define GATE_TOP1(_id, _name, _parent, _shift) { \ 758a6822483SFabien Parent .id = _id, \ 759a6822483SFabien Parent .name = _name, \ 760a6822483SFabien Parent .parent_name = _parent, \ 761a6822483SFabien Parent .regs = &top1_cg_regs, \ 762a6822483SFabien Parent .shift = _shift, \ 763a6822483SFabien Parent .ops = &mtk_clk_gate_ops_setclr, \ 764a6822483SFabien Parent } 765a6822483SFabien Parent 766a6822483SFabien Parent #define GATE_TOP2(_id, _name, _parent, _shift) { \ 767a6822483SFabien Parent .id = _id, \ 768a6822483SFabien Parent .name = _name, \ 769a6822483SFabien Parent .parent_name = _parent, \ 770a6822483SFabien Parent .regs = &top2_cg_regs, \ 771a6822483SFabien Parent .shift = _shift, \ 772a6822483SFabien Parent .ops = &mtk_clk_gate_ops_setclr, \ 773a6822483SFabien Parent } 774a6822483SFabien Parent 775a6822483SFabien Parent #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ 776a6822483SFabien Parent .id = _id, \ 777a6822483SFabien Parent .name = _name, \ 778a6822483SFabien Parent .parent_name = _parent, \ 779a6822483SFabien Parent .regs = &top2_cg_regs, \ 780a6822483SFabien Parent .shift = _shift, \ 781a6822483SFabien Parent .ops = &mtk_clk_gate_ops_setclr_inv, \ 782a6822483SFabien Parent } 783a6822483SFabien Parent 784a6822483SFabien Parent #define GATE_TOP3(_id, _name, _parent, _shift) { \ 785a6822483SFabien Parent .id = _id, \ 786a6822483SFabien Parent .name = _name, \ 787a6822483SFabien Parent .parent_name = _parent, \ 788a6822483SFabien Parent .regs = &top3_cg_regs, \ 789a6822483SFabien Parent .shift = _shift, \ 790a6822483SFabien Parent .ops = &mtk_clk_gate_ops_setclr, \ 791a6822483SFabien Parent } 792a6822483SFabien Parent 793a6822483SFabien Parent #define GATE_TOP4_I(_id, _name, _parent, _shift) { \ 794a6822483SFabien Parent .id = _id, \ 795a6822483SFabien Parent .name = _name, \ 796a6822483SFabien Parent .parent_name = _parent, \ 797a6822483SFabien Parent .regs = &top4_cg_regs, \ 798a6822483SFabien Parent .shift = _shift, \ 799a6822483SFabien Parent .ops = &mtk_clk_gate_ops_setclr_inv, \ 800a6822483SFabien Parent } 801a6822483SFabien Parent 802a6822483SFabien Parent #define GATE_TOP5(_id, _name, _parent, _shift) { \ 803a6822483SFabien Parent .id = _id, \ 804a6822483SFabien Parent .name = _name, \ 805a6822483SFabien Parent .parent_name = _parent, \ 806a6822483SFabien Parent .regs = &top5_cg_regs, \ 807a6822483SFabien Parent .shift = _shift, \ 808a6822483SFabien Parent .ops = &mtk_clk_gate_ops_no_setclr, \ 809a6822483SFabien Parent } 810a6822483SFabien Parent 811a6822483SFabien Parent static const struct mtk_gate top_clks[] __initconst = { 812a6822483SFabien Parent /* TOP0 */ 813a6822483SFabien Parent GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0), 814a6822483SFabien Parent GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1), 815a6822483SFabien Parent GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2), 816a6822483SFabien Parent GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3), 817a6822483SFabien Parent GATE_TOP0_I(CLK_TOP_MIPI_26M_DBG, "mipi_26m_dbg", "mipi_26m", 4), 818a6822483SFabien Parent GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5), 819a6822483SFabien Parent GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9), 820a6822483SFabien Parent /* TOP1 */ 821a6822483SFabien Parent GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1), 822a6822483SFabien Parent GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2), 823a6822483SFabien Parent GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3), 824a6822483SFabien Parent GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4), 825a6822483SFabien Parent GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5), 826a6822483SFabien Parent GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6), 827a6822483SFabien Parent GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7), 828a6822483SFabien Parent GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8), 829a6822483SFabien Parent GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9), 830a6822483SFabien Parent GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10), 831a6822483SFabien Parent GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11), 832a6822483SFabien Parent GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12), 833a6822483SFabien Parent GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13), 834a6822483SFabien Parent GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14), 835a6822483SFabien Parent GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15), 836a6822483SFabien Parent GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16), 837a6822483SFabien Parent GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17), 838a6822483SFabien Parent GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18), 839a6822483SFabien Parent GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19), 840a6822483SFabien Parent GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20), 841a6822483SFabien Parent GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21), 842a6822483SFabien Parent GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22), 843a6822483SFabien Parent GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23), 844a6822483SFabien Parent GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24), 845a6822483SFabien Parent GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25), 846a6822483SFabien Parent GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27), 847a6822483SFabien Parent GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28), 848a6822483SFabien Parent GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29), 849a6822483SFabien Parent GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30), 850a6822483SFabien Parent GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31), 851a6822483SFabien Parent /* TOP2 */ 852a6822483SFabien Parent GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0), 853a6822483SFabien Parent GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1), 854a6822483SFabien Parent GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2), 855a6822483SFabien Parent GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4), 856a6822483SFabien Parent GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5), 857a6822483SFabien Parent GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6), 858a6822483SFabien Parent GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7), 859a6822483SFabien Parent GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8), 860a6822483SFabien Parent GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9), 861a6822483SFabien Parent GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10), 862a6822483SFabien Parent GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11), 863a6822483SFabien Parent GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12), 864a6822483SFabien Parent GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13), 865a6822483SFabien Parent GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14), 866a6822483SFabien Parent GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel", 867a6822483SFabien Parent 15), 868a6822483SFabien Parent GATE_TOP2(CLK_TOP_26M_HDMI_SIFM, "hdmi_sifm_26m", "clk26m_ck", 16), 869a6822483SFabien Parent GATE_TOP2(CLK_TOP_26M_CEC, "cec_26m", "clk26m_ck", 17), 870a6822483SFabien Parent GATE_TOP2(CLK_TOP_32K_CEC, "cec_32k", "clk32k", 18), 871a6822483SFabien Parent GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19), 872a6822483SFabien Parent GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20), 873a6822483SFabien Parent GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21), 874a6822483SFabien Parent GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22), 875a6822483SFabien Parent GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23), 876a6822483SFabien Parent GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24), 877a6822483SFabien Parent GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25), 878a6822483SFabien Parent GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26), 879a6822483SFabien Parent GATE_TOP2(CLK_TOP_GCPU_B, "gcpu_b", "ahb_infra_sel", 27), 880a6822483SFabien Parent GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28), 881a6822483SFabien Parent GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29), 882a6822483SFabien Parent GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30), 883a6822483SFabien Parent GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31), 884a6822483SFabien Parent /* TOP3 */ 885a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0), 886a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1), 887a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2), 888a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_VDEC, "rg_vdec", "vdec_mm_sel", 3), 889a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_FDPI0, "rg_fdpi0", "dpi0_mm_sel", 4), 890a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_FDPI1, "rg_fdpi1", "dpi1_mm_sel", 5), 891a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_AXI_MFG, "rg_axi_mfg", "axi_mfg_in_sel", 6), 892a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_SLOW_MFG, "rg_slow_mfg", "slow_mfg_sel", 7), 893a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8), 894a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9), 895a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10), 896a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11), 897a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12), 898a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13), 899a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel", 900a6822483SFabien Parent 14), 901a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15), 902a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16), 903a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17), 904a6822483SFabien Parent GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18), 905a6822483SFabien Parent /* TOP4 */ 906a6822483SFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8), 907a6822483SFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9), 908a6822483SFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10), 909a6822483SFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11), 910a6822483SFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12), 911a6822483SFabien Parent GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13), 912a6822483SFabien Parent /* TOP5 */ 913a6822483SFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0), 914a6822483SFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1), 915a6822483SFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2), 916a6822483SFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3), 917a6822483SFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4), 918a6822483SFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5), 919a6822483SFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6), 920a6822483SFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7), 921a6822483SFabien Parent GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8), 922a6822483SFabien Parent }; 923a6822483SFabien Parent 924a6822483SFabien Parent static void __init mtk_topckgen_init(struct device_node *node) 925a6822483SFabien Parent { 926a6822483SFabien Parent struct clk_onecell_data *clk_data; 927a6822483SFabien Parent int r; 928a6822483SFabien Parent void __iomem *base; 929a6822483SFabien Parent 930a6822483SFabien Parent base = of_iomap(node, 0); 931a6822483SFabien Parent if (!base) { 932a6822483SFabien Parent pr_err("%s(): ioremap failed\n", __func__); 933a6822483SFabien Parent return; 934a6822483SFabien Parent } 935a6822483SFabien Parent 936a6822483SFabien Parent clk_data = mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK); 937a6822483SFabien Parent 938a6822483SFabien Parent mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), 939a6822483SFabien Parent clk_data); 940a6822483SFabien Parent mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data); 941a6822483SFabien Parent 942a6822483SFabien Parent mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 943a6822483SFabien Parent mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, 944a6822483SFabien Parent &mt8167_clk_lock, clk_data); 945a6822483SFabien Parent mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 946a6822483SFabien Parent base, &mt8167_clk_lock, clk_data); 947a6822483SFabien Parent 948a6822483SFabien Parent r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 949a6822483SFabien Parent if (r) 950a6822483SFabien Parent pr_err("%s(): could not register clock provider: %d\n", 951a6822483SFabien Parent __func__, r); 952a6822483SFabien Parent } 953a6822483SFabien Parent CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init); 954a6822483SFabien Parent 955a6822483SFabien Parent static void __init mtk_infracfg_init(struct device_node *node) 956a6822483SFabien Parent { 957a6822483SFabien Parent struct clk_onecell_data *clk_data; 958a6822483SFabien Parent int r; 959a6822483SFabien Parent void __iomem *base; 960a6822483SFabien Parent 961a6822483SFabien Parent base = of_iomap(node, 0); 962a6822483SFabien Parent if (!base) { 963a6822483SFabien Parent pr_err("%s(): ioremap failed\n", __func__); 964a6822483SFabien Parent return; 965a6822483SFabien Parent } 966a6822483SFabien Parent 967a6822483SFabien Parent clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); 968a6822483SFabien Parent 969a6822483SFabien Parent mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base, 970a6822483SFabien Parent &mt8167_clk_lock, clk_data); 971a6822483SFabien Parent 972a6822483SFabien Parent r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 973a6822483SFabien Parent if (r) 974a6822483SFabien Parent pr_err("%s(): could not register clock provider: %d\n", 975a6822483SFabien Parent __func__, r); 976a6822483SFabien Parent } 977a6822483SFabien Parent CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init); 978a6822483SFabien Parent 979a6822483SFabien Parent #define MT8167_PLL_FMAX (2500UL * MHZ) 980a6822483SFabien Parent 981a6822483SFabien Parent #define CON0_MT8167_RST_BAR BIT(27) 982a6822483SFabien Parent 983a6822483SFabien Parent #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 984a6822483SFabien Parent _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 985a6822483SFabien Parent _pcw_shift, _div_table) { \ 986a6822483SFabien Parent .id = _id, \ 987a6822483SFabien Parent .name = _name, \ 988a6822483SFabien Parent .reg = _reg, \ 989a6822483SFabien Parent .pwr_reg = _pwr_reg, \ 990a6822483SFabien Parent .en_mask = _en_mask, \ 991a6822483SFabien Parent .flags = _flags, \ 992a6822483SFabien Parent .rst_bar_mask = CON0_MT8167_RST_BAR, \ 993a6822483SFabien Parent .fmax = MT8167_PLL_FMAX, \ 994a6822483SFabien Parent .pcwbits = _pcwbits, \ 995a6822483SFabien Parent .pd_reg = _pd_reg, \ 996a6822483SFabien Parent .pd_shift = _pd_shift, \ 997a6822483SFabien Parent .tuner_reg = _tuner_reg, \ 998a6822483SFabien Parent .pcw_reg = _pcw_reg, \ 999a6822483SFabien Parent .pcw_shift = _pcw_shift, \ 1000a6822483SFabien Parent .div_table = _div_table, \ 1001a6822483SFabien Parent } 1002a6822483SFabien Parent 1003a6822483SFabien Parent #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 1004a6822483SFabien Parent _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 1005a6822483SFabien Parent _pcw_shift) \ 1006a6822483SFabien Parent PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 1007a6822483SFabien Parent _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 1008a6822483SFabien Parent NULL) 1009a6822483SFabien Parent 1010a6822483SFabien Parent static const struct mtk_pll_div_table mmpll_div_table[] = { 1011a6822483SFabien Parent { .div = 0, .freq = MT8167_PLL_FMAX }, 1012a6822483SFabien Parent { .div = 1, .freq = 1000000000 }, 1013a6822483SFabien Parent { .div = 2, .freq = 604500000 }, 1014a6822483SFabien Parent { .div = 3, .freq = 253500000 }, 1015a6822483SFabien Parent { .div = 4, .freq = 126750000 }, 1016a6822483SFabien Parent { } /* sentinel */ 1017a6822483SFabien Parent }; 1018a6822483SFabien Parent 1019a6822483SFabien Parent static const struct mtk_pll_data plls[] = { 1020*e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, 1021a6822483SFabien Parent 21, 0x0104, 24, 0, 0x0104, 0), 1022*e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, 1023a6822483SFabien Parent HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), 1024*e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, 1025a6822483SFabien Parent HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), 1026*e1fd35f5SChun-Jie Chen PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, 1027a6822483SFabien Parent 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), 1028*e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, 1029a6822483SFabien Parent 31, 0x0180, 1, 0x0194, 0x0184, 0), 1030*e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, 1031a6822483SFabien Parent 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), 1032*e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0, 1033a6822483SFabien Parent 21, 0x01C4, 24, 0, 0x01C4, 0), 1034*e1fd35f5SChun-Jie Chen PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0, 1035a6822483SFabien Parent 21, 0x01E4, 24, 0, 0x01E4, 0), 1036a6822483SFabien Parent }; 1037a6822483SFabien Parent 1038a6822483SFabien Parent static void __init mtk_apmixedsys_init(struct device_node *node) 1039a6822483SFabien Parent { 1040a6822483SFabien Parent struct clk_onecell_data *clk_data; 1041a6822483SFabien Parent void __iomem *base; 1042a6822483SFabien Parent int r; 1043a6822483SFabien Parent 1044a6822483SFabien Parent base = of_iomap(node, 0); 1045a6822483SFabien Parent if (!base) { 1046a6822483SFabien Parent pr_err("%s(): ioremap failed\n", __func__); 1047a6822483SFabien Parent return; 1048a6822483SFabien Parent } 1049a6822483SFabien Parent 1050a6822483SFabien Parent clk_data = mtk_alloc_clk_data(MT8167_CLK_APMIXED_NR_CLK); 1051a6822483SFabien Parent 1052a6822483SFabien Parent mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1053a6822483SFabien Parent mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs), 1054a6822483SFabien Parent base, &mt8167_clk_lock, clk_data); 1055a6822483SFabien Parent 1056a6822483SFabien Parent r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1057a6822483SFabien Parent if (r) 1058a6822483SFabien Parent pr_err("%s(): could not register clock provider: %d\n", 1059a6822483SFabien Parent __func__, r); 1060a6822483SFabien Parent 1061a6822483SFabien Parent } 1062a6822483SFabien Parent CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8167-apmixedsys", 1063a6822483SFabien Parent mtk_apmixedsys_init); 1064