1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 MediaTek Inc. 4 * Copyright (c) 2020 BayLibre, SAS 5 * Author: James Liao <jamesjj.liao@mediatek.com> 6 * Fabien Parent <fparent@baylibre.com> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 15 #include "clk-mtk.h" 16 #include "clk-gate.h" 17 18 #include <dt-bindings/clock/mt8167-clk.h> 19 20 static const struct mtk_gate_regs mm0_cg_regs = { 21 .set_ofs = 0x104, 22 .clr_ofs = 0x108, 23 .sta_ofs = 0x100, 24 }; 25 26 static const struct mtk_gate_regs mm1_cg_regs = { 27 .set_ofs = 0x114, 28 .clr_ofs = 0x118, 29 .sta_ofs = 0x110, 30 }; 31 32 #define GATE_MM0(_id, _name, _parent, _shift) \ 33 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 34 35 #define GATE_MM1(_id, _name, _parent, _shift) \ 36 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 37 38 static const struct mtk_gate mm_clks[] = { 39 /* MM0 */ 40 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "smi_mm", 0), 41 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1), 42 GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "smi_mm", 2), 43 GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "smi_mm", 3), 44 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4), 45 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5), 46 GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "smi_mm", 6), 47 GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "smi_mm", 7), 48 GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "smi_mm", 8), 49 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "smi_mm", 9), 50 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10), 51 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11), 52 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "smi_mm", 12), 53 GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "smi_mm", 13), 54 GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "smi_mm", 14), 55 GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "smi_mm", 15), 56 GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "smi_mm", 16), 57 GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "smi_mm", 17), 58 GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "smi_mm", 18), 59 GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "smi_mm", 19), 60 /* MM1 */ 61 GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm_mm", "smi_mm", 0), 62 GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm_26m", "smi_mm", 1), 63 GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi_engine", "smi_mm", 2), 64 GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi_digital", "dsi0_lntc_dsick", 3), 65 GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi0_engine", "smi_mm", 4), 66 GATE_MM1(CLK_MM_DPI0_PXL, "mm_dpi0_pxl", "rg_fdpi0", 5), 67 GATE_MM1(CLK_MM_LVDS_PXL, "mm_lvds_pxl", "vpll_dpix", 14), 68 GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 15), 69 GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "smi_mm", 16), 70 GATE_MM1(CLK_MM_DPI1_PXL, "mm_dpi1_pxl", "rg_fdpi1", 17), 71 GATE_MM1(CLK_MM_HDMI_PXL, "mm_hdmi_pxl", "rg_fdpi1", 18), 72 GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll12_div6", 19), 73 GATE_MM1(CLK_MM_HDMI_ADSP_BCK, "mm_hdmi_adsp_b", "apll12_div4b", 20), 74 GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21), 75 }; 76 77 static const struct mtk_clk_desc mm_desc = { 78 .clks = mm_clks, 79 .num_clks = ARRAY_SIZE(mm_clks), 80 }; 81 82 static const struct platform_device_id clk_mt8167_mm_id_table[] = { 83 { .name = "clk-mt8167-mm", .driver_data = (kernel_ulong_t)&mm_desc }, 84 { /* sentinel */ } 85 }; 86 MODULE_DEVICE_TABLE(platform, clk_mt8167_mm_id_table); 87 88 static struct platform_driver clk_mt8167_mm_drv = { 89 .probe = mtk_clk_pdev_probe, 90 .remove_new = mtk_clk_pdev_remove, 91 .driver = { 92 .name = "clk-mt8167-mm", 93 }, 94 .id_table = clk_mt8167_mm_id_table, 95 }; 96 module_platform_driver(clk_mt8167_mm_drv); 97 MODULE_LICENSE("GPL"); 98