1a6822483SFabien Parent // SPDX-License-Identifier: GPL-2.0 2a6822483SFabien Parent /* 3a6822483SFabien Parent * Copyright (c) 2020 MediaTek Inc. 4a6822483SFabien Parent * Copyright (c) 2020 BayLibre, SAS 5a6822483SFabien Parent * Author: James Liao <jamesjj.liao@mediatek.com> 6a6822483SFabien Parent * Fabien Parent <fparent@baylibre.com> 7a6822483SFabien Parent */ 8a6822483SFabien Parent 9a6822483SFabien Parent #include <linux/clk-provider.h> 10a6822483SFabien Parent #include <linux/of.h> 11a6822483SFabien Parent #include <linux/of_address.h> 12a6822483SFabien Parent #include <linux/of_device.h> 13a6822483SFabien Parent #include <linux/platform_device.h> 14a6822483SFabien Parent 15a6822483SFabien Parent #include "clk-mtk.h" 16a6822483SFabien Parent #include "clk-gate.h" 17a6822483SFabien Parent 18a6822483SFabien Parent #include <dt-bindings/clock/mt8167-clk.h> 19a6822483SFabien Parent 20a6822483SFabien Parent static const struct mtk_gate_regs aud_cg_regs = { 21a6822483SFabien Parent .set_ofs = 0x0, 22a6822483SFabien Parent .clr_ofs = 0x0, 23a6822483SFabien Parent .sta_ofs = 0x0, 24a6822483SFabien Parent }; 25a6822483SFabien Parent 26a6822483SFabien Parent #define GATE_AUD(_id, _name, _parent, _shift) { \ 27a6822483SFabien Parent .id = _id, \ 28a6822483SFabien Parent .name = _name, \ 29a6822483SFabien Parent .parent_name = _parent, \ 30a6822483SFabien Parent .regs = &aud_cg_regs, \ 31a6822483SFabien Parent .shift = _shift, \ 32a6822483SFabien Parent .ops = &mtk_clk_gate_ops_no_setclr, \ 33a6822483SFabien Parent } 34a6822483SFabien Parent 35b4bd678fSAngeloGioacchino Del Regno static const struct mtk_gate aud_clks[] = { 36a6822483SFabien Parent GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), 37a6822483SFabien Parent GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6), 38a6822483SFabien Parent GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8), 39a6822483SFabien Parent GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9), 40a6822483SFabien Parent GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15), 41a6822483SFabien Parent GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18), 42a6822483SFabien Parent GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19), 43a6822483SFabien Parent GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20), 44a6822483SFabien Parent GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21), 45a6822483SFabien Parent GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24), 46a6822483SFabien Parent GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25), 47a6822483SFabien Parent GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26), 48a6822483SFabien Parent GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27), 49a6822483SFabien Parent }; 50a6822483SFabien Parent 51*beb47f19SAngeloGioacchino Del Regno static const struct mtk_clk_desc aud_desc = { 52*beb47f19SAngeloGioacchino Del Regno .clks = aud_clks, 53*beb47f19SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(aud_clks), 54*beb47f19SAngeloGioacchino Del Regno }; 55a6822483SFabien Parent 56*beb47f19SAngeloGioacchino Del Regno static const struct of_device_id of_match_clk_mt8167_audsys[] = { 57*beb47f19SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8167-audsys", .data = &aud_desc }, 58*beb47f19SAngeloGioacchino Del Regno { /* sentinel */ } 59*beb47f19SAngeloGioacchino Del Regno }; 60a6822483SFabien Parent 61*beb47f19SAngeloGioacchino Del Regno static struct platform_driver clk_mt8167_audsys_drv = { 62*beb47f19SAngeloGioacchino Del Regno .probe = mtk_clk_simple_probe, 63*beb47f19SAngeloGioacchino Del Regno .remove = mtk_clk_simple_remove, 64*beb47f19SAngeloGioacchino Del Regno .driver = { 65*beb47f19SAngeloGioacchino Del Regno .name = "clk-mt8167-audsys", 66*beb47f19SAngeloGioacchino Del Regno .of_match_table = of_match_clk_mt8167_audsys, 67*beb47f19SAngeloGioacchino Del Regno }, 68*beb47f19SAngeloGioacchino Del Regno }; 69*beb47f19SAngeloGioacchino Del Regno module_platform_driver(clk_mt8167_audsys_drv); 70