11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2a8aede79SJames Liao /* 3a8aede79SJames Liao * Copyright (c) 2014 MediaTek Inc. 4a8aede79SJames Liao * Author: James Liao <jamesjj.liao@mediatek.com> 5*f4f9a9c0SAngeloGioacchino Del Regno * Copyright (c) 2023 Collabora, Ltd. 6*f4f9a9c0SAngeloGioacchino Del Regno * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 7a8aede79SJames Liao */ 8a8aede79SJames Liao 9c726639bSStephen Boyd #include <linux/clk.h> 10a8aede79SJames Liao #include <linux/of.h> 11a8aede79SJames Liao #include <linux/of_address.h> 12a8aede79SJames Liao #include <linux/slab.h> 13a8aede79SJames Liao #include <linux/mfd/syscon.h> 14a8aede79SJames Liao #include <dt-bindings/clock/mt8135-clk.h> 15a8aede79SJames Liao 16a8aede79SJames Liao #include "clk-gate.h" 1739691fb6SChen-Yu Tsai #include "clk-mtk.h" 1839691fb6SChen-Yu Tsai #include "clk-pll.h" 19a8aede79SJames Liao 20a8aede79SJames Liao static DEFINE_SPINLOCK(mt8135_clk_lock); 21a8aede79SJames Liao 22a8aede79SJames Liao static const struct mtk_fixed_factor root_clk_alias[] __initconst = { 23a8aede79SJames Liao FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), 24a8aede79SJames Liao FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), 25a8aede79SJames Liao FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), 26a8aede79SJames Liao FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), 27a8aede79SJames Liao }; 28a8aede79SJames Liao 29a8aede79SJames Liao static const struct mtk_fixed_factor top_divs[] __initconst = { 30a8aede79SJames Liao FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2), 31a8aede79SJames Liao FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3), 32a8aede79SJames Liao FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5), 33a8aede79SJames Liao FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7), 34a8aede79SJames Liao 35a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2), 36a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3), 37a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5), 38a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7), 39a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26), 40a8aede79SJames Liao 41a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 42a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3), 43a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 44a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 45a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2), 46a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2), 47a8aede79SJames Liao 48a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1), 49a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2), 50a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3), 51a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4), 52a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5), 53a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6), 54a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8), 55a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12), 56a8aede79SJames Liao 57a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1), 58a8aede79SJames Liao 59a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1), 60a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1), 61a8aede79SJames Liao 62a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1), 63a8aede79SJames Liao 64a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2), 65a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4), 66a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6), 67a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8), 68a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10), 69a8aede79SJames Liao 70a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2), 71a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4), 72a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6), 73a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8), 74a8aede79SJames Liao 75a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1), 76a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1), 77a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1), 78a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2), 79a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1), 80a8aede79SJames Liao 81a8aede79SJames Liao FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1), 82a8aede79SJames Liao FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4), 83a8aede79SJames Liao FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8), 84a8aede79SJames Liao FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16), 85a8aede79SJames Liao FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24), 86a8aede79SJames Liao 87a8aede79SJames Liao FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 88a8aede79SJames Liao FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 89a8aede79SJames Liao FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 90a8aede79SJames Liao 91a8aede79SJames Liao FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1), 92a8aede79SJames Liao FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1), 93a8aede79SJames Liao 94a8aede79SJames Liao FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1), 95a8aede79SJames Liao 96a8aede79SJames Liao FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2), 97a8aede79SJames Liao FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3), 98a8aede79SJames Liao 99a8aede79SJames Liao FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2), 100a8aede79SJames Liao FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4), 101a8aede79SJames Liao 102a8aede79SJames Liao FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), 103a8aede79SJames Liao }; 104a8aede79SJames Liao 105a8aede79SJames Liao static const char * const axi_parents[] __initconst = { 106a8aede79SJames Liao "clk26m", 107a8aede79SJames Liao "syspll_d3", 108a8aede79SJames Liao "syspll_d4", 109a8aede79SJames Liao "syspll_d6", 110a8aede79SJames Liao "univpll_d5", 111a8aede79SJames Liao "univpll2_d2", 112a8aede79SJames Liao "syspll_d3p5" 113a8aede79SJames Liao }; 114a8aede79SJames Liao 115a8aede79SJames Liao static const char * const smi_parents[] __initconst = { 116a8aede79SJames Liao "clk26m", 117a8aede79SJames Liao "clkph_mck", 118a8aede79SJames Liao "syspll_d2p5", 119a8aede79SJames Liao "syspll_d3", 120a8aede79SJames Liao "syspll_d8", 121a8aede79SJames Liao "univpll_d5", 122a8aede79SJames Liao "univpll1_d2", 123a8aede79SJames Liao "univpll1_d6", 124a8aede79SJames Liao "mmpll_d3", 125a8aede79SJames Liao "mmpll_d4", 126a8aede79SJames Liao "mmpll_d5", 127a8aede79SJames Liao "mmpll_d6", 128a8aede79SJames Liao "mmpll_d7", 129a8aede79SJames Liao "vdecpll", 130a8aede79SJames Liao "lvdspll" 131a8aede79SJames Liao }; 132a8aede79SJames Liao 133a8aede79SJames Liao static const char * const mfg_parents[] __initconst = { 134a8aede79SJames Liao "clk26m", 135a8aede79SJames Liao "univpll1_d4", 136a8aede79SJames Liao "syspll_d2", 137a8aede79SJames Liao "syspll_d2p5", 138a8aede79SJames Liao "syspll_d3", 139a8aede79SJames Liao "univpll_d5", 140a8aede79SJames Liao "univpll1_d2", 141a8aede79SJames Liao "mmpll_d2", 142a8aede79SJames Liao "mmpll_d3", 143a8aede79SJames Liao "mmpll_d4", 144a8aede79SJames Liao "mmpll_d5", 145a8aede79SJames Liao "mmpll_d6", 146a8aede79SJames Liao "mmpll_d7" 147a8aede79SJames Liao }; 148a8aede79SJames Liao 149a8aede79SJames Liao static const char * const irda_parents[] __initconst = { 150a8aede79SJames Liao "clk26m", 151a8aede79SJames Liao "univpll2_d8", 152a8aede79SJames Liao "univpll1_d6" 153a8aede79SJames Liao }; 154a8aede79SJames Liao 155a8aede79SJames Liao static const char * const cam_parents[] __initconst = { 156a8aede79SJames Liao "clk26m", 157a8aede79SJames Liao "syspll_d3", 158a8aede79SJames Liao "syspll_d3p5", 159a8aede79SJames Liao "syspll_d4", 160a8aede79SJames Liao "univpll_d5", 161a8aede79SJames Liao "univpll2_d2", 162a8aede79SJames Liao "univpll_d7", 163a8aede79SJames Liao "univpll1_d4" 164a8aede79SJames Liao }; 165a8aede79SJames Liao 166a8aede79SJames Liao static const char * const aud_intbus_parents[] __initconst = { 167a8aede79SJames Liao "clk26m", 168a8aede79SJames Liao "syspll_d6", 169a8aede79SJames Liao "univpll_d10" 170a8aede79SJames Liao }; 171a8aede79SJames Liao 172a8aede79SJames Liao static const char * const jpg_parents[] __initconst = { 173a8aede79SJames Liao "clk26m", 174a8aede79SJames Liao "syspll_d5", 175a8aede79SJames Liao "syspll_d4", 176a8aede79SJames Liao "syspll_d3", 177a8aede79SJames Liao "univpll_d7", 178a8aede79SJames Liao "univpll2_d2", 179a8aede79SJames Liao "univpll_d5" 180a8aede79SJames Liao }; 181a8aede79SJames Liao 182a8aede79SJames Liao static const char * const disp_parents[] __initconst = { 183a8aede79SJames Liao "clk26m", 184a8aede79SJames Liao "syspll_d3p5", 185a8aede79SJames Liao "syspll_d3", 186a8aede79SJames Liao "univpll2_d2", 187a8aede79SJames Liao "univpll_d5", 188a8aede79SJames Liao "univpll1_d2", 189a8aede79SJames Liao "lvdspll", 190a8aede79SJames Liao "vdecpll" 191a8aede79SJames Liao }; 192a8aede79SJames Liao 193a8aede79SJames Liao static const char * const msdc30_parents[] __initconst = { 194a8aede79SJames Liao "clk26m", 195a8aede79SJames Liao "syspll_d6", 196a8aede79SJames Liao "syspll_d5", 197a8aede79SJames Liao "univpll1_d4", 198a8aede79SJames Liao "univpll2_d4", 199a8aede79SJames Liao "msdcpll" 200a8aede79SJames Liao }; 201a8aede79SJames Liao 202a8aede79SJames Liao static const char * const usb20_parents[] __initconst = { 203a8aede79SJames Liao "clk26m", 204a8aede79SJames Liao "univpll2_d6", 205a8aede79SJames Liao "univpll1_d10" 206a8aede79SJames Liao }; 207a8aede79SJames Liao 208a8aede79SJames Liao static const char * const venc_parents[] __initconst = { 209a8aede79SJames Liao "clk26m", 210a8aede79SJames Liao "syspll_d3", 211a8aede79SJames Liao "syspll_d8", 212a8aede79SJames Liao "univpll_d5", 213a8aede79SJames Liao "univpll1_d6", 214a8aede79SJames Liao "mmpll_d4", 215a8aede79SJames Liao "mmpll_d5", 216a8aede79SJames Liao "mmpll_d6" 217a8aede79SJames Liao }; 218a8aede79SJames Liao 219a8aede79SJames Liao static const char * const spi_parents[] __initconst = { 220a8aede79SJames Liao "clk26m", 221a8aede79SJames Liao "syspll_d6", 222a8aede79SJames Liao "syspll_d8", 223a8aede79SJames Liao "syspll_d10", 224a8aede79SJames Liao "univpll1_d6", 225a8aede79SJames Liao "univpll1_d8" 226a8aede79SJames Liao }; 227a8aede79SJames Liao 228a8aede79SJames Liao static const char * const uart_parents[] __initconst = { 229a8aede79SJames Liao "clk26m", 230a8aede79SJames Liao "univpll2_d8" 231a8aede79SJames Liao }; 232a8aede79SJames Liao 233a8aede79SJames Liao static const char * const mem_parents[] __initconst = { 234a8aede79SJames Liao "clk26m", 235a8aede79SJames Liao "clkph_mck" 236a8aede79SJames Liao }; 237a8aede79SJames Liao 238a8aede79SJames Liao static const char * const camtg_parents[] __initconst = { 239a8aede79SJames Liao "clk26m", 240a8aede79SJames Liao "univpll_d26", 241a8aede79SJames Liao "univpll1_d6", 242a8aede79SJames Liao "syspll_d16", 243a8aede79SJames Liao "syspll_d8" 244a8aede79SJames Liao }; 245a8aede79SJames Liao 246a8aede79SJames Liao static const char * const audio_parents[] __initconst = { 247a8aede79SJames Liao "clk26m", 248a8aede79SJames Liao "syspll_d24" 249a8aede79SJames Liao }; 250a8aede79SJames Liao 251a8aede79SJames Liao static const char * const fix_parents[] __initconst = { 252a8aede79SJames Liao "rtc32k", 253a8aede79SJames Liao "clk26m", 254a8aede79SJames Liao "univpll_d5", 255a8aede79SJames Liao "univpll_d7", 256a8aede79SJames Liao "univpll1_d2", 257a8aede79SJames Liao "univpll1_d4", 258a8aede79SJames Liao "univpll1_d6", 259a8aede79SJames Liao "univpll1_d8" 260a8aede79SJames Liao }; 261a8aede79SJames Liao 262a8aede79SJames Liao static const char * const vdec_parents[] __initconst = { 263a8aede79SJames Liao "clk26m", 264a8aede79SJames Liao "vdecpll", 265a8aede79SJames Liao "clkph_mck", 266a8aede79SJames Liao "syspll_d2p5", 267a8aede79SJames Liao "syspll_d3", 268a8aede79SJames Liao "syspll_d3p5", 269a8aede79SJames Liao "syspll_d4", 270a8aede79SJames Liao "syspll_d5", 271a8aede79SJames Liao "syspll_d6", 272a8aede79SJames Liao "syspll_d8", 273a8aede79SJames Liao "univpll1_d2", 274a8aede79SJames Liao "univpll2_d2", 275a8aede79SJames Liao "univpll_d7", 276a8aede79SJames Liao "univpll_d10", 277a8aede79SJames Liao "univpll2_d4", 278a8aede79SJames Liao "lvdspll" 279a8aede79SJames Liao }; 280a8aede79SJames Liao 281a8aede79SJames Liao static const char * const ddrphycfg_parents[] __initconst = { 282a8aede79SJames Liao "clk26m", 283a8aede79SJames Liao "axi_sel", 284a8aede79SJames Liao "syspll_d12" 285a8aede79SJames Liao }; 286a8aede79SJames Liao 287a8aede79SJames Liao static const char * const dpilvds_parents[] __initconst = { 288a8aede79SJames Liao "clk26m", 289a8aede79SJames Liao "lvdspll", 290a8aede79SJames Liao "lvdspll_d2", 291a8aede79SJames Liao "lvdspll_d4", 292a8aede79SJames Liao "lvdspll_d8" 293a8aede79SJames Liao }; 294a8aede79SJames Liao 295a8aede79SJames Liao static const char * const pmicspi_parents[] __initconst = { 296a8aede79SJames Liao "clk26m", 297a8aede79SJames Liao "univpll2_d6", 298a8aede79SJames Liao "syspll_d8", 299a8aede79SJames Liao "syspll_d10", 300a8aede79SJames Liao "univpll1_d10", 301a8aede79SJames Liao "mempll_mck_d4", 302a8aede79SJames Liao "univpll_d26", 303a8aede79SJames Liao "syspll_d24" 304a8aede79SJames Liao }; 305a8aede79SJames Liao 306a8aede79SJames Liao static const char * const smi_mfg_as_parents[] __initconst = { 307a8aede79SJames Liao "clk26m", 308a8aede79SJames Liao "smi_sel", 309a8aede79SJames Liao "mfg_sel", 310a8aede79SJames Liao "mem_sel" 311a8aede79SJames Liao }; 312a8aede79SJames Liao 313a8aede79SJames Liao static const char * const gcpu_parents[] __initconst = { 314a8aede79SJames Liao "clk26m", 315a8aede79SJames Liao "syspll_d4", 316a8aede79SJames Liao "univpll_d7", 317a8aede79SJames Liao "syspll_d5", 318a8aede79SJames Liao "syspll_d6" 319a8aede79SJames Liao }; 320a8aede79SJames Liao 321a8aede79SJames Liao static const char * const dpi1_parents[] __initconst = { 322a8aede79SJames Liao "clk26m", 323a8aede79SJames Liao "tvhdmi_h_ck", 324a8aede79SJames Liao "tvhdmi_d2", 325a8aede79SJames Liao "tvhdmi_d4" 326a8aede79SJames Liao }; 327a8aede79SJames Liao 328a8aede79SJames Liao static const char * const cci_parents[] __initconst = { 329a8aede79SJames Liao "clk26m", 330a8aede79SJames Liao "mainpll_537p3m", 331a8aede79SJames Liao "univpll_d3", 332a8aede79SJames Liao "syspll_d2p5", 333a8aede79SJames Liao "syspll_d3", 334a8aede79SJames Liao "syspll_d5" 335a8aede79SJames Liao }; 336a8aede79SJames Liao 337a8aede79SJames Liao static const char * const apll_parents[] __initconst = { 338a8aede79SJames Liao "clk26m", 339a8aede79SJames Liao "apll_ck", 340a8aede79SJames Liao "apll_d4", 341a8aede79SJames Liao "apll_d8", 342a8aede79SJames Liao "apll_d16", 343a8aede79SJames Liao "apll_d24" 344a8aede79SJames Liao }; 345a8aede79SJames Liao 346a8aede79SJames Liao static const char * const hdmipll_parents[] __initconst = { 347a8aede79SJames Liao "clk26m", 348a8aede79SJames Liao "hdmitx_clkdig_cts", 349a8aede79SJames Liao "hdmitx_clkdig_d2", 350a8aede79SJames Liao "hdmitx_clkdig_d3" 351a8aede79SJames Liao }; 352a8aede79SJames Liao 353a8aede79SJames Liao static const struct mtk_composite top_muxes[] __initconst = { 354a8aede79SJames Liao /* CLK_CFG_0 */ 355a8aede79SJames Liao MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 356a8aede79SJames Liao 0x0140, 0, 3, INVALID_MUX_GATE_BIT), 357a8aede79SJames Liao MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15), 358a8aede79SJames Liao MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23), 359a8aede79SJames Liao MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31), 360a8aede79SJames Liao /* CLK_CFG_1 */ 361a8aede79SJames Liao MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7), 362a8aede79SJames Liao MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 363a8aede79SJames Liao 0x0144, 8, 2, 15), 364a8aede79SJames Liao MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23), 365a8aede79SJames Liao MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31), 366a8aede79SJames Liao /* CLK_CFG_2 */ 367a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7), 368a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15), 369a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23), 370a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31), 371a8aede79SJames Liao /* CLK_CFG_3 */ 372a8aede79SJames Liao MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7), 373a8aede79SJames Liao /* CLK_CFG_4 */ 374a8aede79SJames Liao MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15), 375a8aede79SJames Liao MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23), 376a8aede79SJames Liao MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31), 377a8aede79SJames Liao /* CLK_CFG_6 */ 378a8aede79SJames Liao MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7), 379a8aede79SJames Liao MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15), 380a8aede79SJames Liao MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31), 381a8aede79SJames Liao /* CLK_CFG_7 */ 382a8aede79SJames Liao MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7), 383a8aede79SJames Liao MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15), 384a8aede79SJames Liao MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 385a8aede79SJames Liao 0x015c, 16, 2, 23), 386a8aede79SJames Liao MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31), 387a8aede79SJames Liao /* CLK_CFG_8 */ 388a8aede79SJames Liao MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7), 389a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15), 390a8aede79SJames Liao MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents, 391a8aede79SJames Liao 0x0164, 16, 2, 23), 392a8aede79SJames Liao MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31), 393a8aede79SJames Liao /* CLK_CFG_9 */ 394a8aede79SJames Liao MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7), 395*f4f9a9c0SAngeloGioacchino Del Regno MUX_GATE_FLAGS(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15, CLK_IS_CRITICAL), 396a8aede79SJames Liao MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23), 397a8aede79SJames Liao MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31), 398a8aede79SJames Liao }; 399a8aede79SJames Liao 400a8aede79SJames Liao static const struct mtk_gate_regs infra_cg_regs = { 401a8aede79SJames Liao .set_ofs = 0x0040, 402a8aede79SJames Liao .clr_ofs = 0x0044, 403a8aede79SJames Liao .sta_ofs = 0x0048, 404a8aede79SJames Liao }; 405a8aede79SJames Liao 4064c85e20bSAngeloGioacchino Del Regno #define GATE_ICG(_id, _name, _parent, _shift) \ 4074c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 408a8aede79SJames Liao 409*f4f9a9c0SAngeloGioacchino Del Regno #define GATE_ICG_AO(_id, _name, _parent, _shift) \ 410*f4f9a9c0SAngeloGioacchino Del Regno GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \ 411*f4f9a9c0SAngeloGioacchino Del Regno &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) 412*f4f9a9c0SAngeloGioacchino Del Regno 413a8aede79SJames Liao static const struct mtk_gate infra_clks[] __initconst = { 414a8aede79SJames Liao GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), 415a8aede79SJames Liao GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), 416a8aede79SJames Liao GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21), 417a8aede79SJames Liao GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20), 418a8aede79SJames Liao GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), 419a8aede79SJames Liao GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15), 420*f4f9a9c0SAngeloGioacchino Del Regno GATE_ICG_AO(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), 421a8aede79SJames Liao GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7), 422a8aede79SJames Liao GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6), 423a8aede79SJames Liao GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5), 424a8aede79SJames Liao GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2), 425a8aede79SJames Liao GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1), 426a8aede79SJames Liao GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0), 427a8aede79SJames Liao }; 428a8aede79SJames Liao 429a8aede79SJames Liao static const struct mtk_gate_regs peri0_cg_regs = { 430a8aede79SJames Liao .set_ofs = 0x0008, 431a8aede79SJames Liao .clr_ofs = 0x0010, 432a8aede79SJames Liao .sta_ofs = 0x0018, 433a8aede79SJames Liao }; 434a8aede79SJames Liao 435a8aede79SJames Liao static const struct mtk_gate_regs peri1_cg_regs = { 436a8aede79SJames Liao .set_ofs = 0x000c, 437a8aede79SJames Liao .clr_ofs = 0x0014, 438a8aede79SJames Liao .sta_ofs = 0x001c, 439a8aede79SJames Liao }; 440a8aede79SJames Liao 4414c85e20bSAngeloGioacchino Del Regno #define GATE_PERI0(_id, _name, _parent, _shift) \ 4424c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 443a8aede79SJames Liao 4444c85e20bSAngeloGioacchino Del Regno #define GATE_PERI1(_id, _name, _parent, _shift) \ 4454c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 446a8aede79SJames Liao 447a8aede79SJames Liao static const struct mtk_gate peri_gates[] __initconst = { 448a8aede79SJames Liao /* PERI0 */ 449a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31), 450a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30), 451a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29), 452a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28), 453a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27), 454a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26), 455a8aede79SJames Liao GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25), 456a8aede79SJames Liao GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24), 457a8aede79SJames Liao GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23), 458a8aede79SJames Liao GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22), 459a8aede79SJames Liao GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21), 460a8aede79SJames Liao GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20), 461a8aede79SJames Liao GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19), 462a8aede79SJames Liao GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18), 463a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17), 464a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16), 465a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15), 466a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14), 467a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13), 468a8aede79SJames Liao GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), 469a8aede79SJames Liao GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), 470a8aede79SJames Liao GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), 471a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), 472a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8), 473a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7), 474a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6), 475a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5), 476a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4), 477a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3), 478a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2), 479a8aede79SJames Liao GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), 480a8aede79SJames Liao GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0), 481a8aede79SJames Liao /* PERI1 */ 482a8aede79SJames Liao GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8), 483a8aede79SJames Liao GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7), 484a8aede79SJames Liao GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6), 485a8aede79SJames Liao GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5), 486a8aede79SJames Liao GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4), 487a8aede79SJames Liao GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3), 488a8aede79SJames Liao GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2), 489a8aede79SJames Liao GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1), 490a8aede79SJames Liao GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0), 491a8aede79SJames Liao }; 492a8aede79SJames Liao 493a8aede79SJames Liao static const char * const uart_ck_sel_parents[] __initconst = { 494a8aede79SJames Liao "clk26m", 495a8aede79SJames Liao "uart_sel", 496a8aede79SJames Liao }; 497a8aede79SJames Liao 498a8aede79SJames Liao static const struct mtk_composite peri_clks[] __initconst = { 499a8aede79SJames Liao MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), 500a8aede79SJames Liao MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), 501a8aede79SJames Liao MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), 502a8aede79SJames Liao MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), 503a8aede79SJames Liao }; 504a8aede79SJames Liao 505723e3671SRex-BC Chen static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; 506723e3671SRex-BC Chen static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 507723e3671SRex-BC Chen 5082d2a2900SRex-BC Chen static const struct mtk_clk_rst_desc clk_rst_desc[] = { 5092d2a2900SRex-BC Chen /* infrasys */ 5102d2a2900SRex-BC Chen { 5112d2a2900SRex-BC Chen .version = MTK_RST_SIMPLE, 512723e3671SRex-BC Chen .rst_bank_ofs = infrasys_rst_ofs, 513723e3671SRex-BC Chen .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 5142d2a2900SRex-BC Chen }, 5152d2a2900SRex-BC Chen /* pericfg */ 5162d2a2900SRex-BC Chen { 5172d2a2900SRex-BC Chen .version = MTK_RST_SIMPLE, 518723e3671SRex-BC Chen .rst_bank_ofs = pericfg_rst_ofs, 519723e3671SRex-BC Chen .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 5202d2a2900SRex-BC Chen } 5212d2a2900SRex-BC Chen }; 5222d2a2900SRex-BC Chen 523a8aede79SJames Liao static void __init mtk_topckgen_init(struct device_node *node) 524a8aede79SJames Liao { 525609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data; 526a8aede79SJames Liao void __iomem *base; 527a8aede79SJames Liao int r; 528a8aede79SJames Liao 529a8aede79SJames Liao base = of_iomap(node, 0); 530a8aede79SJames Liao if (!base) { 531a8aede79SJames Liao pr_err("%s(): ioremap failed\n", __func__); 532a8aede79SJames Liao return; 533a8aede79SJames Liao } 534a8aede79SJames Liao 535a8aede79SJames Liao clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 536a8aede79SJames Liao 537a8aede79SJames Liao mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); 538a8aede79SJames Liao mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 53901a6c1abSAngeloGioacchino Del Regno mtk_clk_register_composites(NULL, top_muxes, 54001a6c1abSAngeloGioacchino Del Regno ARRAY_SIZE(top_muxes), base, 541a8aede79SJames Liao &mt8135_clk_lock, clk_data); 542a8aede79SJames Liao 543609cc5e1SChen-Yu Tsai r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 544a8aede79SJames Liao if (r) 545a8aede79SJames Liao pr_err("%s(): could not register clock provider: %d\n", 546a8aede79SJames Liao __func__, r); 547a8aede79SJames Liao } 548a8aede79SJames Liao CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init); 549a8aede79SJames Liao 550a8aede79SJames Liao static void __init mtk_infrasys_init(struct device_node *node) 551a8aede79SJames Liao { 552609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data; 553a8aede79SJames Liao int r; 554a8aede79SJames Liao 555a8aede79SJames Liao clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 556a8aede79SJames Liao 55720498d52SAngeloGioacchino Del Regno mtk_clk_register_gates(NULL, node, infra_clks, 55820498d52SAngeloGioacchino Del Regno ARRAY_SIZE(infra_clks), clk_data); 559a8aede79SJames Liao 560609cc5e1SChen-Yu Tsai r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 561a8aede79SJames Liao if (r) 562a8aede79SJames Liao pr_err("%s(): could not register clock provider: %d\n", 563a8aede79SJames Liao __func__, r); 564a8aede79SJames Liao 5652d2a2900SRex-BC Chen mtk_register_reset_controller(node, &clk_rst_desc[0]); 566a8aede79SJames Liao } 567a8aede79SJames Liao CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); 568a8aede79SJames Liao 569a8aede79SJames Liao static void __init mtk_pericfg_init(struct device_node *node) 570a8aede79SJames Liao { 571609cc5e1SChen-Yu Tsai struct clk_hw_onecell_data *clk_data; 572a8aede79SJames Liao int r; 573a8aede79SJames Liao void __iomem *base; 574a8aede79SJames Liao 575a8aede79SJames Liao base = of_iomap(node, 0); 576a8aede79SJames Liao if (!base) { 577a8aede79SJames Liao pr_err("%s(): ioremap failed\n", __func__); 578a8aede79SJames Liao return; 579a8aede79SJames Liao } 580a8aede79SJames Liao 581a8aede79SJames Liao clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 582a8aede79SJames Liao 58320498d52SAngeloGioacchino Del Regno mtk_clk_register_gates(NULL, node, peri_gates, 58420498d52SAngeloGioacchino Del Regno ARRAY_SIZE(peri_gates), clk_data); 58501a6c1abSAngeloGioacchino Del Regno mtk_clk_register_composites(NULL, peri_clks, 58601a6c1abSAngeloGioacchino Del Regno ARRAY_SIZE(peri_clks), base, 587a8aede79SJames Liao &mt8135_clk_lock, clk_data); 588a8aede79SJames Liao 589609cc5e1SChen-Yu Tsai r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 590a8aede79SJames Liao if (r) 591a8aede79SJames Liao pr_err("%s(): could not register clock provider: %d\n", 592a8aede79SJames Liao __func__, r); 593a8aede79SJames Liao 5942d2a2900SRex-BC Chen mtk_register_reset_controller(node, &clk_rst_desc[1]); 595a8aede79SJames Liao } 596a8aede79SJames Liao CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); 597a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 598