11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2a8aede79SJames Liao /* 3a8aede79SJames Liao * Copyright (c) 2014 MediaTek Inc. 4a8aede79SJames Liao * Author: James Liao <jamesjj.liao@mediatek.com> 5a8aede79SJames Liao */ 6a8aede79SJames Liao 7c726639bSStephen Boyd #include <linux/clk.h> 8a8aede79SJames Liao #include <linux/of.h> 9a8aede79SJames Liao #include <linux/of_address.h> 10a8aede79SJames Liao #include <linux/slab.h> 11a8aede79SJames Liao #include <linux/mfd/syscon.h> 12a8aede79SJames Liao #include <dt-bindings/clock/mt8135-clk.h> 13a8aede79SJames Liao 14a8aede79SJames Liao #include "clk-gate.h" 15*39691fb6SChen-Yu Tsai #include "clk-mtk.h" 16*39691fb6SChen-Yu Tsai #include "clk-pll.h" 17a8aede79SJames Liao 18a8aede79SJames Liao static DEFINE_SPINLOCK(mt8135_clk_lock); 19a8aede79SJames Liao 20a8aede79SJames Liao static const struct mtk_fixed_factor root_clk_alias[] __initconst = { 21a8aede79SJames Liao FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), 22a8aede79SJames Liao FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), 23a8aede79SJames Liao FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), 24a8aede79SJames Liao FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), 25a8aede79SJames Liao }; 26a8aede79SJames Liao 27a8aede79SJames Liao static const struct mtk_fixed_factor top_divs[] __initconst = { 28a8aede79SJames Liao FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2), 29a8aede79SJames Liao FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3), 30a8aede79SJames Liao FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5), 31a8aede79SJames Liao FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7), 32a8aede79SJames Liao 33a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2), 34a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3), 35a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5), 36a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7), 37a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26), 38a8aede79SJames Liao 39a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 40a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3), 41a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 42a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 43a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2), 44a8aede79SJames Liao FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2), 45a8aede79SJames Liao 46a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1), 47a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2), 48a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3), 49a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4), 50a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5), 51a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6), 52a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8), 53a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12), 54a8aede79SJames Liao 55a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1), 56a8aede79SJames Liao 57a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1), 58a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1), 59a8aede79SJames Liao 60a8aede79SJames Liao FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1), 61a8aede79SJames Liao 62a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2), 63a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4), 64a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6), 65a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8), 66a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10), 67a8aede79SJames Liao 68a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2), 69a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4), 70a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6), 71a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8), 72a8aede79SJames Liao 73a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1), 74a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1), 75a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1), 76a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2), 77a8aede79SJames Liao FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1), 78a8aede79SJames Liao 79a8aede79SJames Liao FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1), 80a8aede79SJames Liao FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4), 81a8aede79SJames Liao FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8), 82a8aede79SJames Liao FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16), 83a8aede79SJames Liao FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24), 84a8aede79SJames Liao 85a8aede79SJames Liao FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 86a8aede79SJames Liao FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 87a8aede79SJames Liao FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 88a8aede79SJames Liao 89a8aede79SJames Liao FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1), 90a8aede79SJames Liao FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1), 91a8aede79SJames Liao 92a8aede79SJames Liao FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1), 93a8aede79SJames Liao 94a8aede79SJames Liao FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2), 95a8aede79SJames Liao FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3), 96a8aede79SJames Liao 97a8aede79SJames Liao FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2), 98a8aede79SJames Liao FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4), 99a8aede79SJames Liao 100a8aede79SJames Liao FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), 101a8aede79SJames Liao }; 102a8aede79SJames Liao 103a8aede79SJames Liao static const char * const axi_parents[] __initconst = { 104a8aede79SJames Liao "clk26m", 105a8aede79SJames Liao "syspll_d3", 106a8aede79SJames Liao "syspll_d4", 107a8aede79SJames Liao "syspll_d6", 108a8aede79SJames Liao "univpll_d5", 109a8aede79SJames Liao "univpll2_d2", 110a8aede79SJames Liao "syspll_d3p5" 111a8aede79SJames Liao }; 112a8aede79SJames Liao 113a8aede79SJames Liao static const char * const smi_parents[] __initconst = { 114a8aede79SJames Liao "clk26m", 115a8aede79SJames Liao "clkph_mck", 116a8aede79SJames Liao "syspll_d2p5", 117a8aede79SJames Liao "syspll_d3", 118a8aede79SJames Liao "syspll_d8", 119a8aede79SJames Liao "univpll_d5", 120a8aede79SJames Liao "univpll1_d2", 121a8aede79SJames Liao "univpll1_d6", 122a8aede79SJames Liao "mmpll_d3", 123a8aede79SJames Liao "mmpll_d4", 124a8aede79SJames Liao "mmpll_d5", 125a8aede79SJames Liao "mmpll_d6", 126a8aede79SJames Liao "mmpll_d7", 127a8aede79SJames Liao "vdecpll", 128a8aede79SJames Liao "lvdspll" 129a8aede79SJames Liao }; 130a8aede79SJames Liao 131a8aede79SJames Liao static const char * const mfg_parents[] __initconst = { 132a8aede79SJames Liao "clk26m", 133a8aede79SJames Liao "univpll1_d4", 134a8aede79SJames Liao "syspll_d2", 135a8aede79SJames Liao "syspll_d2p5", 136a8aede79SJames Liao "syspll_d3", 137a8aede79SJames Liao "univpll_d5", 138a8aede79SJames Liao "univpll1_d2", 139a8aede79SJames Liao "mmpll_d2", 140a8aede79SJames Liao "mmpll_d3", 141a8aede79SJames Liao "mmpll_d4", 142a8aede79SJames Liao "mmpll_d5", 143a8aede79SJames Liao "mmpll_d6", 144a8aede79SJames Liao "mmpll_d7" 145a8aede79SJames Liao }; 146a8aede79SJames Liao 147a8aede79SJames Liao static const char * const irda_parents[] __initconst = { 148a8aede79SJames Liao "clk26m", 149a8aede79SJames Liao "univpll2_d8", 150a8aede79SJames Liao "univpll1_d6" 151a8aede79SJames Liao }; 152a8aede79SJames Liao 153a8aede79SJames Liao static const char * const cam_parents[] __initconst = { 154a8aede79SJames Liao "clk26m", 155a8aede79SJames Liao "syspll_d3", 156a8aede79SJames Liao "syspll_d3p5", 157a8aede79SJames Liao "syspll_d4", 158a8aede79SJames Liao "univpll_d5", 159a8aede79SJames Liao "univpll2_d2", 160a8aede79SJames Liao "univpll_d7", 161a8aede79SJames Liao "univpll1_d4" 162a8aede79SJames Liao }; 163a8aede79SJames Liao 164a8aede79SJames Liao static const char * const aud_intbus_parents[] __initconst = { 165a8aede79SJames Liao "clk26m", 166a8aede79SJames Liao "syspll_d6", 167a8aede79SJames Liao "univpll_d10" 168a8aede79SJames Liao }; 169a8aede79SJames Liao 170a8aede79SJames Liao static const char * const jpg_parents[] __initconst = { 171a8aede79SJames Liao "clk26m", 172a8aede79SJames Liao "syspll_d5", 173a8aede79SJames Liao "syspll_d4", 174a8aede79SJames Liao "syspll_d3", 175a8aede79SJames Liao "univpll_d7", 176a8aede79SJames Liao "univpll2_d2", 177a8aede79SJames Liao "univpll_d5" 178a8aede79SJames Liao }; 179a8aede79SJames Liao 180a8aede79SJames Liao static const char * const disp_parents[] __initconst = { 181a8aede79SJames Liao "clk26m", 182a8aede79SJames Liao "syspll_d3p5", 183a8aede79SJames Liao "syspll_d3", 184a8aede79SJames Liao "univpll2_d2", 185a8aede79SJames Liao "univpll_d5", 186a8aede79SJames Liao "univpll1_d2", 187a8aede79SJames Liao "lvdspll", 188a8aede79SJames Liao "vdecpll" 189a8aede79SJames Liao }; 190a8aede79SJames Liao 191a8aede79SJames Liao static const char * const msdc30_parents[] __initconst = { 192a8aede79SJames Liao "clk26m", 193a8aede79SJames Liao "syspll_d6", 194a8aede79SJames Liao "syspll_d5", 195a8aede79SJames Liao "univpll1_d4", 196a8aede79SJames Liao "univpll2_d4", 197a8aede79SJames Liao "msdcpll" 198a8aede79SJames Liao }; 199a8aede79SJames Liao 200a8aede79SJames Liao static const char * const usb20_parents[] __initconst = { 201a8aede79SJames Liao "clk26m", 202a8aede79SJames Liao "univpll2_d6", 203a8aede79SJames Liao "univpll1_d10" 204a8aede79SJames Liao }; 205a8aede79SJames Liao 206a8aede79SJames Liao static const char * const venc_parents[] __initconst = { 207a8aede79SJames Liao "clk26m", 208a8aede79SJames Liao "syspll_d3", 209a8aede79SJames Liao "syspll_d8", 210a8aede79SJames Liao "univpll_d5", 211a8aede79SJames Liao "univpll1_d6", 212a8aede79SJames Liao "mmpll_d4", 213a8aede79SJames Liao "mmpll_d5", 214a8aede79SJames Liao "mmpll_d6" 215a8aede79SJames Liao }; 216a8aede79SJames Liao 217a8aede79SJames Liao static const char * const spi_parents[] __initconst = { 218a8aede79SJames Liao "clk26m", 219a8aede79SJames Liao "syspll_d6", 220a8aede79SJames Liao "syspll_d8", 221a8aede79SJames Liao "syspll_d10", 222a8aede79SJames Liao "univpll1_d6", 223a8aede79SJames Liao "univpll1_d8" 224a8aede79SJames Liao }; 225a8aede79SJames Liao 226a8aede79SJames Liao static const char * const uart_parents[] __initconst = { 227a8aede79SJames Liao "clk26m", 228a8aede79SJames Liao "univpll2_d8" 229a8aede79SJames Liao }; 230a8aede79SJames Liao 231a8aede79SJames Liao static const char * const mem_parents[] __initconst = { 232a8aede79SJames Liao "clk26m", 233a8aede79SJames Liao "clkph_mck" 234a8aede79SJames Liao }; 235a8aede79SJames Liao 236a8aede79SJames Liao static const char * const camtg_parents[] __initconst = { 237a8aede79SJames Liao "clk26m", 238a8aede79SJames Liao "univpll_d26", 239a8aede79SJames Liao "univpll1_d6", 240a8aede79SJames Liao "syspll_d16", 241a8aede79SJames Liao "syspll_d8" 242a8aede79SJames Liao }; 243a8aede79SJames Liao 244a8aede79SJames Liao static const char * const audio_parents[] __initconst = { 245a8aede79SJames Liao "clk26m", 246a8aede79SJames Liao "syspll_d24" 247a8aede79SJames Liao }; 248a8aede79SJames Liao 249a8aede79SJames Liao static const char * const fix_parents[] __initconst = { 250a8aede79SJames Liao "rtc32k", 251a8aede79SJames Liao "clk26m", 252a8aede79SJames Liao "univpll_d5", 253a8aede79SJames Liao "univpll_d7", 254a8aede79SJames Liao "univpll1_d2", 255a8aede79SJames Liao "univpll1_d4", 256a8aede79SJames Liao "univpll1_d6", 257a8aede79SJames Liao "univpll1_d8" 258a8aede79SJames Liao }; 259a8aede79SJames Liao 260a8aede79SJames Liao static const char * const vdec_parents[] __initconst = { 261a8aede79SJames Liao "clk26m", 262a8aede79SJames Liao "vdecpll", 263a8aede79SJames Liao "clkph_mck", 264a8aede79SJames Liao "syspll_d2p5", 265a8aede79SJames Liao "syspll_d3", 266a8aede79SJames Liao "syspll_d3p5", 267a8aede79SJames Liao "syspll_d4", 268a8aede79SJames Liao "syspll_d5", 269a8aede79SJames Liao "syspll_d6", 270a8aede79SJames Liao "syspll_d8", 271a8aede79SJames Liao "univpll1_d2", 272a8aede79SJames Liao "univpll2_d2", 273a8aede79SJames Liao "univpll_d7", 274a8aede79SJames Liao "univpll_d10", 275a8aede79SJames Liao "univpll2_d4", 276a8aede79SJames Liao "lvdspll" 277a8aede79SJames Liao }; 278a8aede79SJames Liao 279a8aede79SJames Liao static const char * const ddrphycfg_parents[] __initconst = { 280a8aede79SJames Liao "clk26m", 281a8aede79SJames Liao "axi_sel", 282a8aede79SJames Liao "syspll_d12" 283a8aede79SJames Liao }; 284a8aede79SJames Liao 285a8aede79SJames Liao static const char * const dpilvds_parents[] __initconst = { 286a8aede79SJames Liao "clk26m", 287a8aede79SJames Liao "lvdspll", 288a8aede79SJames Liao "lvdspll_d2", 289a8aede79SJames Liao "lvdspll_d4", 290a8aede79SJames Liao "lvdspll_d8" 291a8aede79SJames Liao }; 292a8aede79SJames Liao 293a8aede79SJames Liao static const char * const pmicspi_parents[] __initconst = { 294a8aede79SJames Liao "clk26m", 295a8aede79SJames Liao "univpll2_d6", 296a8aede79SJames Liao "syspll_d8", 297a8aede79SJames Liao "syspll_d10", 298a8aede79SJames Liao "univpll1_d10", 299a8aede79SJames Liao "mempll_mck_d4", 300a8aede79SJames Liao "univpll_d26", 301a8aede79SJames Liao "syspll_d24" 302a8aede79SJames Liao }; 303a8aede79SJames Liao 304a8aede79SJames Liao static const char * const smi_mfg_as_parents[] __initconst = { 305a8aede79SJames Liao "clk26m", 306a8aede79SJames Liao "smi_sel", 307a8aede79SJames Liao "mfg_sel", 308a8aede79SJames Liao "mem_sel" 309a8aede79SJames Liao }; 310a8aede79SJames Liao 311a8aede79SJames Liao static const char * const gcpu_parents[] __initconst = { 312a8aede79SJames Liao "clk26m", 313a8aede79SJames Liao "syspll_d4", 314a8aede79SJames Liao "univpll_d7", 315a8aede79SJames Liao "syspll_d5", 316a8aede79SJames Liao "syspll_d6" 317a8aede79SJames Liao }; 318a8aede79SJames Liao 319a8aede79SJames Liao static const char * const dpi1_parents[] __initconst = { 320a8aede79SJames Liao "clk26m", 321a8aede79SJames Liao "tvhdmi_h_ck", 322a8aede79SJames Liao "tvhdmi_d2", 323a8aede79SJames Liao "tvhdmi_d4" 324a8aede79SJames Liao }; 325a8aede79SJames Liao 326a8aede79SJames Liao static const char * const cci_parents[] __initconst = { 327a8aede79SJames Liao "clk26m", 328a8aede79SJames Liao "mainpll_537p3m", 329a8aede79SJames Liao "univpll_d3", 330a8aede79SJames Liao "syspll_d2p5", 331a8aede79SJames Liao "syspll_d3", 332a8aede79SJames Liao "syspll_d5" 333a8aede79SJames Liao }; 334a8aede79SJames Liao 335a8aede79SJames Liao static const char * const apll_parents[] __initconst = { 336a8aede79SJames Liao "clk26m", 337a8aede79SJames Liao "apll_ck", 338a8aede79SJames Liao "apll_d4", 339a8aede79SJames Liao "apll_d8", 340a8aede79SJames Liao "apll_d16", 341a8aede79SJames Liao "apll_d24" 342a8aede79SJames Liao }; 343a8aede79SJames Liao 344a8aede79SJames Liao static const char * const hdmipll_parents[] __initconst = { 345a8aede79SJames Liao "clk26m", 346a8aede79SJames Liao "hdmitx_clkdig_cts", 347a8aede79SJames Liao "hdmitx_clkdig_d2", 348a8aede79SJames Liao "hdmitx_clkdig_d3" 349a8aede79SJames Liao }; 350a8aede79SJames Liao 351a8aede79SJames Liao static const struct mtk_composite top_muxes[] __initconst = { 352a8aede79SJames Liao /* CLK_CFG_0 */ 353a8aede79SJames Liao MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 354a8aede79SJames Liao 0x0140, 0, 3, INVALID_MUX_GATE_BIT), 355a8aede79SJames Liao MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15), 356a8aede79SJames Liao MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23), 357a8aede79SJames Liao MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31), 358a8aede79SJames Liao /* CLK_CFG_1 */ 359a8aede79SJames Liao MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7), 360a8aede79SJames Liao MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 361a8aede79SJames Liao 0x0144, 8, 2, 15), 362a8aede79SJames Liao MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23), 363a8aede79SJames Liao MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31), 364a8aede79SJames Liao /* CLK_CFG_2 */ 365a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7), 366a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15), 367a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23), 368a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31), 369a8aede79SJames Liao /* CLK_CFG_3 */ 370a8aede79SJames Liao MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7), 371a8aede79SJames Liao /* CLK_CFG_4 */ 372a8aede79SJames Liao MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15), 373a8aede79SJames Liao MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23), 374a8aede79SJames Liao MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31), 375a8aede79SJames Liao /* CLK_CFG_6 */ 376a8aede79SJames Liao MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7), 377a8aede79SJames Liao MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15), 378a8aede79SJames Liao MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31), 379a8aede79SJames Liao /* CLK_CFG_7 */ 380a8aede79SJames Liao MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7), 381a8aede79SJames Liao MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15), 382a8aede79SJames Liao MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 383a8aede79SJames Liao 0x015c, 16, 2, 23), 384a8aede79SJames Liao MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31), 385a8aede79SJames Liao /* CLK_CFG_8 */ 386a8aede79SJames Liao MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7), 387a8aede79SJames Liao MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15), 388a8aede79SJames Liao MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents, 389a8aede79SJames Liao 0x0164, 16, 2, 23), 390a8aede79SJames Liao MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31), 391a8aede79SJames Liao /* CLK_CFG_9 */ 392a8aede79SJames Liao MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7), 393a8aede79SJames Liao MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15), 394a8aede79SJames Liao MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23), 395a8aede79SJames Liao MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31), 396a8aede79SJames Liao }; 397a8aede79SJames Liao 398a8aede79SJames Liao static const struct mtk_gate_regs infra_cg_regs = { 399a8aede79SJames Liao .set_ofs = 0x0040, 400a8aede79SJames Liao .clr_ofs = 0x0044, 401a8aede79SJames Liao .sta_ofs = 0x0048, 402a8aede79SJames Liao }; 403a8aede79SJames Liao 404a8aede79SJames Liao #define GATE_ICG(_id, _name, _parent, _shift) { \ 405a8aede79SJames Liao .id = _id, \ 406a8aede79SJames Liao .name = _name, \ 407a8aede79SJames Liao .parent_name = _parent, \ 408a8aede79SJames Liao .regs = &infra_cg_regs, \ 409a8aede79SJames Liao .shift = _shift, \ 410a8aede79SJames Liao .ops = &mtk_clk_gate_ops_setclr, \ 411a8aede79SJames Liao } 412a8aede79SJames Liao 413a8aede79SJames Liao static const struct mtk_gate infra_clks[] __initconst = { 414a8aede79SJames Liao GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), 415a8aede79SJames Liao GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), 416a8aede79SJames Liao GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21), 417a8aede79SJames Liao GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20), 418a8aede79SJames Liao GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), 419a8aede79SJames Liao GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15), 420a8aede79SJames Liao GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), 421a8aede79SJames Liao GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7), 422a8aede79SJames Liao GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6), 423a8aede79SJames Liao GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5), 424a8aede79SJames Liao GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2), 425a8aede79SJames Liao GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1), 426a8aede79SJames Liao GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0), 427a8aede79SJames Liao }; 428a8aede79SJames Liao 429a8aede79SJames Liao static const struct mtk_gate_regs peri0_cg_regs = { 430a8aede79SJames Liao .set_ofs = 0x0008, 431a8aede79SJames Liao .clr_ofs = 0x0010, 432a8aede79SJames Liao .sta_ofs = 0x0018, 433a8aede79SJames Liao }; 434a8aede79SJames Liao 435a8aede79SJames Liao static const struct mtk_gate_regs peri1_cg_regs = { 436a8aede79SJames Liao .set_ofs = 0x000c, 437a8aede79SJames Liao .clr_ofs = 0x0014, 438a8aede79SJames Liao .sta_ofs = 0x001c, 439a8aede79SJames Liao }; 440a8aede79SJames Liao 441a8aede79SJames Liao #define GATE_PERI0(_id, _name, _parent, _shift) { \ 442a8aede79SJames Liao .id = _id, \ 443a8aede79SJames Liao .name = _name, \ 444a8aede79SJames Liao .parent_name = _parent, \ 445a8aede79SJames Liao .regs = &peri0_cg_regs, \ 446a8aede79SJames Liao .shift = _shift, \ 447a8aede79SJames Liao .ops = &mtk_clk_gate_ops_setclr, \ 448a8aede79SJames Liao } 449a8aede79SJames Liao 450a8aede79SJames Liao #define GATE_PERI1(_id, _name, _parent, _shift) { \ 451a8aede79SJames Liao .id = _id, \ 452a8aede79SJames Liao .name = _name, \ 453a8aede79SJames Liao .parent_name = _parent, \ 454a8aede79SJames Liao .regs = &peri1_cg_regs, \ 455a8aede79SJames Liao .shift = _shift, \ 456a8aede79SJames Liao .ops = &mtk_clk_gate_ops_setclr, \ 457a8aede79SJames Liao } 458a8aede79SJames Liao 459a8aede79SJames Liao static const struct mtk_gate peri_gates[] __initconst = { 460a8aede79SJames Liao /* PERI0 */ 461a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31), 462a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30), 463a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29), 464a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28), 465a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27), 466a8aede79SJames Liao GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26), 467a8aede79SJames Liao GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25), 468a8aede79SJames Liao GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24), 469a8aede79SJames Liao GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23), 470a8aede79SJames Liao GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22), 471a8aede79SJames Liao GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21), 472a8aede79SJames Liao GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20), 473a8aede79SJames Liao GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19), 474a8aede79SJames Liao GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18), 475a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17), 476a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16), 477a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15), 478a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14), 479a8aede79SJames Liao GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13), 480a8aede79SJames Liao GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), 481a8aede79SJames Liao GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), 482a8aede79SJames Liao GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), 483a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), 484a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8), 485a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7), 486a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6), 487a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5), 488a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4), 489a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3), 490a8aede79SJames Liao GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2), 491a8aede79SJames Liao GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), 492a8aede79SJames Liao GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0), 493a8aede79SJames Liao /* PERI1 */ 494a8aede79SJames Liao GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8), 495a8aede79SJames Liao GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7), 496a8aede79SJames Liao GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6), 497a8aede79SJames Liao GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5), 498a8aede79SJames Liao GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4), 499a8aede79SJames Liao GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3), 500a8aede79SJames Liao GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2), 501a8aede79SJames Liao GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1), 502a8aede79SJames Liao GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0), 503a8aede79SJames Liao }; 504a8aede79SJames Liao 505a8aede79SJames Liao static const char * const uart_ck_sel_parents[] __initconst = { 506a8aede79SJames Liao "clk26m", 507a8aede79SJames Liao "uart_sel", 508a8aede79SJames Liao }; 509a8aede79SJames Liao 510a8aede79SJames Liao static const struct mtk_composite peri_clks[] __initconst = { 511a8aede79SJames Liao MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), 512a8aede79SJames Liao MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), 513a8aede79SJames Liao MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), 514a8aede79SJames Liao MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), 515a8aede79SJames Liao }; 516a8aede79SJames Liao 517a8aede79SJames Liao static void __init mtk_topckgen_init(struct device_node *node) 518a8aede79SJames Liao { 519a8aede79SJames Liao struct clk_onecell_data *clk_data; 520a8aede79SJames Liao void __iomem *base; 521a8aede79SJames Liao int r; 522a8aede79SJames Liao 523a8aede79SJames Liao base = of_iomap(node, 0); 524a8aede79SJames Liao if (!base) { 525a8aede79SJames Liao pr_err("%s(): ioremap failed\n", __func__); 526a8aede79SJames Liao return; 527a8aede79SJames Liao } 528a8aede79SJames Liao 529a8aede79SJames Liao clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 530a8aede79SJames Liao 531a8aede79SJames Liao mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); 532a8aede79SJames Liao mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 533a8aede79SJames Liao mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, 534a8aede79SJames Liao &mt8135_clk_lock, clk_data); 535a8aede79SJames Liao 536a8aede79SJames Liao clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]); 537a8aede79SJames Liao 538a8aede79SJames Liao r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 539a8aede79SJames Liao if (r) 540a8aede79SJames Liao pr_err("%s(): could not register clock provider: %d\n", 541a8aede79SJames Liao __func__, r); 542a8aede79SJames Liao } 543a8aede79SJames Liao CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init); 544a8aede79SJames Liao 545a8aede79SJames Liao static void __init mtk_infrasys_init(struct device_node *node) 546a8aede79SJames Liao { 547a8aede79SJames Liao struct clk_onecell_data *clk_data; 548a8aede79SJames Liao int r; 549a8aede79SJames Liao 550a8aede79SJames Liao clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 551a8aede79SJames Liao 552a8aede79SJames Liao mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 553a8aede79SJames Liao clk_data); 554a8aede79SJames Liao 555a8aede79SJames Liao clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]); 556a8aede79SJames Liao 557a8aede79SJames Liao r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 558a8aede79SJames Liao if (r) 559a8aede79SJames Liao pr_err("%s(): could not register clock provider: %d\n", 560a8aede79SJames Liao __func__, r); 561a8aede79SJames Liao 562a8aede79SJames Liao mtk_register_reset_controller(node, 2, 0x30); 563a8aede79SJames Liao } 564a8aede79SJames Liao CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); 565a8aede79SJames Liao 566a8aede79SJames Liao static void __init mtk_pericfg_init(struct device_node *node) 567a8aede79SJames Liao { 568a8aede79SJames Liao struct clk_onecell_data *clk_data; 569a8aede79SJames Liao int r; 570a8aede79SJames Liao void __iomem *base; 571a8aede79SJames Liao 572a8aede79SJames Liao base = of_iomap(node, 0); 573a8aede79SJames Liao if (!base) { 574a8aede79SJames Liao pr_err("%s(): ioremap failed\n", __func__); 575a8aede79SJames Liao return; 576a8aede79SJames Liao } 577a8aede79SJames Liao 578a8aede79SJames Liao clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 579a8aede79SJames Liao 580a8aede79SJames Liao mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), 581a8aede79SJames Liao clk_data); 582a8aede79SJames Liao mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, 583a8aede79SJames Liao &mt8135_clk_lock, clk_data); 584a8aede79SJames Liao 585a8aede79SJames Liao r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 586a8aede79SJames Liao if (r) 587a8aede79SJames Liao pr_err("%s(): could not register clock provider: %d\n", 588a8aede79SJames Liao __func__, r); 589a8aede79SJames Liao 590a8aede79SJames Liao mtk_register_reset_controller(node, 2, 0); 591a8aede79SJames Liao } 592a8aede79SJames Liao CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); 593a8aede79SJames Liao 594a8aede79SJames Liao #define MT8135_PLL_FMAX (2000 * MHZ) 595a8aede79SJames Liao #define CON0_MT8135_RST_BAR BIT(27) 596a8aede79SJames Liao 597a8aede79SJames Liao #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ 598a8aede79SJames Liao .id = _id, \ 599a8aede79SJames Liao .name = _name, \ 600a8aede79SJames Liao .reg = _reg, \ 601a8aede79SJames Liao .pwr_reg = _pwr_reg, \ 602a8aede79SJames Liao .en_mask = _en_mask, \ 603a8aede79SJames Liao .flags = _flags, \ 604a8aede79SJames Liao .rst_bar_mask = CON0_MT8135_RST_BAR, \ 605a8aede79SJames Liao .fmax = MT8135_PLL_FMAX, \ 606a8aede79SJames Liao .pcwbits = _pcwbits, \ 607a8aede79SJames Liao .pd_reg = _pd_reg, \ 608a8aede79SJames Liao .pd_shift = _pd_shift, \ 609a8aede79SJames Liao .tuner_reg = _tuner_reg, \ 610a8aede79SJames Liao .pcw_reg = _pcw_reg, \ 611a8aede79SJames Liao .pcw_shift = _pcw_shift, \ 612a8aede79SJames Liao } 613a8aede79SJames Liao 614a8aede79SJames Liao static const struct mtk_pll_data plls[] = { 615a8aede79SJames Liao PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0), 616a8aede79SJames Liao PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0), 617a8aede79SJames Liao PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0), 618a8aede79SJames Liao PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9), 619a8aede79SJames Liao PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0), 620a8aede79SJames Liao PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0), 621a8aede79SJames Liao PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0), 622a8aede79SJames Liao PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), 623a8aede79SJames Liao PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0), 624a8aede79SJames Liao PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0), 625a8aede79SJames Liao }; 626a8aede79SJames Liao 627a8aede79SJames Liao static void __init mtk_apmixedsys_init(struct device_node *node) 628a8aede79SJames Liao { 629a8aede79SJames Liao struct clk_onecell_data *clk_data; 630a8aede79SJames Liao 63190acb40fSJames Liao clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 632a8aede79SJames Liao if (!clk_data) 633a8aede79SJames Liao return; 634a8aede79SJames Liao 635a8aede79SJames Liao mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 636a8aede79SJames Liao } 637a8aede79SJames Liao CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys", 638a8aede79SJames Liao mtk_apmixedsys_init); 639