1*ec97d23cSSam Shih // SPDX-License-Identifier: GPL-1.0 2*ec97d23cSSam Shih /* 3*ec97d23cSSam Shih * Copyright (c) 2021 MediaTek Inc. 4*ec97d23cSSam Shih * Author: Sam Shih <sam.shih@mediatek.com> 5*ec97d23cSSam Shih * Author: Wenzhen Yu <wenzhen.yu@mediatek.com> 6*ec97d23cSSam Shih */ 7*ec97d23cSSam Shih 8*ec97d23cSSam Shih #include <linux/clk-provider.h> 9*ec97d23cSSam Shih #include <linux/of.h> 10*ec97d23cSSam Shih #include <linux/of_address.h> 11*ec97d23cSSam Shih #include <linux/of_device.h> 12*ec97d23cSSam Shih #include <linux/platform_device.h> 13*ec97d23cSSam Shih #include "clk-mtk.h" 14*ec97d23cSSam Shih #include "clk-gate.h" 15*ec97d23cSSam Shih #include "clk-mux.h" 16*ec97d23cSSam Shih 17*ec97d23cSSam Shih #include <dt-bindings/clock/mt7986-clk.h> 18*ec97d23cSSam Shih #include <linux/clk.h> 19*ec97d23cSSam Shih 20*ec97d23cSSam Shih static DEFINE_SPINLOCK(mt7986_clk_lock); 21*ec97d23cSSam Shih 22*ec97d23cSSam Shih static const struct mtk_fixed_clk top_fixed_clks[] = { 23*ec97d23cSSam Shih FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), 24*ec97d23cSSam Shih FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000), 25*ec97d23cSSam Shih }; 26*ec97d23cSSam Shih 27*ec97d23cSSam Shih static const struct mtk_fixed_factor top_divs[] = { 28*ec97d23cSSam Shih /* XTAL */ 29*ec97d23cSSam Shih FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), 30*ec97d23cSSam Shih FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), 31*ec97d23cSSam Shih FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), 32*ec97d23cSSam Shih /* MPLL */ 33*ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2), 34*ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4), 35*ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8), 36*ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16), 37*ec97d23cSSam Shih FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6), 38*ec97d23cSSam Shih /* MMPLL */ 39*ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2), 40*ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4), 41*ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8), 42*ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16), 43*ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24), 44*ec97d23cSSam Shih FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30), 45*ec97d23cSSam Shih /* APLL2 */ 46*ec97d23cSSam Shih FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4), 47*ec97d23cSSam Shih /* NET1PLL */ 48*ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4), 49*ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5), 50*ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10), 51*ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20), 52*ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16), 53*ec97d23cSSam Shih FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32), 54*ec97d23cSSam Shih /* NET2PLL */ 55*ec97d23cSSam Shih FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4), 56*ec97d23cSSam Shih FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8), 57*ec97d23cSSam Shih FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2), 58*ec97d23cSSam Shih /* WEDMCUPLL */ 59*ec97d23cSSam Shih FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1, 60*ec97d23cSSam Shih 10), 61*ec97d23cSSam Shih }; 62*ec97d23cSSam Shih 63*ec97d23cSSam Shih static const char *const nfi1x_parents[] __initconst = { "top_xtal", 64*ec97d23cSSam Shih "top_mmpll_d8", 65*ec97d23cSSam Shih "top_net1pll_d8_d2", 66*ec97d23cSSam Shih "top_net2pll_d3_d2", 67*ec97d23cSSam Shih "top_mpll_d4", 68*ec97d23cSSam Shih "top_mmpll_d8_d2", 69*ec97d23cSSam Shih "top_wedmcupll_d5_d2", 70*ec97d23cSSam Shih "top_mpll_d8" }; 71*ec97d23cSSam Shih 72*ec97d23cSSam Shih static const char *const spinfi_parents[] __initconst = { 73*ec97d23cSSam Shih "top_xtal_d2", "top_xtal", "top_net1pll_d5_d4", 74*ec97d23cSSam Shih "top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2", 75*ec97d23cSSam Shih "top_mmpll_d3_d8", "top_mpll_d8" 76*ec97d23cSSam Shih }; 77*ec97d23cSSam Shih 78*ec97d23cSSam Shih static const char *const spi_parents[] __initconst = { 79*ec97d23cSSam Shih "top_xtal", "top_mpll_d2", "top_mmpll_d8", 80*ec97d23cSSam Shih "top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4", 81*ec97d23cSSam Shih "top_mpll_d4", "top_wedmcupll_d5_d2" 82*ec97d23cSSam Shih }; 83*ec97d23cSSam Shih 84*ec97d23cSSam Shih static const char *const uart_parents[] __initconst = { "top_xtal", 85*ec97d23cSSam Shih "top_mpll_d8", 86*ec97d23cSSam Shih "top_mpll_d8_d2" }; 87*ec97d23cSSam Shih 88*ec97d23cSSam Shih static const char *const pwm_parents[] __initconst = { 89*ec97d23cSSam Shih "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4" 90*ec97d23cSSam Shih }; 91*ec97d23cSSam Shih 92*ec97d23cSSam Shih static const char *const i2c_parents[] __initconst = { 93*ec97d23cSSam Shih "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4" 94*ec97d23cSSam Shih }; 95*ec97d23cSSam Shih 96*ec97d23cSSam Shih static const char *const pextp_tl_ck_parents[] __initconst = { 97*ec97d23cSSam Shih "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k" 98*ec97d23cSSam Shih }; 99*ec97d23cSSam Shih 100*ec97d23cSSam Shih static const char *const emmc_250m_parents[] __initconst = { 101*ec97d23cSSam Shih "top_xtal", "top_net1pll_d5_d2" 102*ec97d23cSSam Shih }; 103*ec97d23cSSam Shih 104*ec97d23cSSam Shih static const char *const emmc_416m_parents[] __initconst = { "top_xtal", 105*ec97d23cSSam Shih "mpll" }; 106*ec97d23cSSam Shih 107*ec97d23cSSam Shih static const char *const f_26m_adc_parents[] __initconst = { "top_xtal", 108*ec97d23cSSam Shih "top_mpll_d8_d2" }; 109*ec97d23cSSam Shih 110*ec97d23cSSam Shih static const char *const dramc_md32_parents[] __initconst = { "top_xtal", 111*ec97d23cSSam Shih "top_mpll_d2" }; 112*ec97d23cSSam Shih 113*ec97d23cSSam Shih static const char *const sysaxi_parents[] __initconst = { "top_xtal", 114*ec97d23cSSam Shih "top_net1pll_d8_d2", 115*ec97d23cSSam Shih "top_net2pll_d4" }; 116*ec97d23cSSam Shih 117*ec97d23cSSam Shih static const char *const sysapb_parents[] __initconst = { "top_xtal", 118*ec97d23cSSam Shih "top_mpll_d3_d2", 119*ec97d23cSSam Shih "top_net2pll_d4_d2" }; 120*ec97d23cSSam Shih 121*ec97d23cSSam Shih static const char *const arm_db_main_parents[] __initconst = { 122*ec97d23cSSam Shih "top_xtal", "top_net2pll_d3_d2" 123*ec97d23cSSam Shih }; 124*ec97d23cSSam Shih 125*ec97d23cSSam Shih static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag", 126*ec97d23cSSam Shih "top_xtal" }; 127*ec97d23cSSam Shih 128*ec97d23cSSam Shih static const char *const netsys_parents[] __initconst = { "top_xtal", 129*ec97d23cSSam Shih "top_mmpll_d4" }; 130*ec97d23cSSam Shih 131*ec97d23cSSam Shih static const char *const netsys_500m_parents[] __initconst = { 132*ec97d23cSSam Shih "top_xtal", "top_net1pll_d5" 133*ec97d23cSSam Shih }; 134*ec97d23cSSam Shih 135*ec97d23cSSam Shih static const char *const netsys_mcu_parents[] __initconst = { 136*ec97d23cSSam Shih "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4", 137*ec97d23cSSam Shih "top_net1pll_d5" 138*ec97d23cSSam Shih }; 139*ec97d23cSSam Shih 140*ec97d23cSSam Shih static const char *const netsys_2x_parents[] __initconst = { 141*ec97d23cSSam Shih "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2" 142*ec97d23cSSam Shih }; 143*ec97d23cSSam Shih 144*ec97d23cSSam Shih static const char *const sgm_325m_parents[] __initconst = { "top_xtal", 145*ec97d23cSSam Shih "sgmpll" }; 146*ec97d23cSSam Shih 147*ec97d23cSSam Shih static const char *const sgm_reg_parents[] __initconst = { 148*ec97d23cSSam Shih "top_xtal", "top_net1pll_d8_d4" 149*ec97d23cSSam Shih }; 150*ec97d23cSSam Shih 151*ec97d23cSSam Shih static const char *const a1sys_parents[] __initconst = { "top_xtal", 152*ec97d23cSSam Shih "top_apll2_d4" }; 153*ec97d23cSSam Shih 154*ec97d23cSSam Shih static const char *const conn_mcusys_parents[] __initconst = { "top_xtal", 155*ec97d23cSSam Shih "top_mmpll_d2" }; 156*ec97d23cSSam Shih 157*ec97d23cSSam Shih static const char *const eip_b_parents[] __initconst = { "top_xtal", 158*ec97d23cSSam Shih "net2pll" }; 159*ec97d23cSSam Shih 160*ec97d23cSSam Shih static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2", 161*ec97d23cSSam Shih "top_mpll_d8_d2" }; 162*ec97d23cSSam Shih 163*ec97d23cSSam Shih static const char *const a_tuner_parents[] __initconst = { "top_xtal", 164*ec97d23cSSam Shih "top_apll2_d4", 165*ec97d23cSSam Shih "top_mpll_d8_d2" }; 166*ec97d23cSSam Shih 167*ec97d23cSSam Shih static const char *const u2u3_sys_parents[] __initconst = { 168*ec97d23cSSam Shih "top_xtal", "top_net1pll_d5_d4" 169*ec97d23cSSam Shih }; 170*ec97d23cSSam Shih 171*ec97d23cSSam Shih static const char *const da_u2_refsel_parents[] __initconst = { 172*ec97d23cSSam Shih "top_xtal", "top_mmpll_u2phy" 173*ec97d23cSSam Shih }; 174*ec97d23cSSam Shih 175*ec97d23cSSam Shih static const struct mtk_mux top_muxes[] = { 176*ec97d23cSSam Shih /* CLK_CFG_0 */ 177*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 178*ec97d23cSSam Shih 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), 179*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 180*ec97d23cSSam Shih 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), 181*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 182*ec97d23cSSam Shih 0x004, 0x008, 16, 3, 23, 0x1C0, 2), 183*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 184*ec97d23cSSam Shih 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), 185*ec97d23cSSam Shih /* CLK_CFG_1 */ 186*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 187*ec97d23cSSam Shih 0x014, 0x018, 0, 2, 7, 0x1C0, 4), 188*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 189*ec97d23cSSam Shih 0x014, 0x018, 8, 2, 15, 0x1C0, 5), 190*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 191*ec97d23cSSam Shih 0x014, 0x018, 16, 2, 23, 0x1C0, 6), 192*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", 193*ec97d23cSSam Shih pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 194*ec97d23cSSam Shih 31, 0x1C0, 7), 195*ec97d23cSSam Shih /* CLK_CFG_2 */ 196*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", 197*ec97d23cSSam Shih emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, 198*ec97d23cSSam Shih 0x1C0, 8), 199*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", 200*ec97d23cSSam Shih emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, 201*ec97d23cSSam Shih 0x1C0, 9), 202*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", 203*ec97d23cSSam Shih f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, 204*ec97d23cSSam Shih 0x1C0, 10), 205*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 206*ec97d23cSSam Shih 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), 207*ec97d23cSSam Shih /* CLK_CFG_3 */ 208*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", 209*ec97d23cSSam Shih dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, 210*ec97d23cSSam Shih 0x1C0, 12), 211*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 212*ec97d23cSSam Shih 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), 213*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 214*ec97d23cSSam Shih 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), 215*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", 216*ec97d23cSSam Shih arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 217*ec97d23cSSam Shih 31, 0x1C0, 15), 218*ec97d23cSSam Shih /* CLK_CFG_4 */ 219*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", 220*ec97d23cSSam Shih arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7, 221*ec97d23cSSam Shih 0x1C0, 16), 222*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 223*ec97d23cSSam Shih 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), 224*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", 225*ec97d23cSSam Shih netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 226*ec97d23cSSam Shih 23, 0x1C0, 18), 227*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", 228*ec97d23cSSam Shih netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, 229*ec97d23cSSam Shih 0x1C0, 19), 230*ec97d23cSSam Shih /* CLK_CFG_5 */ 231*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", 232*ec97d23cSSam Shih netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, 233*ec97d23cSSam Shih 0x1C0, 20), 234*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", 235*ec97d23cSSam Shih sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 236*ec97d23cSSam Shih 0x1C0, 21), 237*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", 238*ec97d23cSSam Shih sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, 239*ec97d23cSSam Shih 0x1C0, 22), 240*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 241*ec97d23cSSam Shih 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), 242*ec97d23cSSam Shih /* CLK_CFG_6 */ 243*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", 244*ec97d23cSSam Shih conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7, 245*ec97d23cSSam Shih 0x1C0, 24), 246*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 247*ec97d23cSSam Shih 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), 248*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", 249*ec97d23cSSam Shih f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23, 250*ec97d23cSSam Shih 0x1C0, 26), 251*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", 252*ec97d23cSSam Shih f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, 253*ec97d23cSSam Shih 0x1C0, 27), 254*ec97d23cSSam Shih /* CLK_CFG_7 */ 255*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", 256*ec97d23cSSam Shih f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, 257*ec97d23cSSam Shih 0x1C0, 28), 258*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 259*ec97d23cSSam Shih 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), 260*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", 261*ec97d23cSSam Shih a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23, 262*ec97d23cSSam Shih 0x1C0, 30), 263*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 264*ec97d23cSSam Shih 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), 265*ec97d23cSSam Shih /* CLK_CFG_8 */ 266*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", 267*ec97d23cSSam Shih u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7, 268*ec97d23cSSam Shih 0x1C4, 1), 269*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", 270*ec97d23cSSam Shih u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15, 271*ec97d23cSSam Shih 0x1C4, 2), 272*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", 273*ec97d23cSSam Shih da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1, 274*ec97d23cSSam Shih 23, 0x1C4, 3), 275*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", 276*ec97d23cSSam Shih da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1, 277*ec97d23cSSam Shih 31, 0x1C4, 4), 278*ec97d23cSSam Shih /* CLK_CFG_9 */ 279*ec97d23cSSam Shih MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", 280*ec97d23cSSam Shih sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7, 281*ec97d23cSSam Shih 0x1C4, 5), 282*ec97d23cSSam Shih }; 283*ec97d23cSSam Shih 284*ec97d23cSSam Shih static int clk_mt7986_topckgen_probe(struct platform_device *pdev) 285*ec97d23cSSam Shih { 286*ec97d23cSSam Shih struct clk_onecell_data *clk_data; 287*ec97d23cSSam Shih struct device_node *node = pdev->dev.of_node; 288*ec97d23cSSam Shih int r; 289*ec97d23cSSam Shih void __iomem *base; 290*ec97d23cSSam Shih int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + 291*ec97d23cSSam Shih ARRAY_SIZE(top_muxes); 292*ec97d23cSSam Shih 293*ec97d23cSSam Shih base = of_iomap(node, 0); 294*ec97d23cSSam Shih if (!base) { 295*ec97d23cSSam Shih pr_err("%s(): ioremap failed\n", __func__); 296*ec97d23cSSam Shih return -ENOMEM; 297*ec97d23cSSam Shih } 298*ec97d23cSSam Shih 299*ec97d23cSSam Shih clk_data = mtk_alloc_clk_data(nr); 300*ec97d23cSSam Shih if (!clk_data) 301*ec97d23cSSam Shih return -ENOMEM; 302*ec97d23cSSam Shih 303*ec97d23cSSam Shih mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 304*ec97d23cSSam Shih clk_data); 305*ec97d23cSSam Shih mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 306*ec97d23cSSam Shih mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, 307*ec97d23cSSam Shih &mt7986_clk_lock, clk_data); 308*ec97d23cSSam Shih 309*ec97d23cSSam Shih clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]); 310*ec97d23cSSam Shih clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]); 311*ec97d23cSSam Shih clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]); 312*ec97d23cSSam Shih clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]); 313*ec97d23cSSam Shih clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]); 314*ec97d23cSSam Shih clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]); 315*ec97d23cSSam Shih 316*ec97d23cSSam Shih r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 317*ec97d23cSSam Shih 318*ec97d23cSSam Shih if (r) { 319*ec97d23cSSam Shih pr_err("%s(): could not register clock provider: %d\n", 320*ec97d23cSSam Shih __func__, r); 321*ec97d23cSSam Shih goto free_topckgen_data; 322*ec97d23cSSam Shih } 323*ec97d23cSSam Shih return r; 324*ec97d23cSSam Shih 325*ec97d23cSSam Shih free_topckgen_data: 326*ec97d23cSSam Shih mtk_free_clk_data(clk_data); 327*ec97d23cSSam Shih return r; 328*ec97d23cSSam Shih } 329*ec97d23cSSam Shih 330*ec97d23cSSam Shih static const struct of_device_id of_match_clk_mt7986_topckgen[] = { 331*ec97d23cSSam Shih { .compatible = "mediatek,mt7986-topckgen", }, 332*ec97d23cSSam Shih {} 333*ec97d23cSSam Shih }; 334*ec97d23cSSam Shih 335*ec97d23cSSam Shih static struct platform_driver clk_mt7986_topckgen_drv = { 336*ec97d23cSSam Shih .probe = clk_mt7986_topckgen_probe, 337*ec97d23cSSam Shih .driver = { 338*ec97d23cSSam Shih .name = "clk-mt7986-topckgen", 339*ec97d23cSSam Shih .of_match_table = of_match_clk_mt7986_topckgen, 340*ec97d23cSSam Shih }, 341*ec97d23cSSam Shih }; 342*ec97d23cSSam Shih builtin_platform_driver(clk_mt7986_topckgen_drv); 343