1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2021 MediaTek Inc.
4  * Author: Sam Shih <sam.shih@mediatek.com>
5  * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6  * Author: Jianhui Zhao <zhaojh329@gmail.com>
7  * Author: Daniel Golle <daniel@makrotopia.org>
8  */
9 
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include "clk-mtk.h"
16 #include "clk-gate.h"
17 #include "clk-mux.h"
18 
19 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
20 #include <linux/clk.h>
21 
22 static DEFINE_SPINLOCK(mt7981_clk_lock);
23 
24 static const struct mtk_fixed_factor infra_divs[] = {
25 	FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
26 };
27 
28 static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
29 								"uart_sel" };
30 
31 static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
32 							      "spi_sel" };
33 
34 static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
35 							      "spim_mst_sel" };
36 
37 static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
38 
39 static const char *const infra_pwm_bsel_parents[] __initconst = {
40 	"cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
41 };
42 
43 static const char *const infra_pcie_parents[] __initconst = {
44 	"cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
45 };
46 
47 static const struct mtk_mux infra_muxes[] = {
48 	/* MODULE_CLK_SEL_0 */
49 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
50 			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
51 			     -1, -1, -1),
52 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
53 			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
54 			     -1, -1, -1),
55 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
56 			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
57 			     -1, -1, -1),
58 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
59 			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
60 			     -1, -1, -1),
61 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
62 			     infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
63 			     -1, -1, -1),
64 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
65 			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
66 			     -1, -1, -1),
67 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
68 			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
69 			     -1, -1, -1),
70 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
71 			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
72 			     -1, -1, -1),
73 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
74 			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
75 			     -1, -1, -1),
76 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
77 			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
78 			     2, -1, -1, -1),
79 	/* MODULE_CLK_SEL_1 */
80 	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
81 			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
82 			     -1, -1, -1),
83 };
84 
85 static const struct mtk_gate_regs infra0_cg_regs = {
86 	.set_ofs = 0x40,
87 	.clr_ofs = 0x44,
88 	.sta_ofs = 0x48,
89 };
90 
91 static const struct mtk_gate_regs infra1_cg_regs = {
92 	.set_ofs = 0x50,
93 	.clr_ofs = 0x54,
94 	.sta_ofs = 0x58,
95 };
96 
97 static const struct mtk_gate_regs infra2_cg_regs = {
98 	.set_ofs = 0x60,
99 	.clr_ofs = 0x64,
100 	.sta_ofs = 0x68,
101 };
102 
103 #define GATE_INFRA0(_id, _name, _parent, _shift)                               \
104 	{                                                                      \
105 		.id = _id, .name = _name, .parent_name = _parent,              \
106 		.regs = &infra0_cg_regs, .shift = _shift,                      \
107 		.ops = &mtk_clk_gate_ops_setclr,                               \
108 	}
109 
110 #define GATE_INFRA1(_id, _name, _parent, _shift)                               \
111 	{                                                                      \
112 		.id = _id, .name = _name, .parent_name = _parent,              \
113 		.regs = &infra1_cg_regs, .shift = _shift,                      \
114 		.ops = &mtk_clk_gate_ops_setclr,                               \
115 	}
116 
117 #define GATE_INFRA2(_id, _name, _parent, _shift)                               \
118 	{                                                                      \
119 		.id = _id, .name = _name, .parent_name = _parent,              \
120 		.regs = &infra2_cg_regs, .shift = _shift,                      \
121 		.ops = &mtk_clk_gate_ops_setclr,                               \
122 	}
123 
124 static const struct mtk_gate infra_clks[] = {
125 	/* INFRA0 */
126 	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
127 	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
128 	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
129 	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
130 	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
131 	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
132 
133 	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
134 	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
135 	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
136 	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
137 	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
138 	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
139 		    14),
140 	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
141 	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
142 	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
143 	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
144 	GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
145 	/* INFRA1 */
146 	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
147 	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
148 	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
149 	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
150 	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
151 	GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
152 	GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
153 	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
154 	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
155 	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
156 	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
157 	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
158 	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
159 		    13),
160 	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
161 		    14),
162 	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
163 	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
164 	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
165 	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
166 	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
167 	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
168 	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
169 	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
170 	GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
171 	GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
172 	/* INFRA2 */
173 	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
174 	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
175 	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
176 	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
177 	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
178 	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
179 		    13),
180 	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
181 	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
182 };
183 
184 static const struct mtk_clk_desc infracfg_desc = {
185 	.factor_clks = infra_divs,
186 	.num_factor_clks = ARRAY_SIZE(infra_divs),
187 	.mux_clks = infra_muxes,
188 	.num_mux_clks = ARRAY_SIZE(infra_muxes),
189 	.clks = infra_clks,
190 	.num_clks = ARRAY_SIZE(infra_clks),
191 	.clk_lock = &mt7981_clk_lock,
192 };
193 
194 static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
195 	{ .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc },
196 	{ /* sentinel */ }
197 };
198 
199 static struct platform_driver clk_mt7981_infracfg_drv = {
200 	.probe = mtk_clk_simple_probe,
201 	.remove = mtk_clk_simple_remove,
202 	.driver = {
203 		.name = "clk-mt7981-infracfg",
204 		.of_match_table = of_match_clk_mt7981_infracfg,
205 	},
206 };
207 builtin_platform_driver(clk_mt7981_infracfg_drv);
208