1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 MediaTek Inc.
4  * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5  *	   Ryder Lee <ryder.lee@mediatek.com>
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 
13 #include "clk-cpumux.h"
14 #include "clk-gate.h"
15 #include "clk-mtk.h"
16 #include "clk-pll.h"
17 
18 #include <dt-bindings/clock/mt7629-clk.h>
19 
20 #define MT7629_PLL_FMAX		(2500UL * MHZ)
21 #define CON0_MT7629_RST_BAR	BIT(24)
22 
23 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
24 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
25 			_pcw_shift, _div_table, _parent_name) {		\
26 		.id = _id,						\
27 		.name = _name,						\
28 		.reg = _reg,						\
29 		.pwr_reg = _pwr_reg,					\
30 		.en_mask = _en_mask,					\
31 		.flags = _flags,					\
32 		.rst_bar_mask = CON0_MT7629_RST_BAR,			\
33 		.fmax = MT7629_PLL_FMAX,				\
34 		.pcwbits = _pcwbits,					\
35 		.pd_reg = _pd_reg,					\
36 		.pd_shift = _pd_shift,					\
37 		.tuner_reg = _tuner_reg,				\
38 		.pcw_reg = _pcw_reg,					\
39 		.pcw_shift = _pcw_shift,				\
40 		.div_table = _div_table,				\
41 		.parent_name = _parent_name,				\
42 	}
43 
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
45 		_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,		\
46 		_pcw_shift)						\
47 	PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
48 		_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,	\
49 		NULL, "clk20m")
50 
51 #define GATE_APMIXED(_id, _name, _parent, _shift)			\
52 	GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
53 
54 #define GATE_INFRA(_id, _name, _parent, _shift)				\
55 	GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
56 
57 #define GATE_PERI0(_id, _name, _parent, _shift)				\
58 	GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
59 
60 #define GATE_PERI1(_id, _name, _parent, _shift)				\
61 	GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
62 
63 static DEFINE_SPINLOCK(mt7629_clk_lock);
64 
65 static const char * const axi_parents[] = {
66 	"clkxtal",
67 	"syspll1_d2",
68 	"syspll_d5",
69 	"syspll1_d4",
70 	"univpll_d5",
71 	"univpll2_d2",
72 	"univpll_d7",
73 	"dmpll_ck"
74 };
75 
76 static const char * const mem_parents[] = {
77 	"clkxtal",
78 	"dmpll_ck"
79 };
80 
81 static const char * const ddrphycfg_parents[] = {
82 	"clkxtal",
83 	"syspll1_d8"
84 };
85 
86 static const char * const eth_parents[] = {
87 	"clkxtal",
88 	"syspll1_d2",
89 	"univpll1_d2",
90 	"syspll1_d4",
91 	"univpll_d5",
92 	"sgmiipll_d2",
93 	"univpll_d7",
94 	"dmpll_ck"
95 };
96 
97 static const char * const pwm_parents[] = {
98 	"clkxtal",
99 	"univpll2_d4"
100 };
101 
102 static const char * const f10m_ref_parents[] = {
103 	"clkxtal",
104 	"sgmiipll_d2"
105 };
106 
107 static const char * const nfi_infra_parents[] = {
108 	"clkxtal",
109 	"clkxtal",
110 	"clkxtal",
111 	"clkxtal",
112 	"clkxtal",
113 	"clkxtal",
114 	"univpll2_d8",
115 	"univpll3_d4",
116 	"syspll1_d8",
117 	"univpll1_d8",
118 	"syspll4_d2",
119 	"syspll2_d4",
120 	"univpll2_d4",
121 	"univpll3_d2",
122 	"syspll1_d4",
123 	"syspll_d7"
124 };
125 
126 static const char * const flash_parents[] = {
127 	"clkxtal",
128 	"univpll_d80_d4",
129 	"syspll2_d8",
130 	"syspll3_d4",
131 	"univpll3_d4",
132 	"univpll1_d8",
133 	"syspll2_d4",
134 	"univpll2_d4"
135 };
136 
137 static const char * const uart_parents[] = {
138 	"clkxtal",
139 	"univpll2_d8"
140 };
141 
142 static const char * const spi0_parents[] = {
143 	"clkxtal",
144 	"syspll3_d2",
145 	"clkxtal",
146 	"syspll2_d4",
147 	"syspll4_d2",
148 	"univpll2_d4",
149 	"univpll1_d8",
150 	"clkxtal"
151 };
152 
153 static const char * const spi1_parents[] = {
154 	"clkxtal",
155 	"syspll3_d2",
156 	"clkxtal",
157 	"syspll4_d4",
158 	"syspll4_d2",
159 	"univpll2_d4",
160 	"univpll1_d8",
161 	"clkxtal"
162 };
163 
164 static const char * const msdc30_0_parents[] = {
165 	"clkxtal",
166 	"univpll2_d16",
167 	"univ48m"
168 };
169 
170 static const char * const msdc30_1_parents[] = {
171 	"clkxtal",
172 	"univpll2_d16",
173 	"univ48m",
174 	"syspll2_d4",
175 	"univpll2_d4",
176 	"syspll_d7",
177 	"syspll2_d2",
178 	"univpll2_d2"
179 };
180 
181 static const char * const ap2wbmcu_parents[] = {
182 	"clkxtal",
183 	"syspll1_d2",
184 	"univ48m",
185 	"syspll1_d8",
186 	"univpll2_d4",
187 	"syspll_d7",
188 	"syspll2_d2",
189 	"univpll2_d2"
190 };
191 
192 static const char * const audio_parents[] = {
193 	"clkxtal",
194 	"syspll3_d4",
195 	"syspll4_d4",
196 	"syspll1_d16"
197 };
198 
199 static const char * const aud_intbus_parents[] = {
200 	"clkxtal",
201 	"syspll1_d4",
202 	"syspll4_d2",
203 	"dmpll_d4"
204 };
205 
206 static const char * const pmicspi_parents[] = {
207 	"clkxtal",
208 	"syspll1_d8",
209 	"syspll3_d4",
210 	"syspll1_d16",
211 	"univpll3_d4",
212 	"clkxtal",
213 	"univpll2_d4",
214 	"dmpll_d8"
215 };
216 
217 static const char * const scp_parents[] = {
218 	"clkxtal",
219 	"syspll1_d8",
220 	"univpll2_d2",
221 	"univpll2_d4"
222 };
223 
224 static const char * const atb_parents[] = {
225 	"clkxtal",
226 	"syspll1_d2",
227 	"syspll_d5"
228 };
229 
230 static const char * const hif_parents[] = {
231 	"clkxtal",
232 	"syspll1_d2",
233 	"univpll1_d2",
234 	"syspll1_d4",
235 	"univpll_d5",
236 	"clk_null",
237 	"univpll_d7"
238 };
239 
240 static const char * const sata_parents[] = {
241 	"clkxtal",
242 	"univpll2_d4"
243 };
244 
245 static const char * const usb20_parents[] = {
246 	"clkxtal",
247 	"univpll3_d4",
248 	"syspll1_d8"
249 };
250 
251 static const char * const aud1_parents[] = {
252 	"clkxtal"
253 };
254 
255 static const char * const irrx_parents[] = {
256 	"clkxtal",
257 	"syspll4_d16"
258 };
259 
260 static const char * const crypto_parents[] = {
261 	"clkxtal",
262 	"univpll_d3",
263 	"univpll1_d2",
264 	"syspll1_d2",
265 	"univpll_d5",
266 	"syspll_d5",
267 	"univpll2_d2",
268 	"syspll_d2"
269 };
270 
271 static const char * const gpt10m_parents[] = {
272 	"clkxtal",
273 	"clkxtal_d4"
274 };
275 
276 static const char * const peribus_ck_parents[] = {
277 	"syspll1_d8",
278 	"syspll1_d4"
279 };
280 
281 static const char * const infra_mux1_parents[] = {
282 	"clkxtal",
283 	"armpll",
284 	"main_core_en",
285 	"armpll"
286 };
287 
288 static const struct mtk_gate_regs apmixed_cg_regs = {
289 	.set_ofs = 0x8,
290 	.clr_ofs = 0x8,
291 	.sta_ofs = 0x8,
292 };
293 
294 static const struct mtk_gate_regs infra_cg_regs = {
295 	.set_ofs = 0x40,
296 	.clr_ofs = 0x44,
297 	.sta_ofs = 0x48,
298 };
299 
300 static const struct mtk_gate_regs peri0_cg_regs = {
301 	.set_ofs = 0x8,
302 	.clr_ofs = 0x10,
303 	.sta_ofs = 0x18,
304 };
305 
306 static const struct mtk_gate_regs peri1_cg_regs = {
307 	.set_ofs = 0xC,
308 	.clr_ofs = 0x14,
309 	.sta_ofs = 0x1C,
310 };
311 
312 static const struct mtk_pll_data plls[] = {
313 	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
314 	    0, 21, 0x0204, 24, 0, 0x0204, 0),
315 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
316 	    HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
317 	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
318 	    HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
319 	PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
320 	    0, 21, 0x0300, 1, 0, 0x0304, 0),
321 	PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
322 	    0, 21, 0x0314, 1, 0, 0x0318, 0),
323 	PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
324 	    0, 21, 0x0358, 1, 0, 0x035C, 0),
325 };
326 
327 static const struct mtk_gate apmixed_clks[] = {
328 	GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
329 };
330 
331 static const struct mtk_gate infra_clks[] = {
332 	GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0),
333 	GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2),
334 	GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4),
335 	GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18),
336 	GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19),
337 };
338 
339 static const struct mtk_fixed_clk top_fixed_clks[] = {
340 	FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
341 		  31250000),
342 	FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
343 		  31250000),
344 	FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
345 		  125000000),
346 	FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
347 		  125000000),
348 	FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
349 		  250000000),
350 	FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
351 		  250000000),
352 	FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
353 		  33333333),
354 	FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
355 		  50000000),
356 	FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
357 		  50000000),
358 	FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
359 		  50000000),
360 };
361 
362 static const struct mtk_fixed_factor top_divs[] = {
363 	FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
364 	FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
365 	FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
366 	FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
367 	FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
368 	FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
369 	FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
370 	FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1),
371 	FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1),
372 	FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1),
373 	FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
374 	FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
375 	FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4),
376 	FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8),
377 	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
378 	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
379 	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
380 	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
381 	FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
382 	FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
383 	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
384 	FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
385 	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
386 	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
387 	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
388 	FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
389 	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
390 	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
391 	FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
392 	FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
393 	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
394 	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
395 	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
396 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
397 	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
398 	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
399 	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
400 	FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
401 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
402 	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
403 	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
404 	FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
405 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
406 	FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
407 	FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
408 	FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
409 	FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4),
410 	FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1),
411 	FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1),
412 	FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1),
413 	FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1),
414 	FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1),
415 	FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1),
416 	FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1),
417 	FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1),
418 	FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1),
419 	FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4),
420 	FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1),
421 	FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1),
422 	FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1),
423 	FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1),
424 	FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1),
425 	FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1),
426 };
427 
428 static const struct mtk_gate peri_clks[] = {
429 	/* PERI0 */
430 	GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2),
431 	GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3),
432 	GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4),
433 	GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5),
434 	GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6),
435 	GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7),
436 	GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8),
437 	GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9),
438 	GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12),
439 	GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14),
440 	GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17),
441 	GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18),
442 	GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19),
443 	GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20),
444 	GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22),
445 	GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23),
446 	GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28),
447 	GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29),
448 	GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30),
449 	GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31),
450 	/* PERI1 */
451 	GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1),
452 };
453 
454 static struct mtk_composite infra_muxes[] = {
455 	/* INFRA_TOPCKGEN_CKMUXSEL */
456 	MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000,
457 	    2, 2),
458 };
459 
460 static struct mtk_composite top_muxes[] = {
461 	/* CLK_CFG_0 */
462 	MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
463 		 0x040, 0, 3, 7),
464 	MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
465 		 0x040, 8, 1, 15),
466 	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
467 		 0x040, 16, 1, 23),
468 	MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
469 		 0x040, 24, 3, 31),
470 	/* CLK_CFG_1 */
471 	MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
472 		 0x050, 0, 2, 7),
473 	MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
474 		 0x050, 8, 1, 15),
475 	MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
476 		 0x050, 16, 4, 23),
477 	MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
478 		 0x050, 24, 3, 31),
479 	/* CLK_CFG_2 */
480 	MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
481 		 0x060, 0, 1, 7),
482 	MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
483 		 0x060, 8, 3, 15),
484 	MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
485 		 0x060, 16, 3, 23),
486 	MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
487 		 0x060, 24, 3, 31),
488 	/* CLK_CFG_3 */
489 	MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
490 		 0x070, 0, 3, 7),
491 	MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
492 		 0x070, 8, 3, 15),
493 	MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents,
494 		 0x070, 16, 3, 23),
495 	MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents,
496 		 0x070, 24, 3, 31),
497 	/* CLK_CFG_4 */
498 	MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
499 		 0x080, 0, 2, 7),
500 	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
501 		 0x080, 8, 2, 15),
502 	MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
503 		 0x080, 16, 3, 23),
504 	MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
505 		 0x080, 24, 2, 31),
506 	/* CLK_CFG_5 */
507 	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
508 		 0x090, 0, 2, 7),
509 	MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
510 		 0x090, 8, 3, 15),
511 	MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents,
512 		 0x090, 16, 1, 23),
513 	MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
514 		 0x090, 24, 2, 31),
515 	/* CLK_CFG_6 */
516 	MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
517 		 0x0A0, 0, 1, 7),
518 	MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents,
519 		 0x0A0, 8, 1, 15),
520 	MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents,
521 		 0x0A0, 16, 1, 23),
522 	MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents,
523 		 0x0A0, 24, 1, 31),
524 	/* CLK_CFG_7 */
525 	MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents,
526 		 0x0B0, 0, 2, 7),
527 	MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents,
528 		 0x0B0, 8, 2, 15),
529 	MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents,
530 		 0x0B0, 16, 2, 23),
531 	MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents,
532 		 0x0B0, 24, 2, 31),
533 	/* CLK_CFG_8 */
534 	MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents,
535 		 0x0C0, 0, 3, 7),
536 	MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents,
537 		 0x0C0, 8, 1, 15),
538 	MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents,
539 		 0x0C0, 16, 1, 23),
540 };
541 
542 static struct mtk_composite peri_muxes[] = {
543 	/* PERI_GLOBALCON_CKSEL */
544 	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
545 };
546 
547 static int mtk_topckgen_init(struct platform_device *pdev)
548 {
549 	struct clk_hw_onecell_data *clk_data;
550 	void __iomem *base;
551 	struct device_node *node = pdev->dev.of_node;
552 
553 	base = devm_platform_ioremap_resource(pdev, 0);
554 	if (IS_ERR(base))
555 		return PTR_ERR(base);
556 
557 	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
558 
559 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
560 				    clk_data);
561 
562 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
563 				 clk_data);
564 
565 	mtk_clk_register_composites(&pdev->dev, top_muxes,
566 				    ARRAY_SIZE(top_muxes), base,
567 				    &mt7629_clk_lock, clk_data);
568 
569 	clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
570 	clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
571 	clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
572 
573 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
574 }
575 
576 static int mtk_infrasys_init(struct platform_device *pdev)
577 {
578 	struct device_node *node = pdev->dev.of_node;
579 	struct clk_hw_onecell_data *clk_data;
580 
581 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
582 
583 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
584 			       ARRAY_SIZE(infra_clks), clk_data);
585 
586 	mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
587 				  ARRAY_SIZE(infra_muxes), clk_data);
588 
589 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
590 				      clk_data);
591 }
592 
593 static int mtk_pericfg_init(struct platform_device *pdev)
594 {
595 	struct clk_hw_onecell_data *clk_data;
596 	void __iomem *base;
597 	int r;
598 	struct device_node *node = pdev->dev.of_node;
599 
600 	base = devm_platform_ioremap_resource(pdev, 0);
601 	if (IS_ERR(base))
602 		return PTR_ERR(base);
603 
604 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
605 
606 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
607 			       ARRAY_SIZE(peri_clks), clk_data);
608 
609 	mtk_clk_register_composites(&pdev->dev, peri_muxes,
610 				    ARRAY_SIZE(peri_muxes), base,
611 				    &mt7629_clk_lock, clk_data);
612 
613 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
614 	if (r)
615 		return r;
616 
617 	clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
618 
619 	return 0;
620 }
621 
622 static int mtk_apmixedsys_init(struct platform_device *pdev)
623 {
624 	struct clk_hw_onecell_data *clk_data;
625 	struct device_node *node = pdev->dev.of_node;
626 
627 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
628 	if (!clk_data)
629 		return -ENOMEM;
630 
631 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
632 			      clk_data);
633 
634 	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
635 			       ARRAY_SIZE(apmixed_clks), clk_data);
636 
637 	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
638 	clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
639 
640 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
641 }
642 
643 
644 static const struct of_device_id of_match_clk_mt7629[] = {
645 	{
646 		.compatible = "mediatek,mt7629-apmixedsys",
647 		.data = mtk_apmixedsys_init,
648 	}, {
649 		.compatible = "mediatek,mt7629-infracfg",
650 		.data = mtk_infrasys_init,
651 	}, {
652 		.compatible = "mediatek,mt7629-topckgen",
653 		.data = mtk_topckgen_init,
654 	}, {
655 		.compatible = "mediatek,mt7629-pericfg",
656 		.data = mtk_pericfg_init,
657 	}, {
658 		/* sentinel */
659 	}
660 };
661 MODULE_DEVICE_TABLE(of, of_match_clk_mt7629);
662 
663 static int clk_mt7629_probe(struct platform_device *pdev)
664 {
665 	int (*clk_init)(struct platform_device *);
666 	int r;
667 
668 	clk_init = of_device_get_match_data(&pdev->dev);
669 	if (!clk_init)
670 		return -EINVAL;
671 
672 	r = clk_init(pdev);
673 	if (r)
674 		dev_err(&pdev->dev,
675 			"could not register clock provider: %s: %d\n",
676 			pdev->name, r);
677 
678 	return r;
679 }
680 
681 static struct platform_driver clk_mt7629_drv = {
682 	.probe = clk_mt7629_probe,
683 	.driver = {
684 		.name = "clk-mt7629",
685 		.of_match_table = of_match_clk_mt7629,
686 	},
687 };
688 
689 static int clk_mt7629_init(void)
690 {
691 	return platform_driver_register(&clk_mt7629_drv);
692 }
693 
694 arch_initcall(clk_mt7629_init);
695 MODULE_LICENSE("GPL");
696