1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 MediaTek Inc.
4  * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5  *	   Ryder Lee <ryder.lee@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 
14 #include "clk-mtk.h"
15 #include "clk-gate.h"
16 
17 #include <dt-bindings/clock/mt7629-clk.h>
18 
19 #define GATE_ETH(_id, _name, _parent, _shift) {		\
20 		.id = _id,				\
21 		.name = _name,				\
22 		.parent_name = _parent,			\
23 		.regs = &eth_cg_regs,			\
24 		.shift = _shift,			\
25 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
26 	}
27 
28 static const struct mtk_gate_regs eth_cg_regs = {
29 	.set_ofs = 0x30,
30 	.clr_ofs = 0x30,
31 	.sta_ofs = 0x30,
32 };
33 
34 static const struct mtk_gate eth_clks[] = {
35 	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
36 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
37 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
38 	GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
39 	GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
40 };
41 
42 static const struct mtk_gate_regs sgmii_cg_regs = {
43 	.set_ofs = 0xE4,
44 	.clr_ofs = 0xE4,
45 	.sta_ofs = 0xE4,
46 };
47 
48 #define GATE_SGMII(_id, _name, _parent, _shift) {	\
49 		.id = _id,				\
50 		.name = _name,				\
51 		.parent_name = _parent,			\
52 		.regs = &sgmii_cg_regs,			\
53 		.shift = _shift,			\
54 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
55 	}
56 
57 static const struct mtk_gate sgmii_clks[2][4] = {
58 	{
59 		GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
60 			   "ssusb_tx250m", 2),
61 		GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
62 			   "ssusb_eq_rx250m", 3),
63 		GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
64 			   "ssusb_cdr_ref", 4),
65 		GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
66 			   "ssusb_cdr_fb", 5),
67 	}, {
68 		GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
69 			   "ssusb_tx250m", 2),
70 		GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
71 			   "ssusb_eq_rx250m", 3),
72 		GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
73 			   "ssusb_cdr_ref", 4),
74 		GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
75 			   "ssusb_cdr_fb", 5),
76 	}
77 };
78 
79 static u16 rst_ofs[] = { 0x34, };
80 
81 static const struct mtk_clk_rst_desc clk_rst_desc = {
82 	.version = MTK_RST_SIMPLE,
83 	.rst_bank_ofs = rst_ofs,
84 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
85 };
86 
87 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
88 {
89 	struct clk_hw_onecell_data *clk_data;
90 	struct device_node *node = pdev->dev.of_node;
91 	int r;
92 
93 	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
94 
95 	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
96 			       CLK_ETH_NR_CLK, clk_data);
97 
98 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
99 	if (r)
100 		dev_err(&pdev->dev,
101 			"could not register clock provider: %s: %d\n",
102 			pdev->name, r);
103 
104 	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
105 
106 	return r;
107 }
108 
109 static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
110 {
111 	struct clk_hw_onecell_data *clk_data;
112 	struct device_node *node = pdev->dev.of_node;
113 	static int id;
114 	int r;
115 
116 	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
117 
118 	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
119 			       CLK_SGMII_NR_CLK, clk_data);
120 
121 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
122 	if (r)
123 		dev_err(&pdev->dev,
124 			"could not register clock provider: %s: %d\n",
125 			pdev->name, r);
126 
127 	return r;
128 }
129 
130 static const struct of_device_id of_match_clk_mt7629_eth[] = {
131 	{
132 		.compatible = "mediatek,mt7629-ethsys",
133 		.data = clk_mt7629_ethsys_init,
134 	}, {
135 		.compatible = "mediatek,mt7629-sgmiisys",
136 		.data = clk_mt7629_sgmiisys_init,
137 	}, {
138 		/* sentinel */
139 	}
140 };
141 
142 static int clk_mt7629_eth_probe(struct platform_device *pdev)
143 {
144 	int (*clk_init)(struct platform_device *);
145 	int r;
146 
147 	clk_init = of_device_get_match_data(&pdev->dev);
148 	if (!clk_init)
149 		return -EINVAL;
150 
151 	r = clk_init(pdev);
152 	if (r)
153 		dev_err(&pdev->dev,
154 			"could not register clock provider: %s: %d\n",
155 			pdev->name, r);
156 
157 	return r;
158 }
159 
160 static struct platform_driver clk_mt7629_eth_drv = {
161 	.probe = clk_mt7629_eth_probe,
162 	.driver = {
163 		.name = "clk-mt7629-eth",
164 		.of_match_table = of_match_clk_mt7629_eth,
165 	},
166 };
167 
168 builtin_platform_driver(clk_mt7629_eth_drv);
169