1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 MediaTek Inc.
4  * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5  *	   Ryder Lee <ryder.lee@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 
14 #include "clk-mtk.h"
15 #include "clk-gate.h"
16 
17 #include <dt-bindings/clock/mt7629-clk.h>
18 
19 #define GATE_ETH(_id, _name, _parent, _shift)			\
20 	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
21 
22 static const struct mtk_gate_regs eth_cg_regs = {
23 	.set_ofs = 0x30,
24 	.clr_ofs = 0x30,
25 	.sta_ofs = 0x30,
26 };
27 
28 static const struct mtk_gate eth_clks[] = {
29 	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
30 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
31 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
32 	GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
33 	GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
34 };
35 
36 static const struct mtk_gate_regs sgmii_cg_regs = {
37 	.set_ofs = 0xE4,
38 	.clr_ofs = 0xE4,
39 	.sta_ofs = 0xE4,
40 };
41 
42 #define GATE_SGMII(_id, _name, _parent, _shift)			\
43 	GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
44 
45 static const struct mtk_gate sgmii_clks[2][4] = {
46 	{
47 		GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
48 			   "ssusb_tx250m", 2),
49 		GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
50 			   "ssusb_eq_rx250m", 3),
51 		GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
52 			   "ssusb_cdr_ref", 4),
53 		GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
54 			   "ssusb_cdr_fb", 5),
55 	}, {
56 		GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
57 			   "ssusb_tx250m", 2),
58 		GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
59 			   "ssusb_eq_rx250m", 3),
60 		GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
61 			   "ssusb_cdr_ref", 4),
62 		GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
63 			   "ssusb_cdr_fb", 5),
64 	}
65 };
66 
67 static u16 rst_ofs[] = { 0x34, };
68 
69 static const struct mtk_clk_rst_desc clk_rst_desc = {
70 	.version = MTK_RST_SIMPLE,
71 	.rst_bank_ofs = rst_ofs,
72 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
73 };
74 
75 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
76 {
77 	struct clk_hw_onecell_data *clk_data;
78 	struct device_node *node = pdev->dev.of_node;
79 	int r;
80 
81 	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
82 
83 	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
84 			       CLK_ETH_NR_CLK, clk_data);
85 
86 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
87 	if (r)
88 		dev_err(&pdev->dev,
89 			"could not register clock provider: %s: %d\n",
90 			pdev->name, r);
91 
92 	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
93 
94 	return r;
95 }
96 
97 static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
98 {
99 	struct clk_hw_onecell_data *clk_data;
100 	struct device_node *node = pdev->dev.of_node;
101 	static int id;
102 	int r;
103 
104 	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
105 
106 	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
107 			       CLK_SGMII_NR_CLK, clk_data);
108 
109 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
110 	if (r)
111 		dev_err(&pdev->dev,
112 			"could not register clock provider: %s: %d\n",
113 			pdev->name, r);
114 
115 	return r;
116 }
117 
118 static const struct of_device_id of_match_clk_mt7629_eth[] = {
119 	{
120 		.compatible = "mediatek,mt7629-ethsys",
121 		.data = clk_mt7629_ethsys_init,
122 	}, {
123 		.compatible = "mediatek,mt7629-sgmiisys",
124 		.data = clk_mt7629_sgmiisys_init,
125 	}, {
126 		/* sentinel */
127 	}
128 };
129 MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_eth);
130 
131 static int clk_mt7629_eth_probe(struct platform_device *pdev)
132 {
133 	int (*clk_init)(struct platform_device *);
134 	int r;
135 
136 	clk_init = of_device_get_match_data(&pdev->dev);
137 	if (!clk_init)
138 		return -EINVAL;
139 
140 	r = clk_init(pdev);
141 	if (r)
142 		dev_err(&pdev->dev,
143 			"could not register clock provider: %s: %d\n",
144 			pdev->name, r);
145 
146 	return r;
147 }
148 
149 static struct platform_driver clk_mt7629_eth_drv = {
150 	.probe = clk_mt7629_eth_probe,
151 	.driver = {
152 		.name = "clk-mt7629-eth",
153 		.of_match_table = of_match_clk_mt7629_eth,
154 	},
155 };
156 
157 builtin_platform_driver(clk_mt7629_eth_drv);
158 MODULE_LICENSE("GPL");
159