1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 MediaTek Inc.
4  * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5  *	   Ryder Lee <ryder.lee@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 
14 #include "clk-mtk.h"
15 #include "clk-gate.h"
16 
17 #include <dt-bindings/clock/mt7629-clk.h>
18 
19 #define GATE_ETH(_id, _name, _parent, _shift) {		\
20 		.id = _id,				\
21 		.name = _name,				\
22 		.parent_name = _parent,			\
23 		.regs = &eth_cg_regs,			\
24 		.shift = _shift,			\
25 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
26 	}
27 
28 static const struct mtk_gate_regs eth_cg_regs = {
29 	.set_ofs = 0x30,
30 	.clr_ofs = 0x30,
31 	.sta_ofs = 0x30,
32 };
33 
34 static const struct mtk_gate eth_clks[] = {
35 	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
36 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
37 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
38 	GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
39 	GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
40 };
41 
42 static const struct mtk_gate_regs sgmii_cg_regs = {
43 	.set_ofs = 0xE4,
44 	.clr_ofs = 0xE4,
45 	.sta_ofs = 0xE4,
46 };
47 
48 #define GATE_SGMII(_id, _name, _parent, _shift) {	\
49 		.id = _id,				\
50 		.name = _name,				\
51 		.parent_name = _parent,			\
52 		.regs = &sgmii_cg_regs,			\
53 		.shift = _shift,			\
54 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
55 	}
56 
57 static const struct mtk_gate sgmii_clks[2][4] = {
58 	{
59 		GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
60 			   "ssusb_tx250m", 2),
61 		GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
62 			   "ssusb_eq_rx250m", 3),
63 		GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
64 			   "ssusb_cdr_ref", 4),
65 		GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
66 			   "ssusb_cdr_fb", 5),
67 	}, {
68 		GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
69 			   "ssusb_tx250m", 2),
70 		GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
71 			   "ssusb_eq_rx250m", 3),
72 		GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
73 			   "ssusb_cdr_ref", 4),
74 		GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
75 			   "ssusb_cdr_fb", 5),
76 	}
77 };
78 
79 static u16 rst_ofs[] = { 0x34, };
80 
81 static const struct mtk_clk_rst_desc clk_rst_desc = {
82 	.version = MTK_RST_SIMPLE,
83 	.rst_bank_ofs = rst_ofs,
84 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
85 };
86 
87 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
88 {
89 	struct clk_hw_onecell_data *clk_data;
90 	struct device_node *node = pdev->dev.of_node;
91 	int r;
92 
93 	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
94 
95 	mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
96 
97 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
98 	if (r)
99 		dev_err(&pdev->dev,
100 			"could not register clock provider: %s: %d\n",
101 			pdev->name, r);
102 
103 	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
104 
105 	return r;
106 }
107 
108 static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
109 {
110 	struct clk_hw_onecell_data *clk_data;
111 	struct device_node *node = pdev->dev.of_node;
112 	static int id;
113 	int r;
114 
115 	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
116 
117 	mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
118 			       clk_data);
119 
120 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
121 	if (r)
122 		dev_err(&pdev->dev,
123 			"could not register clock provider: %s: %d\n",
124 			pdev->name, r);
125 
126 	return r;
127 }
128 
129 static const struct of_device_id of_match_clk_mt7629_eth[] = {
130 	{
131 		.compatible = "mediatek,mt7629-ethsys",
132 		.data = clk_mt7629_ethsys_init,
133 	}, {
134 		.compatible = "mediatek,mt7629-sgmiisys",
135 		.data = clk_mt7629_sgmiisys_init,
136 	}, {
137 		/* sentinel */
138 	}
139 };
140 
141 static int clk_mt7629_eth_probe(struct platform_device *pdev)
142 {
143 	int (*clk_init)(struct platform_device *);
144 	int r;
145 
146 	clk_init = of_device_get_match_data(&pdev->dev);
147 	if (!clk_init)
148 		return -EINVAL;
149 
150 	r = clk_init(pdev);
151 	if (r)
152 		dev_err(&pdev->dev,
153 			"could not register clock provider: %s: %d\n",
154 			pdev->name, r);
155 
156 	return r;
157 }
158 
159 static struct platform_driver clk_mt7629_eth_drv = {
160 	.probe = clk_mt7629_eth_probe,
161 	.driver = {
162 		.name = "clk-mt7629-eth",
163 		.of_match_table = of_match_clk_mt7629_eth,
164 	},
165 };
166 
167 builtin_platform_driver(clk_mt7629_eth_drv);
168