1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017 MediaTek Inc.
4  * Author: Chen Zhong <chen.zhong@mediatek.com>
5  *	   Sean Wang <sean.wang@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 
14 #include "clk-cpumux.h"
15 #include "clk-gate.h"
16 #include "clk-mtk.h"
17 #include "clk-pll.h"
18 
19 #include <dt-bindings/clock/mt7622-clk.h>
20 #include <linux/clk.h> /* for consumer */
21 
22 #define MT7622_PLL_FMAX		(2500UL * MHZ)
23 #define CON0_MT7622_RST_BAR	BIT(27)
24 
25 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
26 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
27 			_pcw_shift, _div_table, _parent_name) {		\
28 		.id = _id,						\
29 		.name = _name,						\
30 		.reg = _reg,						\
31 		.pwr_reg = _pwr_reg,					\
32 		.en_mask = _en_mask,					\
33 		.flags = _flags,					\
34 		.rst_bar_mask = CON0_MT7622_RST_BAR,			\
35 		.fmax = MT7622_PLL_FMAX,				\
36 		.pcwbits = _pcwbits,					\
37 		.pd_reg = _pd_reg,					\
38 		.pd_shift = _pd_shift,					\
39 		.tuner_reg = _tuner_reg,				\
40 		.pcw_reg = _pcw_reg,					\
41 		.pcw_shift = _pcw_shift,				\
42 		.div_table = _div_table,				\
43 		.parent_name = _parent_name,				\
44 	}
45 
46 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
47 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
48 			_pcw_shift)					\
49 	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
50 		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,  \
51 		 NULL, "clkxtal")
52 
53 #define GATE_APMIXED(_id, _name, _parent, _shift) {			\
54 		.id = _id,						\
55 		.name = _name,						\
56 		.parent_name = _parent,					\
57 		.regs = &apmixed_cg_regs,				\
58 		.shift = _shift,					\
59 		.ops = &mtk_clk_gate_ops_no_setclr_inv,			\
60 	}
61 
62 #define GATE_INFRA(_id, _name, _parent, _shift) {			\
63 		.id = _id,						\
64 		.name = _name,						\
65 		.parent_name = _parent,					\
66 		.regs = &infra_cg_regs,					\
67 		.shift = _shift,					\
68 		.ops = &mtk_clk_gate_ops_setclr,			\
69 	}
70 
71 #define GATE_TOP0(_id, _name, _parent, _shift) {			\
72 		.id = _id,						\
73 		.name = _name,						\
74 		.parent_name = _parent,					\
75 		.regs = &top0_cg_regs,					\
76 		.shift = _shift,					\
77 		.ops = &mtk_clk_gate_ops_no_setclr,			\
78 	}
79 
80 #define GATE_TOP1(_id, _name, _parent, _shift) {			\
81 		.id = _id,						\
82 		.name = _name,						\
83 		.parent_name = _parent,					\
84 		.regs = &top1_cg_regs,					\
85 		.shift = _shift,					\
86 		.ops = &mtk_clk_gate_ops_no_setclr,			\
87 	}
88 
89 #define GATE_PERI0(_id, _name, _parent, _shift) {			\
90 		.id = _id,						\
91 		.name = _name,						\
92 		.parent_name = _parent,					\
93 		.regs = &peri0_cg_regs,					\
94 		.shift = _shift,					\
95 		.ops = &mtk_clk_gate_ops_setclr,			\
96 	}
97 
98 #define GATE_PERI1(_id, _name, _parent, _shift) {			\
99 		.id = _id,						\
100 		.name = _name,						\
101 		.parent_name = _parent,					\
102 		.regs = &peri1_cg_regs,					\
103 		.shift = _shift,					\
104 		.ops = &mtk_clk_gate_ops_setclr,			\
105 	}
106 
107 static DEFINE_SPINLOCK(mt7622_clk_lock);
108 
109 static const char * const infra_mux1_parents[] = {
110 	"clkxtal",
111 	"armpll",
112 	"main_core_en",
113 	"armpll"
114 };
115 
116 static const char * const axi_parents[] = {
117 	"clkxtal",
118 	"syspll1_d2",
119 	"syspll_d5",
120 	"syspll1_d4",
121 	"univpll_d5",
122 	"univpll2_d2",
123 	"univpll_d7"
124 };
125 
126 static const char * const mem_parents[] = {
127 	"clkxtal",
128 	"dmpll_ck"
129 };
130 
131 static const char * const ddrphycfg_parents[] = {
132 	"clkxtal",
133 	"syspll1_d8"
134 };
135 
136 static const char * const eth_parents[] = {
137 	"clkxtal",
138 	"syspll1_d2",
139 	"univpll1_d2",
140 	"syspll1_d4",
141 	"univpll_d5",
142 	"clk_null",
143 	"univpll_d7"
144 };
145 
146 static const char * const pwm_parents[] = {
147 	"clkxtal",
148 	"univpll2_d4"
149 };
150 
151 static const char * const f10m_ref_parents[] = {
152 	"clkxtal",
153 	"syspll4_d16"
154 };
155 
156 static const char * const nfi_infra_parents[] = {
157 	"clkxtal",
158 	"clkxtal",
159 	"clkxtal",
160 	"clkxtal",
161 	"clkxtal",
162 	"clkxtal",
163 	"clkxtal",
164 	"clkxtal",
165 	"univpll2_d8",
166 	"syspll1_d8",
167 	"univpll1_d8",
168 	"syspll4_d2",
169 	"univpll2_d4",
170 	"univpll3_d2",
171 	"syspll1_d4"
172 };
173 
174 static const char * const flash_parents[] = {
175 	"clkxtal",
176 	"univpll_d80_d4",
177 	"syspll2_d8",
178 	"syspll3_d4",
179 	"univpll3_d4",
180 	"univpll1_d8",
181 	"syspll2_d4",
182 	"univpll2_d4"
183 };
184 
185 static const char * const uart_parents[] = {
186 	"clkxtal",
187 	"univpll2_d8"
188 };
189 
190 static const char * const spi0_parents[] = {
191 	"clkxtal",
192 	"syspll3_d2",
193 	"clkxtal",
194 	"syspll2_d4",
195 	"syspll4_d2",
196 	"univpll2_d4",
197 	"univpll1_d8",
198 	"clkxtal"
199 };
200 
201 static const char * const spi1_parents[] = {
202 	"clkxtal",
203 	"syspll3_d2",
204 	"clkxtal",
205 	"syspll4_d4",
206 	"syspll4_d2",
207 	"univpll2_d4",
208 	"univpll1_d8",
209 	"clkxtal"
210 };
211 
212 static const char * const msdc30_0_parents[] = {
213 	"clkxtal",
214 	"univpll2_d16",
215 	"univ48m"
216 };
217 
218 static const char * const a1sys_hp_parents[] = {
219 	"clkxtal",
220 	"aud1pll_ck",
221 	"aud2pll_ck",
222 	"clkxtal"
223 };
224 
225 static const char * const intdir_parents[] = {
226 	"clkxtal",
227 	"syspll_d2",
228 	"univpll_d2",
229 	"sgmiipll_ck"
230 };
231 
232 static const char * const aud_intbus_parents[] = {
233 	"clkxtal",
234 	"syspll1_d4",
235 	"syspll4_d2",
236 	"syspll3_d2"
237 };
238 
239 static const char * const pmicspi_parents[] = {
240 	"clkxtal",
241 	"clk_null",
242 	"clk_null",
243 	"clk_null",
244 	"clk_null",
245 	"univpll2_d16"
246 };
247 
248 static const char * const atb_parents[] = {
249 	"clkxtal",
250 	"syspll1_d2",
251 	"syspll_d5"
252 };
253 
254 static const char * const audio_parents[] = {
255 	"clkxtal",
256 	"syspll3_d4",
257 	"syspll4_d4",
258 	"univpll1_d16"
259 };
260 
261 static const char * const usb20_parents[] = {
262 	"clkxtal",
263 	"univpll3_d4",
264 	"syspll1_d8",
265 	"clkxtal"
266 };
267 
268 static const char * const aud1_parents[] = {
269 	"clkxtal",
270 	"aud1pll_ck"
271 };
272 
273 static const char * const aud2_parents[] = {
274 	"clkxtal",
275 	"aud2pll_ck"
276 };
277 
278 static const char * const asm_l_parents[] = {
279 	"clkxtal",
280 	"syspll_d5",
281 	"univpll2_d2",
282 	"univpll2_d4"
283 };
284 
285 static const char * const apll1_ck_parents[] = {
286 	"aud1_sel",
287 	"aud2_sel"
288 };
289 
290 static const char * const peribus_ck_parents[] = {
291 	"syspll1_d8",
292 	"syspll1_d4"
293 };
294 
295 static const struct mtk_gate_regs apmixed_cg_regs = {
296 	.set_ofs = 0x8,
297 	.clr_ofs = 0x8,
298 	.sta_ofs = 0x8,
299 };
300 
301 static const struct mtk_gate_regs infra_cg_regs = {
302 	.set_ofs = 0x40,
303 	.clr_ofs = 0x44,
304 	.sta_ofs = 0x48,
305 };
306 
307 static const struct mtk_gate_regs top0_cg_regs = {
308 	.set_ofs = 0x120,
309 	.clr_ofs = 0x120,
310 	.sta_ofs = 0x120,
311 };
312 
313 static const struct mtk_gate_regs top1_cg_regs = {
314 	.set_ofs = 0x128,
315 	.clr_ofs = 0x128,
316 	.sta_ofs = 0x128,
317 };
318 
319 static const struct mtk_gate_regs peri0_cg_regs = {
320 	.set_ofs = 0x8,
321 	.clr_ofs = 0x10,
322 	.sta_ofs = 0x18,
323 };
324 
325 static const struct mtk_gate_regs peri1_cg_regs = {
326 	.set_ofs = 0xC,
327 	.clr_ofs = 0x14,
328 	.sta_ofs = 0x1C,
329 };
330 
331 static const struct mtk_pll_data plls[] = {
332 	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
333 	    PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
334 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
335 	    HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
336 	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
337 	    HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
338 	PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
339 	    0, 21, 0x0300, 1, 0, 0x0304, 0),
340 	PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
341 	    0, 21, 0x0314, 1, 0, 0x0318, 0),
342 	PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0,
343 	    0, 31, 0x0324, 1, 0, 0x0328, 0),
344 	PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0,
345 	    0, 31, 0x0334, 1, 0, 0x0338, 0),
346 	PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0,
347 	    0, 21, 0x0344, 1, 0, 0x0348, 0),
348 	PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
349 	    0, 21, 0x0358, 1, 0, 0x035C, 0),
350 };
351 
352 static const struct mtk_gate apmixed_clks[] = {
353 	GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
354 };
355 
356 static const struct mtk_gate infra_clks[] = {
357 	GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
358 	GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
359 	GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
360 	GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
361 	GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
362 	GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
363 };
364 
365 static const struct mtk_fixed_clk top_fixed_clks[] = {
366 	FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
367 		  31250000),
368 	FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
369 		  31250000),
370 	FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
371 		  125000000),
372 	FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
373 		  125000000),
374 	FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
375 		  250000000),
376 	FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
377 		  250000000),
378 	FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
379 		  33333333),
380 	FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
381 		  50000000),
382 	FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
383 		  50000000),
384 	FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
385 		  50000000),
386 };
387 
388 static const struct mtk_fixed_factor top_divs[] = {
389 	FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
390 	FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
391 	FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
392 	FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
393 	FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
394 	FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
395 	FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
396 	FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
397 	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
398 	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
399 	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
400 	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
401 	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
402 	FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
403 	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
404 	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
405 	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
406 	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
407 	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
408 	FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
409 	FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
410 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
411 	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
412 	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
413 	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
414 	FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
415 	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
416 	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
417 	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
418 	FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
419 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
420 	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
421 	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
422 	FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
423 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
424 	FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
425 	FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
426 	FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
427 	FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
428 	FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
429 	FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
430 	FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
431 	FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
432 	FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
433 	FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
434 	FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
435 };
436 
437 static const struct mtk_gate top_clks[] = {
438 	/* TOP0 */
439 	GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
440 	GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
441 	GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
442 		  2),
443 	GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
444 		  3),
445 	GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
446 		  4),
447 	GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
448 		  5),
449 
450 	/* TOP1 */
451 	GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
452 	GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
453 };
454 
455 static const struct mtk_clk_divider top_adj_divs[] = {
456 	DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
457 		0x120, 24, 3),
458 	DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
459 		0x120, 28, 3),
460 	DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
461 		0x124, 0, 7),
462 	DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
463 		0x124, 8, 7),
464 	DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
465 		0x124, 16, 7),
466 	DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
467 		0x124, 24, 7),
468 	DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
469 		0x128, 8, 7),
470 	DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
471 		0x128, 24, 7),
472 };
473 
474 static const struct mtk_gate peri_clks[] = {
475 	/* PERI0 */
476 	GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
477 	GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
478 	GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
479 	GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
480 	GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
481 	GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
482 	GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
483 	GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
484 	GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
485 	GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
486 	GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
487 	GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
488 	GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
489 	GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
490 	GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
491 	GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
492 	GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
493 	GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
494 	GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
495 	GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
496 	GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
497 	GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
498 	GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
499 	GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
500 	GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
501 	GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
502 	GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
503 
504 	/* PERI1 */
505 	GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
506 	GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
507 };
508 
509 static struct mtk_composite infra_muxes[] = {
510 	MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
511 	    0x000, 2, 2),
512 };
513 
514 static struct mtk_composite top_muxes[] = {
515 	/* CLK_CFG_0 */
516 	MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
517 		 0x040, 0, 3, 7),
518 	MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
519 		 0x040, 8, 1, 15),
520 	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
521 		 0x040, 16, 1, 23),
522 	MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
523 		 0x040, 24, 3, 31),
524 
525 	/* CLK_CFG_1 */
526 	MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
527 		 0x050, 0, 2, 7),
528 	MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
529 		 0x050, 8, 1, 15),
530 	MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
531 		 0x050, 16, 4, 23),
532 	MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
533 		 0x050, 24, 3, 31),
534 
535 	/* CLK_CFG_2 */
536 	MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
537 		 0x060, 0, 1, 7),
538 	MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
539 		 0x060, 8, 3, 15),
540 	MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
541 		 0x060, 16, 3, 23),
542 	MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
543 		 0x060, 24, 3, 31),
544 
545 	/* CLK_CFG_3 */
546 	MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
547 		 0x070, 0, 3, 7),
548 	MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
549 		 0x070, 8, 3, 15),
550 	MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
551 		 0x070, 16, 2, 23),
552 	MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
553 		 0x070, 24, 2, 31),
554 
555 	/* CLK_CFG_4 */
556 	MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
557 		 0x080, 0, 2, 7),
558 	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
559 		 0x080, 8, 2, 15),
560 	MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
561 		 0x080, 16, 3, 23),
562 	MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
563 		 0x080, 24, 2, 31),
564 
565 	/* CLK_CFG_5 */
566 	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
567 		 0x090, 0, 2, 7),
568 	MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
569 		 0x090, 8, 3, 15),
570 	MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
571 		 0x090, 16, 2, 23),
572 	MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
573 		 0x090, 24, 2, 31),
574 
575 	/* CLK_CFG_6 */
576 	MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
577 		 0x0A0, 0, 1, 7),
578 	MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
579 		 0x0A0, 8, 1, 15),
580 	MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
581 		 0x0A0, 16, 1, 23),
582 	MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
583 		 0x0A0, 24, 1, 31),
584 
585 	/* CLK_CFG_7 */
586 	MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
587 		 0x0B0, 0, 2, 7),
588 	MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
589 		 0x0B0, 8, 2, 15),
590 	MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
591 		 0x0B0, 16, 2, 23),
592 
593 	/* CLK_AUDDIV_0 */
594 	MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
595 	    0x120, 6, 1),
596 	MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
597 	    0x120, 7, 1),
598 	MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
599 	    0x120, 8, 1),
600 	MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
601 	    0x120, 9, 1),
602 	MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
603 	    0x120, 10, 1),
604 	MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
605 	    0x120, 11, 1),
606 };
607 
608 static struct mtk_composite peri_muxes[] = {
609 	/* PERI_GLOBALCON_CKSEL */
610 	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
611 };
612 
613 static int mtk_topckgen_init(struct platform_device *pdev)
614 {
615 	struct clk_hw_onecell_data *clk_data;
616 	void __iomem *base;
617 	struct device_node *node = pdev->dev.of_node;
618 
619 	base = devm_platform_ioremap_resource(pdev, 0);
620 	if (IS_ERR(base))
621 		return PTR_ERR(base);
622 
623 	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
624 
625 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
626 				    clk_data);
627 
628 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
629 				 clk_data);
630 
631 	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
632 				    base, &mt7622_clk_lock, clk_data);
633 
634 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
635 				  base, &mt7622_clk_lock, clk_data);
636 
637 	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
638 			       clk_data);
639 
640 	clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
641 	clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
642 	clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
643 
644 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
645 }
646 
647 static int mtk_infrasys_init(struct platform_device *pdev)
648 {
649 	struct device_node *node = pdev->dev.of_node;
650 	struct clk_hw_onecell_data *clk_data;
651 	int r;
652 
653 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
654 
655 	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
656 			       clk_data);
657 
658 	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
659 				  clk_data);
660 
661 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
662 				   clk_data);
663 	if (r)
664 		return r;
665 
666 	mtk_register_reset_controller(node, 1, 0x30);
667 
668 	return 0;
669 }
670 
671 static int mtk_apmixedsys_init(struct platform_device *pdev)
672 {
673 	struct clk_hw_onecell_data *clk_data;
674 	struct device_node *node = pdev->dev.of_node;
675 
676 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
677 	if (!clk_data)
678 		return -ENOMEM;
679 
680 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
681 			      clk_data);
682 
683 	mtk_clk_register_gates(node, apmixed_clks,
684 			       ARRAY_SIZE(apmixed_clks), clk_data);
685 
686 	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
687 	clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
688 
689 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
690 }
691 
692 static int mtk_pericfg_init(struct platform_device *pdev)
693 {
694 	struct clk_hw_onecell_data *clk_data;
695 	void __iomem *base;
696 	int r;
697 	struct device_node *node = pdev->dev.of_node;
698 
699 	base = devm_platform_ioremap_resource(pdev, 0);
700 	if (IS_ERR(base))
701 		return PTR_ERR(base);
702 
703 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
704 
705 	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
706 			       clk_data);
707 
708 	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
709 				    &mt7622_clk_lock, clk_data);
710 
711 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
712 	if (r)
713 		return r;
714 
715 	clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
716 
717 	mtk_register_reset_controller(node, 2, 0x0);
718 
719 	return 0;
720 }
721 
722 static const struct of_device_id of_match_clk_mt7622[] = {
723 	{
724 		.compatible = "mediatek,mt7622-apmixedsys",
725 		.data = mtk_apmixedsys_init,
726 	}, {
727 		.compatible = "mediatek,mt7622-infracfg",
728 		.data = mtk_infrasys_init,
729 	}, {
730 		.compatible = "mediatek,mt7622-topckgen",
731 		.data = mtk_topckgen_init,
732 	}, {
733 		.compatible = "mediatek,mt7622-pericfg",
734 		.data = mtk_pericfg_init,
735 	}, {
736 		/* sentinel */
737 	}
738 };
739 
740 static int clk_mt7622_probe(struct platform_device *pdev)
741 {
742 	int (*clk_init)(struct platform_device *);
743 	int r;
744 
745 	clk_init = of_device_get_match_data(&pdev->dev);
746 	if (!clk_init)
747 		return -EINVAL;
748 
749 	r = clk_init(pdev);
750 	if (r)
751 		dev_err(&pdev->dev,
752 			"could not register clock provider: %s: %d\n",
753 			pdev->name, r);
754 
755 	return r;
756 }
757 
758 static struct platform_driver clk_mt7622_drv = {
759 	.probe = clk_mt7622_probe,
760 	.driver = {
761 		.name = "clk-mt7622",
762 		.of_match_table = of_match_clk_mt7622,
763 	},
764 };
765 
766 static int clk_mt7622_init(void)
767 {
768 	return platform_driver_register(&clk_mt7622_drv);
769 }
770 
771 arch_initcall(clk_mt7622_init);
772