1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Chen Zhong <chen.zhong@mediatek.com> 5 * Sean Wang <sean.wang@mediatek.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 14 #include "clk-cpumux.h" 15 #include "clk-gate.h" 16 #include "clk-mtk.h" 17 18 #include <dt-bindings/clock/mt7622-clk.h> 19 #include <linux/clk.h> /* for consumer */ 20 21 #define GATE_INFRA(_id, _name, _parent, _shift) \ 22 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 23 24 #define GATE_TOP0(_id, _name, _parent, _shift) \ 25 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 26 27 #define GATE_TOP1(_id, _name, _parent, _shift) \ 28 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 29 30 #define GATE_PERI0(_id, _name, _parent, _shift) \ 31 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 32 33 #define GATE_PERI0_AO(_id, _name, _parent, _shift) \ 34 GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \ 35 &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) 36 37 #define GATE_PERI1(_id, _name, _parent, _shift) \ 38 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 39 40 static DEFINE_SPINLOCK(mt7622_clk_lock); 41 42 static const char * const infra_mux1_parents[] = { 43 "clkxtal", 44 "armpll", 45 "main_core_en", 46 "armpll" 47 }; 48 49 static const char * const axi_parents[] = { 50 "clkxtal", 51 "syspll1_d2", 52 "syspll_d5", 53 "syspll1_d4", 54 "univpll_d5", 55 "univpll2_d2", 56 "univpll_d7" 57 }; 58 59 static const char * const mem_parents[] = { 60 "clkxtal", 61 "dmpll_ck" 62 }; 63 64 static const char * const ddrphycfg_parents[] = { 65 "clkxtal", 66 "syspll1_d8" 67 }; 68 69 static const char * const eth_parents[] = { 70 "clkxtal", 71 "syspll1_d2", 72 "univpll1_d2", 73 "syspll1_d4", 74 "univpll_d5", 75 "clk_null", 76 "univpll_d7" 77 }; 78 79 static const char * const pwm_parents[] = { 80 "clkxtal", 81 "univpll2_d4" 82 }; 83 84 static const char * const f10m_ref_parents[] = { 85 "clkxtal", 86 "syspll4_d16" 87 }; 88 89 static const char * const nfi_infra_parents[] = { 90 "clkxtal", 91 "clkxtal", 92 "clkxtal", 93 "clkxtal", 94 "clkxtal", 95 "clkxtal", 96 "clkxtal", 97 "clkxtal", 98 "univpll2_d8", 99 "syspll1_d8", 100 "univpll1_d8", 101 "syspll4_d2", 102 "univpll2_d4", 103 "univpll3_d2", 104 "syspll1_d4" 105 }; 106 107 static const char * const flash_parents[] = { 108 "clkxtal", 109 "univpll_d80_d4", 110 "syspll2_d8", 111 "syspll3_d4", 112 "univpll3_d4", 113 "univpll1_d8", 114 "syspll2_d4", 115 "univpll2_d4" 116 }; 117 118 static const char * const uart_parents[] = { 119 "clkxtal", 120 "univpll2_d8" 121 }; 122 123 static const char * const spi0_parents[] = { 124 "clkxtal", 125 "syspll3_d2", 126 "clkxtal", 127 "syspll2_d4", 128 "syspll4_d2", 129 "univpll2_d4", 130 "univpll1_d8", 131 "clkxtal" 132 }; 133 134 static const char * const spi1_parents[] = { 135 "clkxtal", 136 "syspll3_d2", 137 "clkxtal", 138 "syspll4_d4", 139 "syspll4_d2", 140 "univpll2_d4", 141 "univpll1_d8", 142 "clkxtal" 143 }; 144 145 static const char * const msdc30_0_parents[] = { 146 "clkxtal", 147 "univpll2_d16", 148 "univ48m" 149 }; 150 151 static const char * const a1sys_hp_parents[] = { 152 "clkxtal", 153 "aud1pll_ck", 154 "aud2pll_ck", 155 "clkxtal" 156 }; 157 158 static const char * const intdir_parents[] = { 159 "clkxtal", 160 "syspll_d2", 161 "univpll_d2", 162 "sgmiipll_ck" 163 }; 164 165 static const char * const aud_intbus_parents[] = { 166 "clkxtal", 167 "syspll1_d4", 168 "syspll4_d2", 169 "syspll3_d2" 170 }; 171 172 static const char * const pmicspi_parents[] = { 173 "clkxtal", 174 "clk_null", 175 "clk_null", 176 "clk_null", 177 "clk_null", 178 "univpll2_d16" 179 }; 180 181 static const char * const atb_parents[] = { 182 "clkxtal", 183 "syspll1_d2", 184 "syspll_d5" 185 }; 186 187 static const char * const audio_parents[] = { 188 "clkxtal", 189 "syspll3_d4", 190 "syspll4_d4", 191 "univpll1_d16" 192 }; 193 194 static const char * const usb20_parents[] = { 195 "clkxtal", 196 "univpll3_d4", 197 "syspll1_d8", 198 "clkxtal" 199 }; 200 201 static const char * const aud1_parents[] = { 202 "clkxtal", 203 "aud1pll_ck" 204 }; 205 206 static const char * const aud2_parents[] = { 207 "clkxtal", 208 "aud2pll_ck" 209 }; 210 211 static const char * const asm_l_parents[] = { 212 "clkxtal", 213 "syspll_d5", 214 "univpll2_d2", 215 "univpll2_d4" 216 }; 217 218 static const char * const apll1_ck_parents[] = { 219 "aud1_sel", 220 "aud2_sel" 221 }; 222 223 static const char * const peribus_ck_parents[] = { 224 "syspll1_d8", 225 "syspll1_d4" 226 }; 227 228 static const struct mtk_gate_regs infra_cg_regs = { 229 .set_ofs = 0x40, 230 .clr_ofs = 0x44, 231 .sta_ofs = 0x48, 232 }; 233 234 static const struct mtk_gate_regs top0_cg_regs = { 235 .set_ofs = 0x120, 236 .clr_ofs = 0x120, 237 .sta_ofs = 0x120, 238 }; 239 240 static const struct mtk_gate_regs top1_cg_regs = { 241 .set_ofs = 0x128, 242 .clr_ofs = 0x128, 243 .sta_ofs = 0x128, 244 }; 245 246 static const struct mtk_gate_regs peri0_cg_regs = { 247 .set_ofs = 0x8, 248 .clr_ofs = 0x10, 249 .sta_ofs = 0x18, 250 }; 251 252 static const struct mtk_gate_regs peri1_cg_regs = { 253 .set_ofs = 0xC, 254 .clr_ofs = 0x14, 255 .sta_ofs = 0x1C, 256 }; 257 258 static const struct mtk_gate infra_clks[] = { 259 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0), 260 GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2), 261 GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5), 262 GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16), 263 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18), 264 GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22), 265 }; 266 267 static const struct mtk_fixed_clk top_fixed_clks[] = { 268 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", 269 31250000), 270 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal", 271 31250000), 272 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal", 273 125000000), 274 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal", 275 125000000), 276 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal", 277 250000000), 278 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal", 279 250000000), 280 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal", 281 33333333), 282 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal", 283 50000000), 284 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal", 285 50000000), 286 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal", 287 50000000), 288 }; 289 290 static const struct mtk_fixed_factor top_divs[] = { 291 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4), 292 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500), 293 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125), 294 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500), 295 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1), 296 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024), 297 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1), 298 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 299 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 300 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 301 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 302 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 303 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 304 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 305 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 306 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 307 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 308 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 309 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 310 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112), 311 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), 312 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 313 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 314 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 315 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16), 316 FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32), 317 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 318 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 319 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 320 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48), 321 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 322 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 323 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 324 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80), 325 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 326 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320), 327 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25), 328 FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1), 329 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2), 330 FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1), 331 FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1), 332 FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2), 333 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4), 334 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1), 335 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1), 336 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1), 337 }; 338 339 static const struct mtk_gate top_clks[] = { 340 /* TOP0 */ 341 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0), 342 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1), 343 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div", 344 2), 345 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div", 346 3), 347 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div", 348 4), 349 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div", 350 5), 351 352 /* TOP1 */ 353 GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0), 354 GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16), 355 }; 356 357 static const struct mtk_clk_divider top_adj_divs[] = { 358 DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel", 359 0x120, 24, 3), 360 DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel", 361 0x120, 28, 3), 362 DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel", 363 0x124, 0, 7), 364 DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel", 365 0x124, 8, 7), 366 DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck", 367 0x124, 16, 7), 368 DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel", 369 0x124, 24, 7), 370 DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel", 371 0x128, 8, 7), 372 DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel", 373 0x128, 24, 7), 374 }; 375 376 static const struct mtk_gate peri_clks[] = { 377 /* PERI0 */ 378 GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1), 379 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2), 380 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3), 381 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4), 382 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5), 383 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6), 384 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7), 385 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8), 386 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9), 387 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12), 388 GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13), 389 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14), 390 GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), 391 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18), 392 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19), 393 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20), 394 GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21), 395 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22), 396 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23), 397 GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24), 398 GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25), 399 GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26), 400 GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27), 401 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28), 402 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29), 403 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30), 404 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31), 405 406 /* PERI1 */ 407 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1), 408 GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2), 409 }; 410 411 static struct mtk_composite infra_muxes[] = { 412 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 413 0x000, 2, 2), 414 }; 415 416 static struct mtk_composite top_muxes[] = { 417 /* CLK_CFG_0 */ 418 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 419 0x040, 0, 3, 7, CLK_IS_CRITICAL), 420 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 421 0x040, 8, 1, 15, CLK_IS_CRITICAL), 422 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 423 0x040, 16, 1, 23, CLK_IS_CRITICAL), 424 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 425 0x040, 24, 3, 31), 426 427 /* CLK_CFG_1 */ 428 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 429 0x050, 0, 2, 7), 430 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents, 431 0x050, 8, 1, 15), 432 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents, 433 0x050, 16, 4, 23), 434 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 435 0x050, 24, 3, 31), 436 437 /* CLK_CFG_2 */ 438 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 439 0x060, 0, 1, 7), 440 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents, 441 0x060, 8, 3, 15), 442 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents, 443 0x060, 16, 3, 23), 444 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents, 445 0x060, 24, 3, 31), 446 447 /* CLK_CFG_3 */ 448 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents, 449 0x070, 0, 3, 7), 450 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents, 451 0x070, 8, 3, 15), 452 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, 453 0x070, 16, 2, 23), 454 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents, 455 0x070, 24, 2, 31), 456 457 /* CLK_CFG_4 */ 458 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 459 0x080, 0, 2, 7), 460 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 461 0x080, 8, 2, 15), 462 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 463 0x080, 16, 3, 23), 464 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents, 465 0x080, 24, 2, 31), 466 467 /* CLK_CFG_5 */ 468 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 469 0x090, 0, 2, 7), 470 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents, 471 0x090, 8, 3, 15), 472 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 473 0x090, 16, 2, 23), 474 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents, 475 0x090, 24, 2, 31), 476 477 /* CLK_CFG_6 */ 478 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, 479 0x0A0, 0, 1, 7), 480 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents, 481 0x0A0, 8, 1, 15), 482 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents, 483 0x0A0, 16, 1, 23), 484 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents, 485 0x0A0, 24, 1, 31), 486 487 /* CLK_CFG_7 */ 488 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, 489 0x0B0, 0, 2, 7), 490 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, 491 0x0B0, 8, 2, 15), 492 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, 493 0x0B0, 16, 2, 23), 494 495 /* CLK_AUDDIV_0 */ 496 MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents, 497 0x120, 6, 1), 498 MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents, 499 0x120, 7, 1), 500 MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents, 501 0x120, 8, 1), 502 MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents, 503 0x120, 9, 1), 504 MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents, 505 0x120, 10, 1), 506 MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents, 507 0x120, 11, 1), 508 }; 509 510 static struct mtk_composite peri_muxes[] = { 511 /* PERI_GLOBALCON_CKSEL */ 512 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), 513 }; 514 515 static u16 infrasys_rst_ofs[] = { 0x30, }; 516 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 517 518 static const struct mtk_clk_rst_desc clk_rst_desc[] = { 519 /* infrasys */ 520 { 521 .version = MTK_RST_SIMPLE, 522 .rst_bank_ofs = infrasys_rst_ofs, 523 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 524 }, 525 /* pericfg */ 526 { 527 .version = MTK_RST_SIMPLE, 528 .rst_bank_ofs = pericfg_rst_ofs, 529 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 530 }, 531 }; 532 533 static int mtk_topckgen_init(struct platform_device *pdev) 534 { 535 struct clk_hw_onecell_data *clk_data; 536 void __iomem *base; 537 struct device_node *node = pdev->dev.of_node; 538 539 base = devm_platform_ioremap_resource(pdev, 0); 540 if (IS_ERR(base)) 541 return PTR_ERR(base); 542 543 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 544 545 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 546 clk_data); 547 548 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), 549 clk_data); 550 551 mtk_clk_register_composites(&pdev->dev, top_muxes, 552 ARRAY_SIZE(top_muxes), base, 553 &mt7622_clk_lock, clk_data); 554 555 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 556 base, &mt7622_clk_lock, clk_data); 557 558 mtk_clk_register_gates(&pdev->dev, node, top_clks, 559 ARRAY_SIZE(top_clks), clk_data); 560 561 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 562 } 563 564 static int mtk_infrasys_init(struct platform_device *pdev) 565 { 566 struct device_node *node = pdev->dev.of_node; 567 struct clk_hw_onecell_data *clk_data; 568 int r; 569 570 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 571 572 mtk_clk_register_gates(&pdev->dev, node, infra_clks, 573 ARRAY_SIZE(infra_clks), clk_data); 574 575 mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, 576 ARRAY_SIZE(infra_muxes), clk_data); 577 578 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 579 clk_data); 580 if (r) 581 return r; 582 583 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); 584 585 return 0; 586 } 587 588 589 static int mtk_pericfg_init(struct platform_device *pdev) 590 { 591 struct clk_hw_onecell_data *clk_data; 592 void __iomem *base; 593 int r; 594 struct device_node *node = pdev->dev.of_node; 595 596 base = devm_platform_ioremap_resource(pdev, 0); 597 if (IS_ERR(base)) 598 return PTR_ERR(base); 599 600 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 601 602 mtk_clk_register_gates(&pdev->dev, node, peri_clks, 603 ARRAY_SIZE(peri_clks), clk_data); 604 605 mtk_clk_register_composites(&pdev->dev, peri_muxes, 606 ARRAY_SIZE(peri_muxes), base, 607 &mt7622_clk_lock, clk_data); 608 609 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 610 if (r) 611 return r; 612 613 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); 614 615 return 0; 616 } 617 618 static const struct of_device_id of_match_clk_mt7622[] = { 619 { 620 .compatible = "mediatek,mt7622-infracfg", 621 .data = mtk_infrasys_init, 622 }, { 623 .compatible = "mediatek,mt7622-topckgen", 624 .data = mtk_topckgen_init, 625 }, { 626 .compatible = "mediatek,mt7622-pericfg", 627 .data = mtk_pericfg_init, 628 }, { 629 /* sentinel */ 630 } 631 }; 632 633 static int clk_mt7622_probe(struct platform_device *pdev) 634 { 635 int (*clk_init)(struct platform_device *); 636 int r; 637 638 clk_init = of_device_get_match_data(&pdev->dev); 639 if (!clk_init) 640 return -EINVAL; 641 642 r = clk_init(pdev); 643 if (r) 644 dev_err(&pdev->dev, 645 "could not register clock provider: %s: %d\n", 646 pdev->name, r); 647 648 return r; 649 } 650 651 static struct platform_driver clk_mt7622_drv = { 652 .probe = clk_mt7622_probe, 653 .driver = { 654 .name = "clk-mt7622", 655 .of_match_table = of_match_clk_mt7622, 656 }, 657 }; 658 659 static int clk_mt7622_init(void) 660 { 661 return platform_driver_register(&clk_mt7622_drv); 662 } 663 664 arch_initcall(clk_mt7622_init); 665