1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Chen Zhong <chen.zhong@mediatek.com> 5 * Sean Wang <sean.wang@mediatek.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 14 #include "clk-cpumux.h" 15 #include "clk-gate.h" 16 #include "clk-mtk.h" 17 18 #include <dt-bindings/clock/mt7622-clk.h> 19 #include <linux/clk.h> /* for consumer */ 20 21 #define GATE_TOP0(_id, _name, _parent, _shift) \ 22 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 23 24 #define GATE_TOP1(_id, _name, _parent, _shift) \ 25 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 26 27 #define GATE_PERI0(_id, _name, _parent, _shift) \ 28 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 29 30 #define GATE_PERI0_AO(_id, _name, _parent, _shift) \ 31 GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \ 32 &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) 33 34 #define GATE_PERI1(_id, _name, _parent, _shift) \ 35 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 36 37 static DEFINE_SPINLOCK(mt7622_clk_lock); 38 39 static const char * const axi_parents[] = { 40 "clkxtal", 41 "syspll1_d2", 42 "syspll_d5", 43 "syspll1_d4", 44 "univpll_d5", 45 "univpll2_d2", 46 "univpll_d7" 47 }; 48 49 static const char * const mem_parents[] = { 50 "clkxtal", 51 "dmpll_ck" 52 }; 53 54 static const char * const ddrphycfg_parents[] = { 55 "clkxtal", 56 "syspll1_d8" 57 }; 58 59 static const char * const eth_parents[] = { 60 "clkxtal", 61 "syspll1_d2", 62 "univpll1_d2", 63 "syspll1_d4", 64 "univpll_d5", 65 "clk_null", 66 "univpll_d7" 67 }; 68 69 static const char * const pwm_parents[] = { 70 "clkxtal", 71 "univpll2_d4" 72 }; 73 74 static const char * const f10m_ref_parents[] = { 75 "clkxtal", 76 "syspll4_d16" 77 }; 78 79 static const char * const nfi_infra_parents[] = { 80 "clkxtal", 81 "clkxtal", 82 "clkxtal", 83 "clkxtal", 84 "clkxtal", 85 "clkxtal", 86 "clkxtal", 87 "clkxtal", 88 "univpll2_d8", 89 "syspll1_d8", 90 "univpll1_d8", 91 "syspll4_d2", 92 "univpll2_d4", 93 "univpll3_d2", 94 "syspll1_d4" 95 }; 96 97 static const char * const flash_parents[] = { 98 "clkxtal", 99 "univpll_d80_d4", 100 "syspll2_d8", 101 "syspll3_d4", 102 "univpll3_d4", 103 "univpll1_d8", 104 "syspll2_d4", 105 "univpll2_d4" 106 }; 107 108 static const char * const uart_parents[] = { 109 "clkxtal", 110 "univpll2_d8" 111 }; 112 113 static const char * const spi0_parents[] = { 114 "clkxtal", 115 "syspll3_d2", 116 "clkxtal", 117 "syspll2_d4", 118 "syspll4_d2", 119 "univpll2_d4", 120 "univpll1_d8", 121 "clkxtal" 122 }; 123 124 static const char * const spi1_parents[] = { 125 "clkxtal", 126 "syspll3_d2", 127 "clkxtal", 128 "syspll4_d4", 129 "syspll4_d2", 130 "univpll2_d4", 131 "univpll1_d8", 132 "clkxtal" 133 }; 134 135 static const char * const msdc30_0_parents[] = { 136 "clkxtal", 137 "univpll2_d16", 138 "univ48m" 139 }; 140 141 static const char * const a1sys_hp_parents[] = { 142 "clkxtal", 143 "aud1pll_ck", 144 "aud2pll_ck", 145 "clkxtal" 146 }; 147 148 static const char * const intdir_parents[] = { 149 "clkxtal", 150 "syspll_d2", 151 "univpll_d2", 152 "sgmiipll_ck" 153 }; 154 155 static const char * const aud_intbus_parents[] = { 156 "clkxtal", 157 "syspll1_d4", 158 "syspll4_d2", 159 "syspll3_d2" 160 }; 161 162 static const char * const pmicspi_parents[] = { 163 "clkxtal", 164 "clk_null", 165 "clk_null", 166 "clk_null", 167 "clk_null", 168 "univpll2_d16" 169 }; 170 171 static const char * const atb_parents[] = { 172 "clkxtal", 173 "syspll1_d2", 174 "syspll_d5" 175 }; 176 177 static const char * const audio_parents[] = { 178 "clkxtal", 179 "syspll3_d4", 180 "syspll4_d4", 181 "univpll1_d16" 182 }; 183 184 static const char * const usb20_parents[] = { 185 "clkxtal", 186 "univpll3_d4", 187 "syspll1_d8", 188 "clkxtal" 189 }; 190 191 static const char * const aud1_parents[] = { 192 "clkxtal", 193 "aud1pll_ck" 194 }; 195 196 static const char * const aud2_parents[] = { 197 "clkxtal", 198 "aud2pll_ck" 199 }; 200 201 static const char * const asm_l_parents[] = { 202 "clkxtal", 203 "syspll_d5", 204 "univpll2_d2", 205 "univpll2_d4" 206 }; 207 208 static const char * const apll1_ck_parents[] = { 209 "aud1_sel", 210 "aud2_sel" 211 }; 212 213 static const char * const peribus_ck_parents[] = { 214 "syspll1_d8", 215 "syspll1_d4" 216 }; 217 218 static const struct mtk_gate_regs top0_cg_regs = { 219 .set_ofs = 0x120, 220 .clr_ofs = 0x120, 221 .sta_ofs = 0x120, 222 }; 223 224 static const struct mtk_gate_regs top1_cg_regs = { 225 .set_ofs = 0x128, 226 .clr_ofs = 0x128, 227 .sta_ofs = 0x128, 228 }; 229 230 static const struct mtk_gate_regs peri0_cg_regs = { 231 .set_ofs = 0x8, 232 .clr_ofs = 0x10, 233 .sta_ofs = 0x18, 234 }; 235 236 static const struct mtk_gate_regs peri1_cg_regs = { 237 .set_ofs = 0xC, 238 .clr_ofs = 0x14, 239 .sta_ofs = 0x1C, 240 }; 241 242 static const struct mtk_fixed_clk top_fixed_clks[] = { 243 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", 244 31250000), 245 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal", 246 31250000), 247 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal", 248 125000000), 249 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal", 250 125000000), 251 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal", 252 250000000), 253 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal", 254 250000000), 255 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal", 256 33333333), 257 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal", 258 50000000), 259 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal", 260 50000000), 261 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal", 262 50000000), 263 }; 264 265 static const struct mtk_fixed_factor top_divs[] = { 266 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4), 267 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500), 268 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125), 269 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500), 270 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1), 271 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024), 272 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1), 273 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 274 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 275 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 276 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 277 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 278 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 279 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 280 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 281 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 282 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 283 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 284 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 285 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112), 286 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), 287 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 288 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 289 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 290 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16), 291 FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32), 292 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 293 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 294 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 295 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48), 296 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 297 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 298 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 299 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80), 300 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 301 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320), 302 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25), 303 FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1), 304 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2), 305 FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1), 306 FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1), 307 FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2), 308 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4), 309 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1), 310 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1), 311 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1), 312 }; 313 314 static const struct mtk_gate top_clks[] = { 315 /* TOP0 */ 316 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0), 317 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1), 318 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div", 319 2), 320 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div", 321 3), 322 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div", 323 4), 324 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div", 325 5), 326 327 /* TOP1 */ 328 GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0), 329 GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16), 330 }; 331 332 static const struct mtk_clk_divider top_adj_divs[] = { 333 DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel", 334 0x120, 24, 3), 335 DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel", 336 0x120, 28, 3), 337 DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel", 338 0x124, 0, 7), 339 DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel", 340 0x124, 8, 7), 341 DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck", 342 0x124, 16, 7), 343 DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel", 344 0x124, 24, 7), 345 DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel", 346 0x128, 8, 7), 347 DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel", 348 0x128, 24, 7), 349 }; 350 351 static const struct mtk_gate peri_clks[] = { 352 /* PERI0 */ 353 GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1), 354 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2), 355 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3), 356 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4), 357 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5), 358 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6), 359 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7), 360 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8), 361 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9), 362 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12), 363 GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13), 364 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14), 365 GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), 366 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18), 367 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19), 368 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20), 369 GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21), 370 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22), 371 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23), 372 GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24), 373 GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25), 374 GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26), 375 GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27), 376 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28), 377 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29), 378 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30), 379 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31), 380 381 /* PERI1 */ 382 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1), 383 GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2), 384 }; 385 386 static struct mtk_composite top_muxes[] = { 387 /* CLK_CFG_0 */ 388 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 389 0x040, 0, 3, 7, CLK_IS_CRITICAL), 390 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 391 0x040, 8, 1, 15, CLK_IS_CRITICAL), 392 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 393 0x040, 16, 1, 23, CLK_IS_CRITICAL), 394 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 395 0x040, 24, 3, 31), 396 397 /* CLK_CFG_1 */ 398 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 399 0x050, 0, 2, 7), 400 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents, 401 0x050, 8, 1, 15), 402 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents, 403 0x050, 16, 4, 23), 404 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 405 0x050, 24, 3, 31), 406 407 /* CLK_CFG_2 */ 408 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 409 0x060, 0, 1, 7), 410 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents, 411 0x060, 8, 3, 15), 412 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents, 413 0x060, 16, 3, 23), 414 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents, 415 0x060, 24, 3, 31), 416 417 /* CLK_CFG_3 */ 418 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents, 419 0x070, 0, 3, 7), 420 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents, 421 0x070, 8, 3, 15), 422 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, 423 0x070, 16, 2, 23), 424 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents, 425 0x070, 24, 2, 31), 426 427 /* CLK_CFG_4 */ 428 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 429 0x080, 0, 2, 7), 430 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 431 0x080, 8, 2, 15), 432 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 433 0x080, 16, 3, 23), 434 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents, 435 0x080, 24, 2, 31), 436 437 /* CLK_CFG_5 */ 438 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 439 0x090, 0, 2, 7), 440 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents, 441 0x090, 8, 3, 15), 442 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 443 0x090, 16, 2, 23), 444 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents, 445 0x090, 24, 2, 31), 446 447 /* CLK_CFG_6 */ 448 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, 449 0x0A0, 0, 1, 7), 450 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents, 451 0x0A0, 8, 1, 15), 452 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents, 453 0x0A0, 16, 1, 23), 454 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents, 455 0x0A0, 24, 1, 31), 456 457 /* CLK_CFG_7 */ 458 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, 459 0x0B0, 0, 2, 7), 460 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, 461 0x0B0, 8, 2, 15), 462 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, 463 0x0B0, 16, 2, 23), 464 465 /* CLK_AUDDIV_0 */ 466 MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents, 467 0x120, 6, 1), 468 MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents, 469 0x120, 7, 1), 470 MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents, 471 0x120, 8, 1), 472 MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents, 473 0x120, 9, 1), 474 MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents, 475 0x120, 10, 1), 476 MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents, 477 0x120, 11, 1), 478 }; 479 480 static struct mtk_composite peri_muxes[] = { 481 /* PERI_GLOBALCON_CKSEL */ 482 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), 483 }; 484 485 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 486 487 static const struct mtk_clk_rst_desc clk_rst_desc = { 488 .version = MTK_RST_SIMPLE, 489 .rst_bank_ofs = pericfg_rst_ofs, 490 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 491 }; 492 493 static const struct mtk_clk_desc topck_desc = { 494 .clks = top_clks, 495 .num_clks = ARRAY_SIZE(top_clks), 496 .fixed_clks = top_fixed_clks, 497 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 498 .factor_clks = top_divs, 499 .num_factor_clks = ARRAY_SIZE(top_divs), 500 .composite_clks = top_muxes, 501 .num_composite_clks = ARRAY_SIZE(top_muxes), 502 .divider_clks = top_adj_divs, 503 .num_divider_clks = ARRAY_SIZE(top_adj_divs), 504 .clk_lock = &mt7622_clk_lock, 505 }; 506 507 static const struct mtk_clk_desc peri_desc = { 508 .clks = peri_clks, 509 .num_clks = ARRAY_SIZE(peri_clks), 510 .composite_clks = peri_muxes, 511 .num_composite_clks = ARRAY_SIZE(peri_muxes), 512 .rst_desc = &clk_rst_desc, 513 .clk_lock = &mt7622_clk_lock, 514 }; 515 516 static const struct of_device_id of_match_clk_mt7622[] = { 517 { .compatible = "mediatek,mt7622-topckgen", .data = &topck_desc }, 518 { .compatible = "mediatek,mt7622-pericfg", .data = &peri_desc }, 519 { /* sentinel */ } 520 }; 521 MODULE_DEVICE_TABLE(of, of_match_clk_mt7622); 522 523 static struct platform_driver clk_mt7622_drv = { 524 .driver = { 525 .name = "clk-mt7622", 526 .of_match_table = of_match_clk_mt7622, 527 }, 528 .probe = mtk_clk_simple_probe, 529 .remove_new = mtk_clk_simple_remove, 530 }; 531 module_platform_driver(clk_mt7622_drv) 532 533 MODULE_DESCRIPTION("MediaTek MT7622 clocks driver"); 534 MODULE_LICENSE("GPL"); 535