1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017 MediaTek Inc.
4  * Author: Chen Zhong <chen.zhong@mediatek.com>
5  *	   Sean Wang <sean.wang@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 
14 #include "clk-mtk.h"
15 #include "clk-gate.h"
16 #include "clk-cpumux.h"
17 
18 #include <dt-bindings/clock/mt7622-clk.h>
19 #include <linux/clk.h> /* for consumer */
20 
21 #define MT7622_PLL_FMAX		(2500UL * MHZ)
22 #define CON0_MT7622_RST_BAR	BIT(27)
23 
24 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
25 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
26 			_pcw_shift, _div_table, _parent_name) {		\
27 		.id = _id,						\
28 		.name = _name,						\
29 		.reg = _reg,						\
30 		.pwr_reg = _pwr_reg,					\
31 		.en_mask = _en_mask,					\
32 		.flags = _flags,					\
33 		.rst_bar_mask = CON0_MT7622_RST_BAR,			\
34 		.fmax = MT7622_PLL_FMAX,				\
35 		.pcwbits = _pcwbits,					\
36 		.pd_reg = _pd_reg,					\
37 		.pd_shift = _pd_shift,					\
38 		.tuner_reg = _tuner_reg,				\
39 		.pcw_reg = _pcw_reg,					\
40 		.pcw_shift = _pcw_shift,				\
41 		.div_table = _div_table,				\
42 		.parent_name = _parent_name,				\
43 	}
44 
45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
46 			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
47 			_pcw_shift)					\
48 	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
49 		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,  \
50 		 NULL, "clkxtal")
51 
52 #define GATE_APMIXED(_id, _name, _parent, _shift) {			\
53 		.id = _id,						\
54 		.name = _name,						\
55 		.parent_name = _parent,					\
56 		.regs = &apmixed_cg_regs,				\
57 		.shift = _shift,					\
58 		.ops = &mtk_clk_gate_ops_no_setclr_inv,			\
59 	}
60 
61 #define GATE_INFRA(_id, _name, _parent, _shift) {			\
62 		.id = _id,						\
63 		.name = _name,						\
64 		.parent_name = _parent,					\
65 		.regs = &infra_cg_regs,					\
66 		.shift = _shift,					\
67 		.ops = &mtk_clk_gate_ops_setclr,			\
68 	}
69 
70 #define GATE_TOP0(_id, _name, _parent, _shift) {			\
71 		.id = _id,						\
72 		.name = _name,						\
73 		.parent_name = _parent,					\
74 		.regs = &top0_cg_regs,					\
75 		.shift = _shift,					\
76 		.ops = &mtk_clk_gate_ops_no_setclr,			\
77 	}
78 
79 #define GATE_TOP1(_id, _name, _parent, _shift) {			\
80 		.id = _id,						\
81 		.name = _name,						\
82 		.parent_name = _parent,					\
83 		.regs = &top1_cg_regs,					\
84 		.shift = _shift,					\
85 		.ops = &mtk_clk_gate_ops_no_setclr,			\
86 	}
87 
88 #define GATE_PERI0(_id, _name, _parent, _shift) {			\
89 		.id = _id,						\
90 		.name = _name,						\
91 		.parent_name = _parent,					\
92 		.regs = &peri0_cg_regs,					\
93 		.shift = _shift,					\
94 		.ops = &mtk_clk_gate_ops_setclr,			\
95 	}
96 
97 #define GATE_PERI1(_id, _name, _parent, _shift) {			\
98 		.id = _id,						\
99 		.name = _name,						\
100 		.parent_name = _parent,					\
101 		.regs = &peri1_cg_regs,					\
102 		.shift = _shift,					\
103 		.ops = &mtk_clk_gate_ops_setclr,			\
104 	}
105 
106 static DEFINE_SPINLOCK(mt7622_clk_lock);
107 
108 static const char * const infra_mux1_parents[] = {
109 	"clkxtal",
110 	"armpll",
111 	"main_core_en",
112 	"armpll"
113 };
114 
115 static const char * const axi_parents[] = {
116 	"clkxtal",
117 	"syspll1_d2",
118 	"syspll_d5",
119 	"syspll1_d4",
120 	"univpll_d5",
121 	"univpll2_d2",
122 	"univpll_d7"
123 };
124 
125 static const char * const mem_parents[] = {
126 	"clkxtal",
127 	"dmpll_ck"
128 };
129 
130 static const char * const ddrphycfg_parents[] = {
131 	"clkxtal",
132 	"syspll1_d8"
133 };
134 
135 static const char * const eth_parents[] = {
136 	"clkxtal",
137 	"syspll1_d2",
138 	"univpll1_d2",
139 	"syspll1_d4",
140 	"univpll_d5",
141 	"clk_null",
142 	"univpll_d7"
143 };
144 
145 static const char * const pwm_parents[] = {
146 	"clkxtal",
147 	"univpll2_d4"
148 };
149 
150 static const char * const f10m_ref_parents[] = {
151 	"clkxtal",
152 	"syspll4_d16"
153 };
154 
155 static const char * const nfi_infra_parents[] = {
156 	"clkxtal",
157 	"clkxtal",
158 	"clkxtal",
159 	"clkxtal",
160 	"clkxtal",
161 	"clkxtal",
162 	"clkxtal",
163 	"clkxtal",
164 	"univpll2_d8",
165 	"syspll1_d8",
166 	"univpll1_d8",
167 	"syspll4_d2",
168 	"univpll2_d4",
169 	"univpll3_d2",
170 	"syspll1_d4"
171 };
172 
173 static const char * const flash_parents[] = {
174 	"clkxtal",
175 	"univpll_d80_d4",
176 	"syspll2_d8",
177 	"syspll3_d4",
178 	"univpll3_d4",
179 	"univpll1_d8",
180 	"syspll2_d4",
181 	"univpll2_d4"
182 };
183 
184 static const char * const uart_parents[] = {
185 	"clkxtal",
186 	"univpll2_d8"
187 };
188 
189 static const char * const spi0_parents[] = {
190 	"clkxtal",
191 	"syspll3_d2",
192 	"clkxtal",
193 	"syspll2_d4",
194 	"syspll4_d2",
195 	"univpll2_d4",
196 	"univpll1_d8",
197 	"clkxtal"
198 };
199 
200 static const char * const spi1_parents[] = {
201 	"clkxtal",
202 	"syspll3_d2",
203 	"clkxtal",
204 	"syspll4_d4",
205 	"syspll4_d2",
206 	"univpll2_d4",
207 	"univpll1_d8",
208 	"clkxtal"
209 };
210 
211 static const char * const msdc30_0_parents[] = {
212 	"clkxtal",
213 	"univpll2_d16",
214 	"univ48m"
215 };
216 
217 static const char * const a1sys_hp_parents[] = {
218 	"clkxtal",
219 	"aud1pll_ck",
220 	"aud2pll_ck",
221 	"clkxtal"
222 };
223 
224 static const char * const intdir_parents[] = {
225 	"clkxtal",
226 	"syspll_d2",
227 	"univpll_d2",
228 	"sgmiipll_ck"
229 };
230 
231 static const char * const aud_intbus_parents[] = {
232 	"clkxtal",
233 	"syspll1_d4",
234 	"syspll4_d2",
235 	"syspll3_d2"
236 };
237 
238 static const char * const pmicspi_parents[] = {
239 	"clkxtal",
240 	"clk_null",
241 	"clk_null",
242 	"clk_null",
243 	"clk_null",
244 	"univpll2_d16"
245 };
246 
247 static const char * const atb_parents[] = {
248 	"clkxtal",
249 	"syspll1_d2",
250 	"syspll_d5"
251 };
252 
253 static const char * const audio_parents[] = {
254 	"clkxtal",
255 	"syspll3_d4",
256 	"syspll4_d4",
257 	"univpll1_d16"
258 };
259 
260 static const char * const usb20_parents[] = {
261 	"clkxtal",
262 	"univpll3_d4",
263 	"syspll1_d8",
264 	"clkxtal"
265 };
266 
267 static const char * const aud1_parents[] = {
268 	"clkxtal",
269 	"aud1pll_ck"
270 };
271 
272 static const char * const aud2_parents[] = {
273 	"clkxtal",
274 	"aud2pll_ck"
275 };
276 
277 static const char * const asm_l_parents[] = {
278 	"clkxtal",
279 	"syspll_d5",
280 	"univpll2_d2",
281 	"univpll2_d4"
282 };
283 
284 static const char * const apll1_ck_parents[] = {
285 	"aud1_sel",
286 	"aud2_sel"
287 };
288 
289 static const char * const peribus_ck_parents[] = {
290 	"syspll1_d8",
291 	"syspll1_d4"
292 };
293 
294 static const struct mtk_gate_regs apmixed_cg_regs = {
295 	.set_ofs = 0x8,
296 	.clr_ofs = 0x8,
297 	.sta_ofs = 0x8,
298 };
299 
300 static const struct mtk_gate_regs infra_cg_regs = {
301 	.set_ofs = 0x40,
302 	.clr_ofs = 0x44,
303 	.sta_ofs = 0x48,
304 };
305 
306 static const struct mtk_gate_regs top0_cg_regs = {
307 	.set_ofs = 0x120,
308 	.clr_ofs = 0x120,
309 	.sta_ofs = 0x120,
310 };
311 
312 static const struct mtk_gate_regs top1_cg_regs = {
313 	.set_ofs = 0x128,
314 	.clr_ofs = 0x128,
315 	.sta_ofs = 0x128,
316 };
317 
318 static const struct mtk_gate_regs peri0_cg_regs = {
319 	.set_ofs = 0x8,
320 	.clr_ofs = 0x10,
321 	.sta_ofs = 0x18,
322 };
323 
324 static const struct mtk_gate_regs peri1_cg_regs = {
325 	.set_ofs = 0xC,
326 	.clr_ofs = 0x14,
327 	.sta_ofs = 0x1C,
328 };
329 
330 static const struct mtk_pll_data plls[] = {
331 	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
332 	    PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
333 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
334 	    HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
335 	PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
336 	    HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
337 	PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
338 	    0, 21, 0x0300, 1, 0, 0x0304, 0),
339 	PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
340 	    0, 21, 0x0314, 1, 0, 0x0318, 0),
341 	PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
342 	    0, 31, 0x0324, 1, 0, 0x0328, 0),
343 	PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
344 	    0, 31, 0x0334, 1, 0, 0x0338, 0),
345 	PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
346 	    0, 21, 0x0344, 1, 0, 0x0348, 0),
347 	PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
348 	    0, 21, 0x0358, 1, 0, 0x035C, 0),
349 };
350 
351 static const struct mtk_gate apmixed_clks[] = {
352 	GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
353 };
354 
355 static const struct mtk_gate infra_clks[] = {
356 	GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
357 	GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
358 	GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
359 	GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
360 	GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
361 	GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
362 };
363 
364 static const struct mtk_fixed_clk top_fixed_clks[] = {
365 	FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
366 		  31250000),
367 	FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
368 		  31250000),
369 	FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
370 		  125000000),
371 	FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
372 		  125000000),
373 	FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
374 		  250000000),
375 	FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
376 		  250000000),
377 	FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
378 		  33333333),
379 	FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
380 		  50000000),
381 	FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
382 		  50000000),
383 	FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
384 		  50000000),
385 };
386 
387 static const struct mtk_fixed_factor top_divs[] = {
388 	FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
389 	FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
390 	FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
391 	FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
392 	FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
393 	FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
394 	FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
395 	FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
396 	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
397 	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
398 	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
399 	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
400 	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
401 	FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
402 	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
403 	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
404 	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
405 	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
406 	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
407 	FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
408 	FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
409 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
410 	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
411 	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
412 	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
413 	FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
414 	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
415 	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
416 	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
417 	FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
418 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
419 	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
420 	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
421 	FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
422 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
423 	FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
424 	FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
425 	FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
426 	FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
427 	FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
428 	FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
429 	FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
430 	FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
431 	FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
432 	FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
433 	FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
434 };
435 
436 static const struct mtk_gate top_clks[] = {
437 	/* TOP0 */
438 	GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
439 	GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
440 	GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
441 		  2),
442 	GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
443 		  3),
444 	GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
445 		  4),
446 	GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
447 		  5),
448 
449 	/* TOP1 */
450 	GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
451 	GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
452 };
453 
454 static const struct mtk_clk_divider top_adj_divs[] = {
455 	DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
456 		0x120, 24, 3),
457 	DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
458 		0x120, 28, 3),
459 	DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
460 		0x124, 0, 7),
461 	DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
462 		0x124, 8, 7),
463 	DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
464 		0x124, 16, 7),
465 	DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
466 		0x124, 24, 7),
467 	DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
468 		0x128, 8, 7),
469 	DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
470 		0x128, 24, 7),
471 };
472 
473 static const struct mtk_gate peri_clks[] = {
474 	/* PERI0 */
475 	GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
476 	GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
477 	GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
478 	GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
479 	GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
480 	GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
481 	GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
482 	GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
483 	GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
484 	GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
485 	GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
486 	GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
487 	GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
488 	GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
489 	GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
490 	GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
491 	GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
492 	GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
493 	GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
494 	GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
495 	GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
496 	GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
497 	GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
498 	GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
499 	GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
500 	GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
501 	GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
502 
503 	/* PERI1 */
504 	GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
505 	GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
506 };
507 
508 static struct mtk_composite infra_muxes[] = {
509 	MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
510 	    0x000, 2, 2),
511 };
512 
513 static struct mtk_composite top_muxes[] = {
514 	/* CLK_CFG_0 */
515 	MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
516 		 0x040, 0, 3, 7),
517 	MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
518 		 0x040, 8, 1, 15),
519 	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
520 		 0x040, 16, 1, 23),
521 	MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
522 		 0x040, 24, 3, 31),
523 
524 	/* CLK_CFG_1 */
525 	MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
526 		 0x050, 0, 2, 7),
527 	MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
528 		 0x050, 8, 1, 15),
529 	MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
530 		 0x050, 16, 4, 23),
531 	MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
532 		 0x050, 24, 3, 31),
533 
534 	/* CLK_CFG_2 */
535 	MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
536 		 0x060, 0, 1, 7),
537 	MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
538 		 0x060, 8, 3, 15),
539 	MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
540 		 0x060, 16, 3, 23),
541 	MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
542 		 0x060, 24, 3, 31),
543 
544 	/* CLK_CFG_3 */
545 	MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
546 		 0x070, 0, 3, 7),
547 	MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
548 		 0x070, 8, 3, 15),
549 	MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
550 		 0x070, 16, 2, 23),
551 	MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
552 		 0x070, 24, 2, 31),
553 
554 	/* CLK_CFG_4 */
555 	MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
556 		 0x080, 0, 2, 7),
557 	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
558 		 0x080, 8, 2, 15),
559 	MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
560 		 0x080, 16, 3, 23),
561 	MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
562 		 0x080, 24, 2, 31),
563 
564 	/* CLK_CFG_5 */
565 	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
566 		 0x090, 0, 2, 7),
567 	MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
568 		 0x090, 8, 3, 15),
569 	MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
570 		 0x090, 16, 2, 23),
571 	MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
572 		 0x090, 24, 2, 31),
573 
574 	/* CLK_CFG_6 */
575 	MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
576 		 0x0A0, 0, 1, 7),
577 	MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
578 		 0x0A0, 8, 1, 15),
579 	MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
580 		 0x0A0, 16, 1, 23),
581 	MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
582 		 0x0A0, 24, 1, 31),
583 
584 	/* CLK_CFG_7 */
585 	MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
586 		 0x0B0, 0, 2, 7),
587 	MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
588 		 0x0B0, 8, 2, 15),
589 	MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
590 		 0x0B0, 16, 2, 23),
591 
592 	/* CLK_AUDDIV_0 */
593 	MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
594 	    0x120, 6, 1),
595 	MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
596 	    0x120, 7, 1),
597 	MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
598 	    0x120, 8, 1),
599 	MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
600 	    0x120, 9, 1),
601 	MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
602 	    0x120, 10, 1),
603 	MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
604 	    0x120, 11, 1),
605 };
606 
607 static struct mtk_composite peri_muxes[] = {
608 	/* PERI_GLOBALCON_CKSEL */
609 	MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
610 };
611 
612 static int mtk_topckgen_init(struct platform_device *pdev)
613 {
614 	struct clk_onecell_data *clk_data;
615 	void __iomem *base;
616 	struct device_node *node = pdev->dev.of_node;
617 
618 	base = devm_platform_ioremap_resource(pdev, 0);
619 	if (IS_ERR(base))
620 		return PTR_ERR(base);
621 
622 	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
623 
624 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
625 				    clk_data);
626 
627 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
628 				 clk_data);
629 
630 	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
631 				    base, &mt7622_clk_lock, clk_data);
632 
633 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
634 				  base, &mt7622_clk_lock, clk_data);
635 
636 	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
637 			       clk_data);
638 
639 	clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
640 	clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
641 	clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
642 
643 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
644 }
645 
646 static int mtk_infrasys_init(struct platform_device *pdev)
647 {
648 	struct device_node *node = pdev->dev.of_node;
649 	struct clk_onecell_data *clk_data;
650 	int r;
651 
652 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
653 
654 	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
655 			       clk_data);
656 
657 	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
658 				  clk_data);
659 
660 	r = of_clk_add_provider(node, of_clk_src_onecell_get,
661 				clk_data);
662 	if (r)
663 		return r;
664 
665 	mtk_register_reset_controller(node, 1, 0x30);
666 
667 	return 0;
668 }
669 
670 static int mtk_apmixedsys_init(struct platform_device *pdev)
671 {
672 	struct clk_onecell_data *clk_data;
673 	struct device_node *node = pdev->dev.of_node;
674 
675 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
676 	if (!clk_data)
677 		return -ENOMEM;
678 
679 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
680 			      clk_data);
681 
682 	mtk_clk_register_gates(node, apmixed_clks,
683 			       ARRAY_SIZE(apmixed_clks), clk_data);
684 
685 	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
686 	clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
687 
688 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
689 }
690 
691 static int mtk_pericfg_init(struct platform_device *pdev)
692 {
693 	struct clk_onecell_data *clk_data;
694 	void __iomem *base;
695 	int r;
696 	struct device_node *node = pdev->dev.of_node;
697 
698 	base = devm_platform_ioremap_resource(pdev, 0);
699 	if (IS_ERR(base))
700 		return PTR_ERR(base);
701 
702 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
703 
704 	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
705 			       clk_data);
706 
707 	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
708 				    &mt7622_clk_lock, clk_data);
709 
710 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
711 	if (r)
712 		return r;
713 
714 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
715 
716 	mtk_register_reset_controller(node, 2, 0x0);
717 
718 	return 0;
719 }
720 
721 static const struct of_device_id of_match_clk_mt7622[] = {
722 	{
723 		.compatible = "mediatek,mt7622-apmixedsys",
724 		.data = mtk_apmixedsys_init,
725 	}, {
726 		.compatible = "mediatek,mt7622-infracfg",
727 		.data = mtk_infrasys_init,
728 	}, {
729 		.compatible = "mediatek,mt7622-topckgen",
730 		.data = mtk_topckgen_init,
731 	}, {
732 		.compatible = "mediatek,mt7622-pericfg",
733 		.data = mtk_pericfg_init,
734 	}, {
735 		/* sentinel */
736 	}
737 };
738 
739 static int clk_mt7622_probe(struct platform_device *pdev)
740 {
741 	int (*clk_init)(struct platform_device *);
742 	int r;
743 
744 	clk_init = of_device_get_match_data(&pdev->dev);
745 	if (!clk_init)
746 		return -EINVAL;
747 
748 	r = clk_init(pdev);
749 	if (r)
750 		dev_err(&pdev->dev,
751 			"could not register clock provider: %s: %d\n",
752 			pdev->name, r);
753 
754 	return r;
755 }
756 
757 static struct platform_driver clk_mt7622_drv = {
758 	.probe = clk_mt7622_probe,
759 	.driver = {
760 		.name = "clk-mt7622",
761 		.of_match_table = of_match_clk_mt7622,
762 	},
763 };
764 
765 static int clk_mt7622_init(void)
766 {
767 	return platform_driver_register(&clk_mt7622_drv);
768 }
769 
770 arch_initcall(clk_mt7622_init);
771