1 /* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Chen Zhong <chen.zhong@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 22 #include "clk-mtk.h" 23 #include "clk-gate.h" 24 #include "clk-cpumux.h" 25 26 #include <dt-bindings/clock/mt7622-clk.h> 27 #include <linux/clk.h> /* for consumer */ 28 29 #define MT7622_PLL_FMAX (2500UL * MHZ) 30 #define CON0_MT7622_RST_BAR BIT(27) 31 32 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ 33 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 34 _pcw_shift, _div_table, _parent_name) { \ 35 .id = _id, \ 36 .name = _name, \ 37 .reg = _reg, \ 38 .pwr_reg = _pwr_reg, \ 39 .en_mask = _en_mask, \ 40 .flags = _flags, \ 41 .rst_bar_mask = CON0_MT7622_RST_BAR, \ 42 .fmax = MT7622_PLL_FMAX, \ 43 .pcwbits = _pcwbits, \ 44 .pd_reg = _pd_reg, \ 45 .pd_shift = _pd_shift, \ 46 .tuner_reg = _tuner_reg, \ 47 .pcw_reg = _pcw_reg, \ 48 .pcw_shift = _pcw_shift, \ 49 .div_table = _div_table, \ 50 .parent_name = _parent_name, \ 51 } 52 53 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 54 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ 55 _pcw_shift) \ 56 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ 57 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ 58 NULL, "clkxtal") 59 60 #define GATE_APMIXED(_id, _name, _parent, _shift) { \ 61 .id = _id, \ 62 .name = _name, \ 63 .parent_name = _parent, \ 64 .regs = &apmixed_cg_regs, \ 65 .shift = _shift, \ 66 .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 67 } 68 69 #define GATE_INFRA(_id, _name, _parent, _shift) { \ 70 .id = _id, \ 71 .name = _name, \ 72 .parent_name = _parent, \ 73 .regs = &infra_cg_regs, \ 74 .shift = _shift, \ 75 .ops = &mtk_clk_gate_ops_setclr, \ 76 } 77 78 #define GATE_TOP0(_id, _name, _parent, _shift) { \ 79 .id = _id, \ 80 .name = _name, \ 81 .parent_name = _parent, \ 82 .regs = &top0_cg_regs, \ 83 .shift = _shift, \ 84 .ops = &mtk_clk_gate_ops_no_setclr, \ 85 } 86 87 #define GATE_TOP1(_id, _name, _parent, _shift) { \ 88 .id = _id, \ 89 .name = _name, \ 90 .parent_name = _parent, \ 91 .regs = &top1_cg_regs, \ 92 .shift = _shift, \ 93 .ops = &mtk_clk_gate_ops_no_setclr, \ 94 } 95 96 #define GATE_PERI0(_id, _name, _parent, _shift) { \ 97 .id = _id, \ 98 .name = _name, \ 99 .parent_name = _parent, \ 100 .regs = &peri0_cg_regs, \ 101 .shift = _shift, \ 102 .ops = &mtk_clk_gate_ops_setclr, \ 103 } 104 105 #define GATE_PERI1(_id, _name, _parent, _shift) { \ 106 .id = _id, \ 107 .name = _name, \ 108 .parent_name = _parent, \ 109 .regs = &peri1_cg_regs, \ 110 .shift = _shift, \ 111 .ops = &mtk_clk_gate_ops_setclr, \ 112 } 113 114 static DEFINE_SPINLOCK(mt7622_clk_lock); 115 116 static const char * const infra_mux1_parents[] = { 117 "clkxtal", 118 "armpll", 119 "main_core_en", 120 "armpll" 121 }; 122 123 static const char * const axi_parents[] = { 124 "clkxtal", 125 "syspll1_d2", 126 "syspll_d5", 127 "syspll1_d4", 128 "univpll_d5", 129 "univpll2_d2", 130 "univpll_d7" 131 }; 132 133 static const char * const mem_parents[] = { 134 "clkxtal", 135 "dmpll_ck" 136 }; 137 138 static const char * const ddrphycfg_parents[] = { 139 "clkxtal", 140 "syspll1_d8" 141 }; 142 143 static const char * const eth_parents[] = { 144 "clkxtal", 145 "syspll1_d2", 146 "univpll1_d2", 147 "syspll1_d4", 148 "univpll_d5", 149 "clk_null", 150 "univpll_d7" 151 }; 152 153 static const char * const pwm_parents[] = { 154 "clkxtal", 155 "univpll2_d4" 156 }; 157 158 static const char * const f10m_ref_parents[] = { 159 "clkxtal", 160 "syspll4_d16" 161 }; 162 163 static const char * const nfi_infra_parents[] = { 164 "clkxtal", 165 "clkxtal", 166 "clkxtal", 167 "clkxtal", 168 "clkxtal", 169 "clkxtal", 170 "clkxtal", 171 "clkxtal", 172 "univpll2_d8", 173 "syspll1_d8", 174 "univpll1_d8", 175 "syspll4_d2", 176 "univpll2_d4", 177 "univpll3_d2", 178 "syspll1_d4" 179 }; 180 181 static const char * const flash_parents[] = { 182 "clkxtal", 183 "univpll_d80_d4", 184 "syspll2_d8", 185 "syspll3_d4", 186 "univpll3_d4", 187 "univpll1_d8", 188 "syspll2_d4", 189 "univpll2_d4" 190 }; 191 192 static const char * const uart_parents[] = { 193 "clkxtal", 194 "univpll2_d8" 195 }; 196 197 static const char * const spi0_parents[] = { 198 "clkxtal", 199 "syspll3_d2", 200 "clkxtal", 201 "syspll2_d4", 202 "syspll4_d2", 203 "univpll2_d4", 204 "univpll1_d8", 205 "clkxtal" 206 }; 207 208 static const char * const spi1_parents[] = { 209 "clkxtal", 210 "syspll3_d2", 211 "clkxtal", 212 "syspll4_d4", 213 "syspll4_d2", 214 "univpll2_d4", 215 "univpll1_d8", 216 "clkxtal" 217 }; 218 219 static const char * const msdc30_0_parents[] = { 220 "clkxtal", 221 "univpll2_d16", 222 "univ48m" 223 }; 224 225 static const char * const a1sys_hp_parents[] = { 226 "clkxtal", 227 "aud1pll_ck", 228 "aud2pll_ck", 229 "clkxtal" 230 }; 231 232 static const char * const intdir_parents[] = { 233 "clkxtal", 234 "syspll_d2", 235 "univpll_d2", 236 "sgmiipll_ck" 237 }; 238 239 static const char * const aud_intbus_parents[] = { 240 "clkxtal", 241 "syspll1_d4", 242 "syspll4_d2", 243 "syspll3_d2" 244 }; 245 246 static const char * const pmicspi_parents[] = { 247 "clkxtal", 248 "clk_null", 249 "clk_null", 250 "clk_null", 251 "clk_null", 252 "univpll2_d16" 253 }; 254 255 static const char * const atb_parents[] = { 256 "clkxtal", 257 "syspll1_d2", 258 "syspll_d5" 259 }; 260 261 static const char * const audio_parents[] = { 262 "clkxtal", 263 "syspll3_d4", 264 "syspll4_d4", 265 "univpll1_d16" 266 }; 267 268 static const char * const usb20_parents[] = { 269 "clkxtal", 270 "univpll3_d4", 271 "syspll1_d8", 272 "clkxtal" 273 }; 274 275 static const char * const aud1_parents[] = { 276 "clkxtal", 277 "aud1pll_ck" 278 }; 279 280 static const char * const aud2_parents[] = { 281 "clkxtal", 282 "aud2pll_ck" 283 }; 284 285 static const char * const asm_l_parents[] = { 286 "clkxtal", 287 "syspll_d5", 288 "univpll2_d2", 289 "univpll2_d4" 290 }; 291 292 static const char * const apll1_ck_parents[] = { 293 "aud1_sel", 294 "aud2_sel" 295 }; 296 297 static const char * const peribus_ck_parents[] = { 298 "syspll1_d8", 299 "syspll1_d4" 300 }; 301 302 static const struct mtk_gate_regs apmixed_cg_regs = { 303 .set_ofs = 0x8, 304 .clr_ofs = 0x8, 305 .sta_ofs = 0x8, 306 }; 307 308 static const struct mtk_gate_regs infra_cg_regs = { 309 .set_ofs = 0x40, 310 .clr_ofs = 0x44, 311 .sta_ofs = 0x48, 312 }; 313 314 static const struct mtk_gate_regs top0_cg_regs = { 315 .set_ofs = 0x120, 316 .clr_ofs = 0x120, 317 .sta_ofs = 0x120, 318 }; 319 320 static const struct mtk_gate_regs top1_cg_regs = { 321 .set_ofs = 0x128, 322 .clr_ofs = 0x128, 323 .sta_ofs = 0x128, 324 }; 325 326 static const struct mtk_gate_regs peri0_cg_regs = { 327 .set_ofs = 0x8, 328 .clr_ofs = 0x10, 329 .sta_ofs = 0x18, 330 }; 331 332 static const struct mtk_gate_regs peri1_cg_regs = { 333 .set_ofs = 0xC, 334 .clr_ofs = 0x14, 335 .sta_ofs = 0x1C, 336 }; 337 338 static const struct mtk_pll_data plls[] = { 339 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 340 PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), 341 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001, 342 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), 343 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001, 344 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), 345 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001, 346 0, 21, 0x0300, 1, 0, 0x0304, 0), 347 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001, 348 0, 21, 0x0314, 1, 0, 0x0318, 0), 349 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001, 350 0, 31, 0x0324, 1, 0, 0x0328, 0), 351 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001, 352 0, 31, 0x0334, 1, 0, 0x0338, 0), 353 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001, 354 0, 21, 0x0344, 1, 0, 0x0348, 0), 355 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001, 356 0, 21, 0x0358, 1, 0, 0x035C, 0), 357 }; 358 359 static const struct mtk_gate apmixed_clks[] = { 360 GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), 361 }; 362 363 static const struct mtk_gate infra_clks[] = { 364 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0), 365 GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2), 366 GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5), 367 GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16), 368 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18), 369 GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22), 370 }; 371 372 static const struct mtk_fixed_clk top_fixed_clks[] = { 373 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", 374 31250000), 375 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal", 376 31250000), 377 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal", 378 125000000), 379 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal", 380 125000000), 381 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal", 382 250000000), 383 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal", 384 250000000), 385 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal", 386 33333333), 387 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal", 388 50000000), 389 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal", 390 50000000), 391 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal", 392 50000000), 393 }; 394 395 static const struct mtk_fixed_factor top_divs[] = { 396 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4), 397 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500), 398 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125), 399 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500), 400 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1), 401 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024), 402 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1), 403 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), 404 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 405 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 406 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 407 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 408 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 409 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 410 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 411 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 412 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 413 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 414 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 415 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112), 416 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), 417 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 418 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 419 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 420 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16), 421 FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32), 422 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 423 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 424 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 425 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48), 426 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 427 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 428 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 429 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80), 430 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 431 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320), 432 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25), 433 FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1), 434 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2), 435 FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1), 436 FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1), 437 FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2), 438 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4), 439 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1), 440 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1), 441 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1), 442 }; 443 444 static const struct mtk_gate top_clks[] = { 445 /* TOP0 */ 446 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0), 447 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1), 448 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div", 449 2), 450 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div", 451 3), 452 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div", 453 4), 454 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div", 455 5), 456 457 /* TOP1 */ 458 GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0), 459 GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16), 460 }; 461 462 static const struct mtk_clk_divider top_adj_divs[] = { 463 DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel", 464 0x120, 24, 3), 465 DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel", 466 0x120, 28, 3), 467 DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel", 468 0x124, 0, 7), 469 DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel", 470 0x124, 8, 7), 471 DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck", 472 0x124, 16, 7), 473 DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel", 474 0x124, 24, 7), 475 DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel", 476 0x128, 8, 7), 477 DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel", 478 0x128, 24, 7), 479 }; 480 481 static const struct mtk_gate peri_clks[] = { 482 /* PERI0 */ 483 GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1), 484 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2), 485 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3), 486 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4), 487 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5), 488 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6), 489 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7), 490 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8), 491 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9), 492 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12), 493 GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13), 494 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14), 495 GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), 496 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18), 497 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19), 498 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20), 499 GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21), 500 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22), 501 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23), 502 GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24), 503 GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25), 504 GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26), 505 GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27), 506 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28), 507 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29), 508 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30), 509 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31), 510 511 /* PERI1 */ 512 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1), 513 GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2), 514 }; 515 516 static struct mtk_composite infra_muxes[] = { 517 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 518 0x000, 2, 2), 519 }; 520 521 static struct mtk_composite top_muxes[] = { 522 /* CLK_CFG_0 */ 523 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 524 0x040, 0, 3, 7), 525 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 526 0x040, 8, 1, 15), 527 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 528 0x040, 16, 1, 23), 529 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 530 0x040, 24, 3, 31), 531 532 /* CLK_CFG_1 */ 533 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 534 0x050, 0, 2, 7), 535 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents, 536 0x050, 8, 1, 15), 537 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents, 538 0x050, 16, 4, 23), 539 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 540 0x050, 24, 3, 31), 541 542 /* CLK_CFG_2 */ 543 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 544 0x060, 0, 1, 7), 545 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents, 546 0x060, 8, 3, 15), 547 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents, 548 0x060, 16, 3, 23), 549 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents, 550 0x060, 24, 3, 31), 551 552 /* CLK_CFG_3 */ 553 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents, 554 0x070, 0, 3, 7), 555 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents, 556 0x070, 8, 3, 15), 557 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, 558 0x070, 16, 2, 23), 559 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents, 560 0x070, 24, 2, 31), 561 562 /* CLK_CFG_4 */ 563 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 564 0x080, 0, 2, 7), 565 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 566 0x080, 8, 2, 15), 567 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 568 0x080, 16, 3, 23), 569 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents, 570 0x080, 24, 2, 31), 571 572 /* CLK_CFG_5 */ 573 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 574 0x090, 0, 2, 7), 575 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents, 576 0x090, 8, 3, 15), 577 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 578 0x090, 16, 2, 23), 579 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents, 580 0x090, 24, 2, 31), 581 582 /* CLK_CFG_6 */ 583 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, 584 0x0A0, 0, 1, 7), 585 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents, 586 0x0A0, 8, 1, 15), 587 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents, 588 0x0A0, 16, 1, 23), 589 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents, 590 0x0A0, 24, 1, 31), 591 592 /* CLK_CFG_7 */ 593 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, 594 0x0B0, 0, 2, 7), 595 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, 596 0x0B0, 8, 2, 15), 597 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, 598 0x0B0, 16, 2, 23), 599 600 /* CLK_AUDDIV_0 */ 601 MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents, 602 0x120, 6, 1), 603 MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents, 604 0x120, 7, 1), 605 MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents, 606 0x120, 8, 1), 607 MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents, 608 0x120, 9, 1), 609 MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents, 610 0x120, 10, 1), 611 MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents, 612 0x120, 11, 1), 613 }; 614 615 static struct mtk_composite peri_muxes[] = { 616 /* PERI_GLOBALCON_CKSEL */ 617 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), 618 }; 619 620 static int mtk_topckgen_init(struct platform_device *pdev) 621 { 622 struct clk_onecell_data *clk_data; 623 void __iomem *base; 624 struct device_node *node = pdev->dev.of_node; 625 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 626 627 base = devm_ioremap_resource(&pdev->dev, res); 628 if (IS_ERR(base)) 629 return PTR_ERR(base); 630 631 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 632 633 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 634 clk_data); 635 636 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), 637 clk_data); 638 639 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), 640 base, &mt7622_clk_lock, clk_data); 641 642 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 643 base, &mt7622_clk_lock, clk_data); 644 645 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), 646 clk_data); 647 648 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); 649 clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); 650 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); 651 652 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 653 } 654 655 static int mtk_infrasys_init(struct platform_device *pdev) 656 { 657 struct device_node *node = pdev->dev.of_node; 658 struct clk_onecell_data *clk_data; 659 int r; 660 661 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 662 663 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 664 clk_data); 665 666 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), 667 clk_data); 668 669 r = of_clk_add_provider(node, of_clk_src_onecell_get, 670 clk_data); 671 if (r) 672 return r; 673 674 mtk_register_reset_controller(node, 1, 0x30); 675 676 return 0; 677 } 678 679 static int mtk_apmixedsys_init(struct platform_device *pdev) 680 { 681 struct clk_onecell_data *clk_data; 682 struct device_node *node = pdev->dev.of_node; 683 684 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 685 if (!clk_data) 686 return -ENOMEM; 687 688 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), 689 clk_data); 690 691 mtk_clk_register_gates(node, apmixed_clks, 692 ARRAY_SIZE(apmixed_clks), clk_data); 693 694 clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); 695 clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]); 696 697 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 698 } 699 700 static int mtk_pericfg_init(struct platform_device *pdev) 701 { 702 struct clk_onecell_data *clk_data; 703 void __iomem *base; 704 int r; 705 struct device_node *node = pdev->dev.of_node; 706 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 707 708 base = devm_ioremap_resource(&pdev->dev, res); 709 if (IS_ERR(base)) 710 return PTR_ERR(base); 711 712 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 713 714 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), 715 clk_data); 716 717 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, 718 &mt7622_clk_lock, clk_data); 719 720 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 721 if (r) 722 return r; 723 724 clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); 725 726 mtk_register_reset_controller(node, 2, 0x0); 727 728 return 0; 729 } 730 731 static const struct of_device_id of_match_clk_mt7622[] = { 732 { 733 .compatible = "mediatek,mt7622-apmixedsys", 734 .data = mtk_apmixedsys_init, 735 }, { 736 .compatible = "mediatek,mt7622-infracfg", 737 .data = mtk_infrasys_init, 738 }, { 739 .compatible = "mediatek,mt7622-topckgen", 740 .data = mtk_topckgen_init, 741 }, { 742 .compatible = "mediatek,mt7622-pericfg", 743 .data = mtk_pericfg_init, 744 }, { 745 /* sentinel */ 746 } 747 }; 748 749 static int clk_mt7622_probe(struct platform_device *pdev) 750 { 751 int (*clk_init)(struct platform_device *); 752 int r; 753 754 clk_init = of_device_get_match_data(&pdev->dev); 755 if (!clk_init) 756 return -EINVAL; 757 758 r = clk_init(pdev); 759 if (r) 760 dev_err(&pdev->dev, 761 "could not register clock provider: %s: %d\n", 762 pdev->name, r); 763 764 return r; 765 } 766 767 static struct platform_driver clk_mt7622_drv = { 768 .probe = clk_mt7622_probe, 769 .driver = { 770 .name = "clk-mt7622", 771 .of_match_table = of_match_clk_mt7622, 772 }, 773 }; 774 775 static int clk_mt7622_init(void) 776 { 777 return platform_driver_register(&clk_mt7622_drv); 778 } 779 780 arch_initcall(clk_mt7622_init); 781