1 /*
2  * Copyright (c) 2017 MediaTek Inc.
3  * Author: Chen Zhong <chen.zhong@mediatek.com>
4  *	   Sean Wang <sean.wang@mediatek.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/clk-provider.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 
22 #include "clk-mtk.h"
23 #include "clk-gate.h"
24 
25 #include <dt-bindings/clock/mt7622-clk.h>
26 
27 #define GATE_ETH(_id, _name, _parent, _shift) {	\
28 		.id = _id,				\
29 		.name = _name,				\
30 		.parent_name = _parent,			\
31 		.regs = &eth_cg_regs,			\
32 		.shift = _shift,			\
33 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
34 	}
35 
36 static const struct mtk_gate_regs eth_cg_regs = {
37 	.set_ofs = 0x30,
38 	.clr_ofs = 0x30,
39 	.sta_ofs = 0x30,
40 };
41 
42 static const struct mtk_gate eth_clks[] = {
43 	GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
44 	GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
45 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
46 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
47 	GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
48 };
49 
50 static const struct mtk_gate_regs sgmii_cg_regs = {
51 	.set_ofs = 0xE4,
52 	.clr_ofs = 0xE4,
53 	.sta_ofs = 0xE4,
54 };
55 
56 #define GATE_SGMII(_id, _name, _parent, _shift) {	\
57 		.id = _id,				\
58 		.name = _name,				\
59 		.parent_name = _parent,			\
60 		.regs = &sgmii_cg_regs,			\
61 		.shift = _shift,			\
62 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
63 	}
64 
65 static const struct mtk_gate sgmii_clks[] = {
66 	GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
67 		   "ssusb_tx250m", 2),
68 	GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
69 		   "ssusb_eq_rx250m", 3),
70 	GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
71 		   "ssusb_cdr_ref", 4),
72 	GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
73 		   "ssusb_cdr_fb", 5),
74 };
75 
76 static int clk_mt7622_ethsys_init(struct platform_device *pdev)
77 {
78 	struct clk_onecell_data *clk_data;
79 	struct device_node *node = pdev->dev.of_node;
80 	int r;
81 
82 	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
83 
84 	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
85 			       clk_data);
86 
87 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
88 	if (r)
89 		dev_err(&pdev->dev,
90 			"could not register clock provider: %s: %d\n",
91 			pdev->name, r);
92 
93 	mtk_register_reset_controller(node, 1, 0x34);
94 
95 	return r;
96 }
97 
98 static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
99 {
100 	struct clk_onecell_data *clk_data;
101 	struct device_node *node = pdev->dev.of_node;
102 	int r;
103 
104 	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
105 
106 	mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
107 			       clk_data);
108 
109 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
110 	if (r)
111 		dev_err(&pdev->dev,
112 			"could not register clock provider: %s: %d\n",
113 			pdev->name, r);
114 
115 	return r;
116 }
117 
118 static const struct of_device_id of_match_clk_mt7622_eth[] = {
119 	{
120 		.compatible = "mediatek,mt7622-ethsys",
121 		.data = clk_mt7622_ethsys_init,
122 	}, {
123 		.compatible = "mediatek,mt7622-sgmiisys",
124 		.data = clk_mt7622_sgmiisys_init,
125 	}, {
126 		/* sentinel */
127 	}
128 };
129 
130 static int clk_mt7622_eth_probe(struct platform_device *pdev)
131 {
132 	int (*clk_init)(struct platform_device *);
133 	int r;
134 
135 	clk_init = of_device_get_match_data(&pdev->dev);
136 	if (!clk_init)
137 		return -EINVAL;
138 
139 	r = clk_init(pdev);
140 	if (r)
141 		dev_err(&pdev->dev,
142 			"could not register clock provider: %s: %d\n",
143 			pdev->name, r);
144 
145 	return r;
146 }
147 
148 static struct platform_driver clk_mt7622_eth_drv = {
149 	.probe = clk_mt7622_eth_probe,
150 	.driver = {
151 		.name = "clk-mt7622-eth",
152 		.of_match_table = of_match_clk_mt7622_eth,
153 	},
154 };
155 
156 builtin_platform_driver(clk_mt7622_eth_drv);
157