1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017 MediaTek Inc.
4  * Author: Chen Zhong <chen.zhong@mediatek.com>
5  *	   Sean Wang <sean.wang@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 
14 #include "clk-mtk.h"
15 #include "clk-gate.h"
16 
17 #include <dt-bindings/clock/mt7622-clk.h>
18 
19 #define GATE_ETH(_id, _name, _parent, _shift) {	\
20 		.id = _id,				\
21 		.name = _name,				\
22 		.parent_name = _parent,			\
23 		.regs = &eth_cg_regs,			\
24 		.shift = _shift,			\
25 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
26 	}
27 
28 static const struct mtk_gate_regs eth_cg_regs = {
29 	.set_ofs = 0x30,
30 	.clr_ofs = 0x30,
31 	.sta_ofs = 0x30,
32 };
33 
34 static const struct mtk_gate eth_clks[] = {
35 	GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
36 	GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
37 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
38 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
39 	GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
40 };
41 
42 static const struct mtk_gate_regs sgmii_cg_regs = {
43 	.set_ofs = 0xE4,
44 	.clr_ofs = 0xE4,
45 	.sta_ofs = 0xE4,
46 };
47 
48 #define GATE_SGMII(_id, _name, _parent, _shift) {	\
49 		.id = _id,				\
50 		.name = _name,				\
51 		.parent_name = _parent,			\
52 		.regs = &sgmii_cg_regs,			\
53 		.shift = _shift,			\
54 		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
55 	}
56 
57 static const struct mtk_gate sgmii_clks[] = {
58 	GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
59 		   "ssusb_tx250m", 2),
60 	GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
61 		   "ssusb_eq_rx250m", 3),
62 	GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
63 		   "ssusb_cdr_ref", 4),
64 	GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
65 		   "ssusb_cdr_fb", 5),
66 };
67 
68 static u16 rst_ofs[] = { 0x34, };
69 
70 static const struct mtk_clk_rst_desc clk_rst_desc = {
71 	.version = MTK_RST_SIMPLE,
72 	.rst_bank_ofs = rst_ofs,
73 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
74 };
75 
76 static const struct mtk_clk_desc eth_desc = {
77 	.clks = eth_clks,
78 	.num_clks = ARRAY_SIZE(eth_clks),
79 	.rst_desc = &clk_rst_desc,
80 };
81 
82 static const struct mtk_clk_desc sgmii_desc = {
83 	.clks = sgmii_clks,
84 	.num_clks = ARRAY_SIZE(sgmii_clks),
85 };
86 
87 static const struct of_device_id of_match_clk_mt7622_eth[] = {
88 	{ .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
89 	{ .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
90 	{ /* sentinel */ }
91 };
92 
93 static struct platform_driver clk_mt7622_eth_drv = {
94 	.probe = mtk_clk_simple_probe,
95 	.remove = mtk_clk_simple_remove,
96 	.driver = {
97 		.name = "clk-mt7622-eth",
98 		.of_match_table = of_match_clk_mt7622_eth,
99 	},
100 };
101 
102 builtin_platform_driver(clk_mt7622_eth_drv);
103