1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Chen Zhong <chen.zhong@mediatek.com> 5 * Sean Wang <sean.wang@mediatek.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 14 #include "clk-mtk.h" 15 #include "clk-gate.h" 16 17 #include <dt-bindings/clock/mt7622-clk.h> 18 19 #define GATE_ETH(_id, _name, _parent, _shift) { \ 20 .id = _id, \ 21 .name = _name, \ 22 .parent_name = _parent, \ 23 .regs = ð_cg_regs, \ 24 .shift = _shift, \ 25 .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 26 } 27 28 static const struct mtk_gate_regs eth_cg_regs = { 29 .set_ofs = 0x30, 30 .clr_ofs = 0x30, 31 .sta_ofs = 0x30, 32 }; 33 34 static const struct mtk_gate eth_clks[] = { 35 GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), 36 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), 37 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 38 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 39 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), 40 }; 41 42 static const struct mtk_gate_regs sgmii_cg_regs = { 43 .set_ofs = 0xE4, 44 .clr_ofs = 0xE4, 45 .sta_ofs = 0xE4, 46 }; 47 48 #define GATE_SGMII(_id, _name, _parent, _shift) { \ 49 .id = _id, \ 50 .name = _name, \ 51 .parent_name = _parent, \ 52 .regs = &sgmii_cg_regs, \ 53 .shift = _shift, \ 54 .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 55 } 56 57 static const struct mtk_gate sgmii_clks[] = { 58 GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", 59 "ssusb_tx250m", 2), 60 GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en", 61 "ssusb_eq_rx250m", 3), 62 GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref", 63 "ssusb_cdr_ref", 4), 64 GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb", 65 "ssusb_cdr_fb", 5), 66 }; 67 68 static const struct mtk_clk_rst_desc clk_rst_desc = { 69 .version = MTK_RST_SIMPLE, 70 .rst_bank_nr = 1, 71 .reg_ofs = 0x34, 72 }; 73 74 static int clk_mt7622_ethsys_init(struct platform_device *pdev) 75 { 76 struct clk_hw_onecell_data *clk_data; 77 struct device_node *node = pdev->dev.of_node; 78 int r; 79 80 clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); 81 82 mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), 83 clk_data); 84 85 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 86 if (r) 87 dev_err(&pdev->dev, 88 "could not register clock provider: %s: %d\n", 89 pdev->name, r); 90 91 mtk_register_reset_controller(node, &clk_rst_desc); 92 93 return r; 94 } 95 96 static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) 97 { 98 struct clk_hw_onecell_data *clk_data; 99 struct device_node *node = pdev->dev.of_node; 100 int r; 101 102 clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); 103 104 mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), 105 clk_data); 106 107 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 108 if (r) 109 dev_err(&pdev->dev, 110 "could not register clock provider: %s: %d\n", 111 pdev->name, r); 112 113 return r; 114 } 115 116 static const struct of_device_id of_match_clk_mt7622_eth[] = { 117 { 118 .compatible = "mediatek,mt7622-ethsys", 119 .data = clk_mt7622_ethsys_init, 120 }, { 121 .compatible = "mediatek,mt7622-sgmiisys", 122 .data = clk_mt7622_sgmiisys_init, 123 }, { 124 /* sentinel */ 125 } 126 }; 127 128 static int clk_mt7622_eth_probe(struct platform_device *pdev) 129 { 130 int (*clk_init)(struct platform_device *); 131 int r; 132 133 clk_init = of_device_get_match_data(&pdev->dev); 134 if (!clk_init) 135 return -EINVAL; 136 137 r = clk_init(pdev); 138 if (r) 139 dev_err(&pdev->dev, 140 "could not register clock provider: %s: %d\n", 141 pdev->name, r); 142 143 return r; 144 } 145 146 static struct platform_driver clk_mt7622_eth_drv = { 147 .probe = clk_mt7622_eth_probe, 148 .driver = { 149 .name = "clk-mt7622-eth", 150 .of_match_table = of_match_clk_mt7622_eth, 151 }, 152 }; 153 154 builtin_platform_driver(clk_mt7622_eth_drv); 155