1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017 MediaTek Inc.
4  * Author: Chen Zhong <chen.zhong@mediatek.com>
5  *	   Sean Wang <sean.wang@mediatek.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 
14 #include "clk-mtk.h"
15 #include "clk-gate.h"
16 
17 #include <dt-bindings/clock/mt7622-clk.h>
18 
19 #define GATE_ETH(_id, _name, _parent, _shift)			\
20 	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
21 
22 static const struct mtk_gate_regs eth_cg_regs = {
23 	.set_ofs = 0x30,
24 	.clr_ofs = 0x30,
25 	.sta_ofs = 0x30,
26 };
27 
28 static const struct mtk_gate eth_clks[] = {
29 	GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
30 	GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
31 	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
32 	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
33 	GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
34 };
35 
36 static const struct mtk_gate_regs sgmii_cg_regs = {
37 	.set_ofs = 0xE4,
38 	.clr_ofs = 0xE4,
39 	.sta_ofs = 0xE4,
40 };
41 
42 #define GATE_SGMII(_id, _name, _parent, _shift)			\
43 	GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
44 
45 static const struct mtk_gate sgmii_clks[] = {
46 	GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
47 		   "ssusb_tx250m", 2),
48 	GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
49 		   "ssusb_eq_rx250m", 3),
50 	GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
51 		   "ssusb_cdr_ref", 4),
52 	GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
53 		   "ssusb_cdr_fb", 5),
54 };
55 
56 static u16 rst_ofs[] = { 0x34, };
57 
58 static const struct mtk_clk_rst_desc clk_rst_desc = {
59 	.version = MTK_RST_SIMPLE,
60 	.rst_bank_ofs = rst_ofs,
61 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
62 };
63 
64 static const struct mtk_clk_desc eth_desc = {
65 	.clks = eth_clks,
66 	.num_clks = ARRAY_SIZE(eth_clks),
67 	.rst_desc = &clk_rst_desc,
68 };
69 
70 static const struct mtk_clk_desc sgmii_desc = {
71 	.clks = sgmii_clks,
72 	.num_clks = ARRAY_SIZE(sgmii_clks),
73 };
74 
75 static const struct of_device_id of_match_clk_mt7622_eth[] = {
76 	{ .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
77 	{ .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
78 	{ /* sentinel */ }
79 };
80 MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_eth);
81 
82 static struct platform_driver clk_mt7622_eth_drv = {
83 	.probe = mtk_clk_simple_probe,
84 	.remove = mtk_clk_simple_remove,
85 	.driver = {
86 		.name = "clk-mt7622-eth",
87 		.of_match_table = of_match_clk_mt7622_eth,
88 	},
89 };
90 module_platform_driver(clk_mt7622_eth_drv);
91 MODULE_LICENSE("GPL");
92