12fc0a509SSean Wang /* 22fc0a509SSean Wang * Copyright (c) 2017 MediaTek Inc. 32fc0a509SSean Wang * Author: Chen Zhong <chen.zhong@mediatek.com> 42fc0a509SSean Wang * Sean Wang <sean.wang@mediatek.com> 52fc0a509SSean Wang * 62fc0a509SSean Wang * This program is free software; you can redistribute it and/or modify 72fc0a509SSean Wang * it under the terms of the GNU General Public License version 2 as 82fc0a509SSean Wang * published by the Free Software Foundation. 92fc0a509SSean Wang * 102fc0a509SSean Wang * This program is distributed in the hope that it will be useful, 112fc0a509SSean Wang * but WITHOUT ANY WARRANTY; without even the implied warranty of 122fc0a509SSean Wang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 132fc0a509SSean Wang * GNU General Public License for more details. 142fc0a509SSean Wang */ 152fc0a509SSean Wang 162fc0a509SSean Wang #include <linux/clk-provider.h> 172fc0a509SSean Wang #include <linux/of.h> 182fc0a509SSean Wang #include <linux/of_address.h> 192fc0a509SSean Wang #include <linux/of_device.h> 202fc0a509SSean Wang #include <linux/platform_device.h> 212fc0a509SSean Wang 222fc0a509SSean Wang #include "clk-mtk.h" 232fc0a509SSean Wang #include "clk-gate.h" 242fc0a509SSean Wang 252fc0a509SSean Wang #include <dt-bindings/clock/mt7622-clk.h> 262fc0a509SSean Wang 272fc0a509SSean Wang #define GATE_ETH(_id, _name, _parent, _shift) { \ 282fc0a509SSean Wang .id = _id, \ 292fc0a509SSean Wang .name = _name, \ 302fc0a509SSean Wang .parent_name = _parent, \ 312fc0a509SSean Wang .regs = ð_cg_regs, \ 322fc0a509SSean Wang .shift = _shift, \ 332fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 342fc0a509SSean Wang } 352fc0a509SSean Wang 362fc0a509SSean Wang static const struct mtk_gate_regs eth_cg_regs = { 372fc0a509SSean Wang .set_ofs = 0x30, 382fc0a509SSean Wang .clr_ofs = 0x30, 392fc0a509SSean Wang .sta_ofs = 0x30, 402fc0a509SSean Wang }; 412fc0a509SSean Wang 422fc0a509SSean Wang static const struct mtk_gate eth_clks[] = { 432fc0a509SSean Wang GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), 442fc0a509SSean Wang GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), 452fc0a509SSean Wang GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 462fc0a509SSean Wang GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 472fc0a509SSean Wang GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), 482fc0a509SSean Wang }; 492fc0a509SSean Wang 502fc0a509SSean Wang static const struct mtk_gate_regs sgmii_cg_regs = { 512fc0a509SSean Wang .set_ofs = 0xE4, 522fc0a509SSean Wang .clr_ofs = 0xE4, 532fc0a509SSean Wang .sta_ofs = 0xE4, 542fc0a509SSean Wang }; 552fc0a509SSean Wang 562fc0a509SSean Wang #define GATE_SGMII(_id, _name, _parent, _shift) { \ 572fc0a509SSean Wang .id = _id, \ 582fc0a509SSean Wang .name = _name, \ 592fc0a509SSean Wang .parent_name = _parent, \ 602fc0a509SSean Wang .regs = &sgmii_cg_regs, \ 612fc0a509SSean Wang .shift = _shift, \ 622fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 632fc0a509SSean Wang } 642fc0a509SSean Wang 652fc0a509SSean Wang static const struct mtk_gate sgmii_clks[] = { 662fc0a509SSean Wang GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", 672fc0a509SSean Wang "ssusb_tx250m", 2), 682fc0a509SSean Wang GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en", 692fc0a509SSean Wang "ssusb_eq_rx250m", 3), 702fc0a509SSean Wang GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref", 712fc0a509SSean Wang "ssusb_cdr_ref", 4), 722fc0a509SSean Wang GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb", 732fc0a509SSean Wang "ssusb_cdr_fb", 5), 742fc0a509SSean Wang }; 752fc0a509SSean Wang 762fc0a509SSean Wang static int clk_mt7622_ethsys_init(struct platform_device *pdev) 772fc0a509SSean Wang { 782fc0a509SSean Wang struct clk_onecell_data *clk_data; 792fc0a509SSean Wang struct device_node *node = pdev->dev.of_node; 802fc0a509SSean Wang int r; 812fc0a509SSean Wang 822fc0a509SSean Wang clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); 832fc0a509SSean Wang 842fc0a509SSean Wang mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), 852fc0a509SSean Wang clk_data); 862fc0a509SSean Wang 872fc0a509SSean Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 882fc0a509SSean Wang if (r) 892fc0a509SSean Wang dev_err(&pdev->dev, 902fc0a509SSean Wang "could not register clock provider: %s: %d\n", 912fc0a509SSean Wang pdev->name, r); 922fc0a509SSean Wang 932fc0a509SSean Wang mtk_register_reset_controller(node, 1, 0x34); 942fc0a509SSean Wang 952fc0a509SSean Wang return r; 962fc0a509SSean Wang } 972fc0a509SSean Wang 982fc0a509SSean Wang static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) 992fc0a509SSean Wang { 1002fc0a509SSean Wang struct clk_onecell_data *clk_data; 1012fc0a509SSean Wang struct device_node *node = pdev->dev.of_node; 1022fc0a509SSean Wang int r; 1032fc0a509SSean Wang 1042fc0a509SSean Wang clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); 1052fc0a509SSean Wang 1062fc0a509SSean Wang mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), 1072fc0a509SSean Wang clk_data); 1082fc0a509SSean Wang 1092fc0a509SSean Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1102fc0a509SSean Wang if (r) 1112fc0a509SSean Wang dev_err(&pdev->dev, 1122fc0a509SSean Wang "could not register clock provider: %s: %d\n", 1132fc0a509SSean Wang pdev->name, r); 1142fc0a509SSean Wang 1152fc0a509SSean Wang return r; 1162fc0a509SSean Wang } 1172fc0a509SSean Wang 1182fc0a509SSean Wang static const struct of_device_id of_match_clk_mt7622_eth[] = { 1192fc0a509SSean Wang { 1202fc0a509SSean Wang .compatible = "mediatek,mt7622-ethsys", 1212fc0a509SSean Wang .data = clk_mt7622_ethsys_init, 1222fc0a509SSean Wang }, { 1232fc0a509SSean Wang .compatible = "mediatek,mt7622-sgmiisys", 1242fc0a509SSean Wang .data = clk_mt7622_sgmiisys_init, 1252fc0a509SSean Wang }, { 1262fc0a509SSean Wang /* sentinel */ 1272fc0a509SSean Wang } 1282fc0a509SSean Wang }; 1292fc0a509SSean Wang 1302fc0a509SSean Wang static int clk_mt7622_eth_probe(struct platform_device *pdev) 1312fc0a509SSean Wang { 1322fc0a509SSean Wang int (*clk_init)(struct platform_device *); 1332fc0a509SSean Wang int r; 1342fc0a509SSean Wang 1352fc0a509SSean Wang clk_init = of_device_get_match_data(&pdev->dev); 1362fc0a509SSean Wang if (!clk_init) 1372fc0a509SSean Wang return -EINVAL; 1382fc0a509SSean Wang 1392fc0a509SSean Wang r = clk_init(pdev); 1402fc0a509SSean Wang if (r) 1412fc0a509SSean Wang dev_err(&pdev->dev, 1422fc0a509SSean Wang "could not register clock provider: %s: %d\n", 1432fc0a509SSean Wang pdev->name, r); 1442fc0a509SSean Wang 1452fc0a509SSean Wang return r; 1462fc0a509SSean Wang } 1472fc0a509SSean Wang 1482fc0a509SSean Wang static struct platform_driver clk_mt7622_eth_drv = { 1492fc0a509SSean Wang .probe = clk_mt7622_eth_probe, 1502fc0a509SSean Wang .driver = { 1512fc0a509SSean Wang .name = "clk-mt7622-eth", 1522fc0a509SSean Wang .of_match_table = of_match_clk_mt7622_eth, 1532fc0a509SSean Wang }, 1542fc0a509SSean Wang }; 1552fc0a509SSean Wang 1562fc0a509SSean Wang builtin_platform_driver(clk_mt7622_eth_drv); 157