11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22fc0a509SSean Wang /* 32fc0a509SSean Wang * Copyright (c) 2017 MediaTek Inc. 42fc0a509SSean Wang * Author: Chen Zhong <chen.zhong@mediatek.com> 52fc0a509SSean Wang * Sean Wang <sean.wang@mediatek.com> 62fc0a509SSean Wang */ 72fc0a509SSean Wang 82fc0a509SSean Wang #include <linux/clk-provider.h> 92fc0a509SSean Wang #include <linux/of.h> 102fc0a509SSean Wang #include <linux/of_address.h> 112fc0a509SSean Wang #include <linux/of_device.h> 122fc0a509SSean Wang #include <linux/platform_device.h> 132fc0a509SSean Wang 142fc0a509SSean Wang #include "clk-mtk.h" 152fc0a509SSean Wang #include "clk-gate.h" 162fc0a509SSean Wang 172fc0a509SSean Wang #include <dt-bindings/clock/mt7622-clk.h> 182fc0a509SSean Wang 192fc0a509SSean Wang #define GATE_ETH(_id, _name, _parent, _shift) { \ 202fc0a509SSean Wang .id = _id, \ 212fc0a509SSean Wang .name = _name, \ 222fc0a509SSean Wang .parent_name = _parent, \ 232fc0a509SSean Wang .regs = ð_cg_regs, \ 242fc0a509SSean Wang .shift = _shift, \ 252fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 262fc0a509SSean Wang } 272fc0a509SSean Wang 282fc0a509SSean Wang static const struct mtk_gate_regs eth_cg_regs = { 292fc0a509SSean Wang .set_ofs = 0x30, 302fc0a509SSean Wang .clr_ofs = 0x30, 312fc0a509SSean Wang .sta_ofs = 0x30, 322fc0a509SSean Wang }; 332fc0a509SSean Wang 342fc0a509SSean Wang static const struct mtk_gate eth_clks[] = { 352fc0a509SSean Wang GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), 362fc0a509SSean Wang GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), 372fc0a509SSean Wang GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 382fc0a509SSean Wang GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 392fc0a509SSean Wang GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), 402fc0a509SSean Wang }; 412fc0a509SSean Wang 422fc0a509SSean Wang static const struct mtk_gate_regs sgmii_cg_regs = { 432fc0a509SSean Wang .set_ofs = 0xE4, 442fc0a509SSean Wang .clr_ofs = 0xE4, 452fc0a509SSean Wang .sta_ofs = 0xE4, 462fc0a509SSean Wang }; 472fc0a509SSean Wang 482fc0a509SSean Wang #define GATE_SGMII(_id, _name, _parent, _shift) { \ 492fc0a509SSean Wang .id = _id, \ 502fc0a509SSean Wang .name = _name, \ 512fc0a509SSean Wang .parent_name = _parent, \ 522fc0a509SSean Wang .regs = &sgmii_cg_regs, \ 532fc0a509SSean Wang .shift = _shift, \ 542fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 552fc0a509SSean Wang } 562fc0a509SSean Wang 572fc0a509SSean Wang static const struct mtk_gate sgmii_clks[] = { 582fc0a509SSean Wang GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", 592fc0a509SSean Wang "ssusb_tx250m", 2), 602fc0a509SSean Wang GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en", 612fc0a509SSean Wang "ssusb_eq_rx250m", 3), 622fc0a509SSean Wang GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref", 632fc0a509SSean Wang "ssusb_cdr_ref", 4), 642fc0a509SSean Wang GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb", 652fc0a509SSean Wang "ssusb_cdr_fb", 5), 662fc0a509SSean Wang }; 672fc0a509SSean Wang 682fc0a509SSean Wang static int clk_mt7622_ethsys_init(struct platform_device *pdev) 692fc0a509SSean Wang { 702fc0a509SSean Wang struct clk_onecell_data *clk_data; 712fc0a509SSean Wang struct device_node *node = pdev->dev.of_node; 722fc0a509SSean Wang int r; 732fc0a509SSean Wang 742fc0a509SSean Wang clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); 752fc0a509SSean Wang 762fc0a509SSean Wang mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), 772fc0a509SSean Wang clk_data); 782fc0a509SSean Wang 792fc0a509SSean Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 802fc0a509SSean Wang if (r) 812fc0a509SSean Wang dev_err(&pdev->dev, 822fc0a509SSean Wang "could not register clock provider: %s: %d\n", 832fc0a509SSean Wang pdev->name, r); 842fc0a509SSean Wang 852fc0a509SSean Wang mtk_register_reset_controller(node, 1, 0x34); 862fc0a509SSean Wang 872fc0a509SSean Wang return r; 882fc0a509SSean Wang } 892fc0a509SSean Wang 902fc0a509SSean Wang static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) 912fc0a509SSean Wang { 922fc0a509SSean Wang struct clk_onecell_data *clk_data; 932fc0a509SSean Wang struct device_node *node = pdev->dev.of_node; 942fc0a509SSean Wang int r; 952fc0a509SSean Wang 962fc0a509SSean Wang clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); 972fc0a509SSean Wang 982fc0a509SSean Wang mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), 992fc0a509SSean Wang clk_data); 1002fc0a509SSean Wang 1012fc0a509SSean Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1022fc0a509SSean Wang if (r) 1032fc0a509SSean Wang dev_err(&pdev->dev, 1042fc0a509SSean Wang "could not register clock provider: %s: %d\n", 1052fc0a509SSean Wang pdev->name, r); 1062fc0a509SSean Wang 1072fc0a509SSean Wang return r; 1082fc0a509SSean Wang } 1092fc0a509SSean Wang 1102fc0a509SSean Wang static const struct of_device_id of_match_clk_mt7622_eth[] = { 1112fc0a509SSean Wang { 1122fc0a509SSean Wang .compatible = "mediatek,mt7622-ethsys", 1132fc0a509SSean Wang .data = clk_mt7622_ethsys_init, 1142fc0a509SSean Wang }, { 1152fc0a509SSean Wang .compatible = "mediatek,mt7622-sgmiisys", 1162fc0a509SSean Wang .data = clk_mt7622_sgmiisys_init, 1172fc0a509SSean Wang }, { 1182fc0a509SSean Wang /* sentinel */ 1192fc0a509SSean Wang } 1202fc0a509SSean Wang }; 1212fc0a509SSean Wang 1222fc0a509SSean Wang static int clk_mt7622_eth_probe(struct platform_device *pdev) 1232fc0a509SSean Wang { 1242fc0a509SSean Wang int (*clk_init)(struct platform_device *); 1252fc0a509SSean Wang int r; 1262fc0a509SSean Wang 1272fc0a509SSean Wang clk_init = of_device_get_match_data(&pdev->dev); 1282fc0a509SSean Wang if (!clk_init) 1292fc0a509SSean Wang return -EINVAL; 1302fc0a509SSean Wang 1312fc0a509SSean Wang r = clk_init(pdev); 1322fc0a509SSean Wang if (r) 1332fc0a509SSean Wang dev_err(&pdev->dev, 1342fc0a509SSean Wang "could not register clock provider: %s: %d\n", 1352fc0a509SSean Wang pdev->name, r); 1362fc0a509SSean Wang 1372fc0a509SSean Wang return r; 1382fc0a509SSean Wang } 1392fc0a509SSean Wang 1402fc0a509SSean Wang static struct platform_driver clk_mt7622_eth_drv = { 1412fc0a509SSean Wang .probe = clk_mt7622_eth_probe, 1422fc0a509SSean Wang .driver = { 1432fc0a509SSean Wang .name = "clk-mt7622-eth", 1442fc0a509SSean Wang .of_match_table = of_match_clk_mt7622_eth, 1452fc0a509SSean Wang }, 1462fc0a509SSean Wang }; 1472fc0a509SSean Wang 1482fc0a509SSean Wang builtin_platform_driver(clk_mt7622_eth_drv); 149