11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22fc0a509SSean Wang /* 32fc0a509SSean Wang * Copyright (c) 2017 MediaTek Inc. 42fc0a509SSean Wang * Author: Chen Zhong <chen.zhong@mediatek.com> 52fc0a509SSean Wang * Sean Wang <sean.wang@mediatek.com> 62fc0a509SSean Wang */ 72fc0a509SSean Wang 82fc0a509SSean Wang #include <linux/clk-provider.h> 92fc0a509SSean Wang #include <linux/of.h> 102fc0a509SSean Wang #include <linux/of_address.h> 112fc0a509SSean Wang #include <linux/of_device.h> 122fc0a509SSean Wang #include <linux/platform_device.h> 132fc0a509SSean Wang 142fc0a509SSean Wang #include "clk-mtk.h" 152fc0a509SSean Wang #include "clk-gate.h" 162fc0a509SSean Wang 172fc0a509SSean Wang #include <dt-bindings/clock/mt7622-clk.h> 182fc0a509SSean Wang 192fc0a509SSean Wang #define GATE_ETH(_id, _name, _parent, _shift) { \ 202fc0a509SSean Wang .id = _id, \ 212fc0a509SSean Wang .name = _name, \ 222fc0a509SSean Wang .parent_name = _parent, \ 232fc0a509SSean Wang .regs = ð_cg_regs, \ 242fc0a509SSean Wang .shift = _shift, \ 252fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 262fc0a509SSean Wang } 272fc0a509SSean Wang 282fc0a509SSean Wang static const struct mtk_gate_regs eth_cg_regs = { 292fc0a509SSean Wang .set_ofs = 0x30, 302fc0a509SSean Wang .clr_ofs = 0x30, 312fc0a509SSean Wang .sta_ofs = 0x30, 322fc0a509SSean Wang }; 332fc0a509SSean Wang 342fc0a509SSean Wang static const struct mtk_gate eth_clks[] = { 352fc0a509SSean Wang GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), 362fc0a509SSean Wang GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), 372fc0a509SSean Wang GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), 382fc0a509SSean Wang GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), 392fc0a509SSean Wang GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), 402fc0a509SSean Wang }; 412fc0a509SSean Wang 422fc0a509SSean Wang static const struct mtk_gate_regs sgmii_cg_regs = { 432fc0a509SSean Wang .set_ofs = 0xE4, 442fc0a509SSean Wang .clr_ofs = 0xE4, 452fc0a509SSean Wang .sta_ofs = 0xE4, 462fc0a509SSean Wang }; 472fc0a509SSean Wang 482fc0a509SSean Wang #define GATE_SGMII(_id, _name, _parent, _shift) { \ 492fc0a509SSean Wang .id = _id, \ 502fc0a509SSean Wang .name = _name, \ 512fc0a509SSean Wang .parent_name = _parent, \ 522fc0a509SSean Wang .regs = &sgmii_cg_regs, \ 532fc0a509SSean Wang .shift = _shift, \ 542fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr_inv, \ 552fc0a509SSean Wang } 562fc0a509SSean Wang 572fc0a509SSean Wang static const struct mtk_gate sgmii_clks[] = { 582fc0a509SSean Wang GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", 592fc0a509SSean Wang "ssusb_tx250m", 2), 602fc0a509SSean Wang GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en", 612fc0a509SSean Wang "ssusb_eq_rx250m", 3), 622fc0a509SSean Wang GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref", 632fc0a509SSean Wang "ssusb_cdr_ref", 4), 642fc0a509SSean Wang GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb", 652fc0a509SSean Wang "ssusb_cdr_fb", 5), 662fc0a509SSean Wang }; 672fc0a509SSean Wang 68723e3671SRex-BC Chen static u16 rst_ofs[] = { 0x34, }; 69723e3671SRex-BC Chen 702d2a2900SRex-BC Chen static const struct mtk_clk_rst_desc clk_rst_desc = { 712d2a2900SRex-BC Chen .version = MTK_RST_SIMPLE, 72723e3671SRex-BC Chen .rst_bank_ofs = rst_ofs, 73723e3671SRex-BC Chen .rst_bank_nr = ARRAY_SIZE(rst_ofs), 742d2a2900SRex-BC Chen }; 752d2a2900SRex-BC Chen 76*0f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc eth_desc = { 77*0f69a423SAngeloGioacchino Del Regno .clks = eth_clks, 78*0f69a423SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(eth_clks), 79*0f69a423SAngeloGioacchino Del Regno .rst_desc = &clk_rst_desc, 802fc0a509SSean Wang }; 812fc0a509SSean Wang 82*0f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc sgmii_desc = { 83*0f69a423SAngeloGioacchino Del Regno .clks = sgmii_clks, 84*0f69a423SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(sgmii_clks), 85*0f69a423SAngeloGioacchino Del Regno }; 862fc0a509SSean Wang 87*0f69a423SAngeloGioacchino Del Regno static const struct of_device_id of_match_clk_mt7622_eth[] = { 88*0f69a423SAngeloGioacchino Del Regno { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc }, 89*0f69a423SAngeloGioacchino Del Regno { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, 90*0f69a423SAngeloGioacchino Del Regno { /* sentinel */ } 91*0f69a423SAngeloGioacchino Del Regno }; 922fc0a509SSean Wang 932fc0a509SSean Wang static struct platform_driver clk_mt7622_eth_drv = { 94*0f69a423SAngeloGioacchino Del Regno .probe = mtk_clk_simple_probe, 95*0f69a423SAngeloGioacchino Del Regno .remove = mtk_clk_simple_remove, 962fc0a509SSean Wang .driver = { 972fc0a509SSean Wang .name = "clk-mt7622-eth", 982fc0a509SSean Wang .of_match_table = of_match_clk_mt7622_eth, 992fc0a509SSean Wang }, 1002fc0a509SSean Wang }; 1012fc0a509SSean Wang 1022fc0a509SSean Wang builtin_platform_driver(clk_mt7622_eth_drv); 103