1 /* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Chen Zhong <chen.zhong@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 22 #include "clk-mtk.h" 23 #include "clk-gate.h" 24 25 #include <dt-bindings/clock/mt7622-clk.h> 26 27 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ 28 .id = _id, \ 29 .name = _name, \ 30 .parent_name = _parent, \ 31 .regs = &audio0_cg_regs, \ 32 .shift = _shift, \ 33 .ops = &mtk_clk_gate_ops_no_setclr, \ 34 } 35 36 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ 37 .id = _id, \ 38 .name = _name, \ 39 .parent_name = _parent, \ 40 .regs = &audio1_cg_regs, \ 41 .shift = _shift, \ 42 .ops = &mtk_clk_gate_ops_no_setclr, \ 43 } 44 45 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ 46 .id = _id, \ 47 .name = _name, \ 48 .parent_name = _parent, \ 49 .regs = &audio2_cg_regs, \ 50 .shift = _shift, \ 51 .ops = &mtk_clk_gate_ops_no_setclr, \ 52 } 53 54 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ 55 .id = _id, \ 56 .name = _name, \ 57 .parent_name = _parent, \ 58 .regs = &audio3_cg_regs, \ 59 .shift = _shift, \ 60 .ops = &mtk_clk_gate_ops_no_setclr, \ 61 } 62 63 static const struct mtk_gate_regs audio0_cg_regs = { 64 .set_ofs = 0x0, 65 .clr_ofs = 0x0, 66 .sta_ofs = 0x0, 67 }; 68 69 static const struct mtk_gate_regs audio1_cg_regs = { 70 .set_ofs = 0x10, 71 .clr_ofs = 0x10, 72 .sta_ofs = 0x10, 73 }; 74 75 static const struct mtk_gate_regs audio2_cg_regs = { 76 .set_ofs = 0x14, 77 .clr_ofs = 0x14, 78 .sta_ofs = 0x14, 79 }; 80 81 static const struct mtk_gate_regs audio3_cg_regs = { 82 .set_ofs = 0x634, 83 .clr_ofs = 0x634, 84 .sta_ofs = 0x634, 85 }; 86 87 static const struct mtk_gate audio_clks[] = { 88 /* AUDIO0 */ 89 GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2), 90 GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20), 91 GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21), 92 GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23), 93 /* AUDIO1 */ 94 GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0), 95 GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1), 96 GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2), 97 GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3), 98 GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6), 99 GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7), 100 GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8), 101 GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9), 102 GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12), 103 GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13), 104 GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14), 105 GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15), 106 GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20), 107 GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21), 108 GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22), 109 /* AUDIO2 */ 110 GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0), 111 GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1), 112 GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2), 113 GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3), 114 GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4), 115 GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5), 116 GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6), 117 GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7), 118 GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8), 119 GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9), 120 GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10), 121 GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11), 122 GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12), 123 GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13), 124 GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14), 125 GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15), 126 GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16), 127 GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17), 128 /* AUDIO3 */ 129 GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2), 130 GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3), 131 GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6), 132 GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7), 133 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10), 134 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11), 135 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12), 136 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13), 137 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), 138 }; 139 140 static int clk_mt7622_audiosys_init(struct platform_device *pdev) 141 { 142 struct clk_onecell_data *clk_data; 143 struct device_node *node = pdev->dev.of_node; 144 int r; 145 146 clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); 147 148 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), 149 clk_data); 150 151 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 152 if (r) 153 dev_err(&pdev->dev, 154 "could not register clock provider: %s: %d\n", 155 pdev->name, r); 156 157 return r; 158 } 159 160 static const struct of_device_id of_match_clk_mt7622_aud[] = { 161 { 162 .compatible = "mediatek,mt7622-audsys", 163 .data = clk_mt7622_audiosys_init, 164 }, { 165 /* sentinel */ 166 } 167 }; 168 169 static int clk_mt7622_aud_probe(struct platform_device *pdev) 170 { 171 int (*clk_init)(struct platform_device *); 172 int r; 173 174 clk_init = of_device_get_match_data(&pdev->dev); 175 if (!clk_init) 176 return -EINVAL; 177 178 r = clk_init(pdev); 179 if (r) 180 dev_err(&pdev->dev, 181 "could not register clock provider: %s: %d\n", 182 pdev->name, r); 183 184 return r; 185 } 186 187 static struct platform_driver clk_mt7622_aud_drv = { 188 .probe = clk_mt7622_aud_probe, 189 .driver = { 190 .name = "clk-mt7622-aud", 191 .of_match_table = of_match_clk_mt7622_aud, 192 }, 193 }; 194 195 builtin_platform_driver(clk_mt7622_aud_drv); 196