11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22fc0a509SSean Wang /* 32fc0a509SSean Wang * Copyright (c) 2017 MediaTek Inc. 42fc0a509SSean Wang * Author: Chen Zhong <chen.zhong@mediatek.com> 52fc0a509SSean Wang * Sean Wang <sean.wang@mediatek.com> 62fc0a509SSean Wang */ 72fc0a509SSean Wang 82fc0a509SSean Wang #include <linux/clk-provider.h> 92fc0a509SSean Wang #include <linux/of.h> 102fc0a509SSean Wang #include <linux/of_address.h> 112fc0a509SSean Wang #include <linux/of_device.h> 122fc0a509SSean Wang #include <linux/platform_device.h> 132fc0a509SSean Wang 142fc0a509SSean Wang #include "clk-mtk.h" 152fc0a509SSean Wang #include "clk-gate.h" 162fc0a509SSean Wang 172fc0a509SSean Wang #include <dt-bindings/clock/mt7622-clk.h> 182fc0a509SSean Wang 194c85e20bSAngeloGioacchino Del Regno #define GATE_AUDIO0(_id, _name, _parent, _shift) \ 204c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 212fc0a509SSean Wang 224c85e20bSAngeloGioacchino Del Regno #define GATE_AUDIO1(_id, _name, _parent, _shift) \ 234c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 242fc0a509SSean Wang 254c85e20bSAngeloGioacchino Del Regno #define GATE_AUDIO2(_id, _name, _parent, _shift) \ 264c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 272fc0a509SSean Wang 284c85e20bSAngeloGioacchino Del Regno #define GATE_AUDIO3(_id, _name, _parent, _shift) \ 294c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 302fc0a509SSean Wang 312fc0a509SSean Wang static const struct mtk_gate_regs audio0_cg_regs = { 322fc0a509SSean Wang .set_ofs = 0x0, 332fc0a509SSean Wang .clr_ofs = 0x0, 342fc0a509SSean Wang .sta_ofs = 0x0, 352fc0a509SSean Wang }; 362fc0a509SSean Wang 372fc0a509SSean Wang static const struct mtk_gate_regs audio1_cg_regs = { 382fc0a509SSean Wang .set_ofs = 0x10, 392fc0a509SSean Wang .clr_ofs = 0x10, 402fc0a509SSean Wang .sta_ofs = 0x10, 412fc0a509SSean Wang }; 422fc0a509SSean Wang 432fc0a509SSean Wang static const struct mtk_gate_regs audio2_cg_regs = { 442fc0a509SSean Wang .set_ofs = 0x14, 452fc0a509SSean Wang .clr_ofs = 0x14, 462fc0a509SSean Wang .sta_ofs = 0x14, 472fc0a509SSean Wang }; 482fc0a509SSean Wang 492fc0a509SSean Wang static const struct mtk_gate_regs audio3_cg_regs = { 502fc0a509SSean Wang .set_ofs = 0x634, 512fc0a509SSean Wang .clr_ofs = 0x634, 522fc0a509SSean Wang .sta_ofs = 0x634, 532fc0a509SSean Wang }; 542fc0a509SSean Wang 552fc0a509SSean Wang static const struct mtk_gate audio_clks[] = { 562fc0a509SSean Wang /* AUDIO0 */ 572fc0a509SSean Wang GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2), 582fc0a509SSean Wang GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20), 592fc0a509SSean Wang GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21), 602fc0a509SSean Wang GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23), 612fc0a509SSean Wang /* AUDIO1 */ 622fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0), 632fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1), 642fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2), 652fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3), 662fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6), 672fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7), 682fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8), 692fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9), 702fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12), 712fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13), 722fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14), 732fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15), 742fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20), 752fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21), 762fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22), 77936ceb12SRyder Lee GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23), 782fc0a509SSean Wang /* AUDIO2 */ 792fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0), 802fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1), 812fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2), 822fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3), 832fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4), 842fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5), 852fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6), 862fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7), 872fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8), 882fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9), 892fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10), 902fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11), 912fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12), 922fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13), 932fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14), 942fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15), 952fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16), 962fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17), 972fc0a509SSean Wang /* AUDIO3 */ 982fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2), 992fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3), 1002fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6), 1012fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7), 1022fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10), 1032fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11), 1042fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12), 1052fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13), 1062fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), 1072fc0a509SSean Wang }; 1082fc0a509SSean Wang 1090f69a423SAngeloGioacchino Del Regno static const struct mtk_clk_desc audio_desc = { 1100f69a423SAngeloGioacchino Del Regno .clks = audio_clks, 1110f69a423SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(audio_clks), 1120f69a423SAngeloGioacchino Del Regno }; 1130f69a423SAngeloGioacchino Del Regno 1140f69a423SAngeloGioacchino Del Regno static int clk_mt7622_aud_probe(struct platform_device *pdev) 1152fc0a509SSean Wang { 1162fc0a509SSean Wang int r; 1172fc0a509SSean Wang 1180f69a423SAngeloGioacchino Del Regno r = mtk_clk_simple_probe(pdev); 119037b2113SRyder Lee if (r) { 1202fc0a509SSean Wang dev_err(&pdev->dev, 1212fc0a509SSean Wang "could not register clock provider: %s: %d\n", 1222fc0a509SSean Wang pdev->name, r); 1232fc0a509SSean Wang 1240f69a423SAngeloGioacchino Del Regno return r; 125037b2113SRyder Lee } 126037b2113SRyder Lee 127037b2113SRyder Lee r = devm_of_platform_populate(&pdev->dev); 128037b2113SRyder Lee if (r) 129037b2113SRyder Lee goto err_plat_populate; 130037b2113SRyder Lee 131037b2113SRyder Lee return 0; 132037b2113SRyder Lee 133037b2113SRyder Lee err_plat_populate: 1340f69a423SAngeloGioacchino Del Regno mtk_clk_simple_remove(pdev); 1352fc0a509SSean Wang return r; 1362fc0a509SSean Wang } 1372fc0a509SSean Wang 1380f69a423SAngeloGioacchino Del Regno static int clk_mt7622_aud_remove(struct platform_device *pdev) 1390f69a423SAngeloGioacchino Del Regno { 1400f69a423SAngeloGioacchino Del Regno of_platform_depopulate(&pdev->dev); 1410f69a423SAngeloGioacchino Del Regno return mtk_clk_simple_remove(pdev); 1420f69a423SAngeloGioacchino Del Regno } 1430f69a423SAngeloGioacchino Del Regno 1442fc0a509SSean Wang static const struct of_device_id of_match_clk_mt7622_aud[] = { 1450f69a423SAngeloGioacchino Del Regno { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc }, 1460f69a423SAngeloGioacchino Del Regno { /* sentinel */ } 1472fc0a509SSean Wang }; 148*65c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_aud); 1492fc0a509SSean Wang 1502fc0a509SSean Wang static struct platform_driver clk_mt7622_aud_drv = { 1512fc0a509SSean Wang .probe = clk_mt7622_aud_probe, 1520f69a423SAngeloGioacchino Del Regno .remove = clk_mt7622_aud_remove, 1532fc0a509SSean Wang .driver = { 1542fc0a509SSean Wang .name = "clk-mt7622-aud", 1552fc0a509SSean Wang .of_match_table = of_match_clk_mt7622_aud, 1562fc0a509SSean Wang }, 1572fc0a509SSean Wang }; 158164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt7622_aud_drv); 159a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 160