11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22fc0a509SSean Wang /* 32fc0a509SSean Wang * Copyright (c) 2017 MediaTek Inc. 42fc0a509SSean Wang * Author: Chen Zhong <chen.zhong@mediatek.com> 52fc0a509SSean Wang * Sean Wang <sean.wang@mediatek.com> 62fc0a509SSean Wang */ 72fc0a509SSean Wang 82fc0a509SSean Wang #include <linux/clk-provider.h> 92fc0a509SSean Wang #include <linux/of.h> 102fc0a509SSean Wang #include <linux/of_address.h> 112fc0a509SSean Wang #include <linux/of_device.h> 122fc0a509SSean Wang #include <linux/platform_device.h> 132fc0a509SSean Wang 142fc0a509SSean Wang #include "clk-mtk.h" 152fc0a509SSean Wang #include "clk-gate.h" 162fc0a509SSean Wang 172fc0a509SSean Wang #include <dt-bindings/clock/mt7622-clk.h> 182fc0a509SSean Wang 192fc0a509SSean Wang #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ 202fc0a509SSean Wang .id = _id, \ 212fc0a509SSean Wang .name = _name, \ 222fc0a509SSean Wang .parent_name = _parent, \ 232fc0a509SSean Wang .regs = &audio0_cg_regs, \ 242fc0a509SSean Wang .shift = _shift, \ 252fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr, \ 262fc0a509SSean Wang } 272fc0a509SSean Wang 282fc0a509SSean Wang #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ 292fc0a509SSean Wang .id = _id, \ 302fc0a509SSean Wang .name = _name, \ 312fc0a509SSean Wang .parent_name = _parent, \ 322fc0a509SSean Wang .regs = &audio1_cg_regs, \ 332fc0a509SSean Wang .shift = _shift, \ 342fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr, \ 352fc0a509SSean Wang } 362fc0a509SSean Wang 372fc0a509SSean Wang #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ 382fc0a509SSean Wang .id = _id, \ 392fc0a509SSean Wang .name = _name, \ 402fc0a509SSean Wang .parent_name = _parent, \ 412fc0a509SSean Wang .regs = &audio2_cg_regs, \ 422fc0a509SSean Wang .shift = _shift, \ 432fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr, \ 442fc0a509SSean Wang } 452fc0a509SSean Wang 462fc0a509SSean Wang #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ 472fc0a509SSean Wang .id = _id, \ 482fc0a509SSean Wang .name = _name, \ 492fc0a509SSean Wang .parent_name = _parent, \ 502fc0a509SSean Wang .regs = &audio3_cg_regs, \ 512fc0a509SSean Wang .shift = _shift, \ 522fc0a509SSean Wang .ops = &mtk_clk_gate_ops_no_setclr, \ 532fc0a509SSean Wang } 542fc0a509SSean Wang 552fc0a509SSean Wang static const struct mtk_gate_regs audio0_cg_regs = { 562fc0a509SSean Wang .set_ofs = 0x0, 572fc0a509SSean Wang .clr_ofs = 0x0, 582fc0a509SSean Wang .sta_ofs = 0x0, 592fc0a509SSean Wang }; 602fc0a509SSean Wang 612fc0a509SSean Wang static const struct mtk_gate_regs audio1_cg_regs = { 622fc0a509SSean Wang .set_ofs = 0x10, 632fc0a509SSean Wang .clr_ofs = 0x10, 642fc0a509SSean Wang .sta_ofs = 0x10, 652fc0a509SSean Wang }; 662fc0a509SSean Wang 672fc0a509SSean Wang static const struct mtk_gate_regs audio2_cg_regs = { 682fc0a509SSean Wang .set_ofs = 0x14, 692fc0a509SSean Wang .clr_ofs = 0x14, 702fc0a509SSean Wang .sta_ofs = 0x14, 712fc0a509SSean Wang }; 722fc0a509SSean Wang 732fc0a509SSean Wang static const struct mtk_gate_regs audio3_cg_regs = { 742fc0a509SSean Wang .set_ofs = 0x634, 752fc0a509SSean Wang .clr_ofs = 0x634, 762fc0a509SSean Wang .sta_ofs = 0x634, 772fc0a509SSean Wang }; 782fc0a509SSean Wang 792fc0a509SSean Wang static const struct mtk_gate audio_clks[] = { 802fc0a509SSean Wang /* AUDIO0 */ 812fc0a509SSean Wang GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2), 822fc0a509SSean Wang GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20), 832fc0a509SSean Wang GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21), 842fc0a509SSean Wang GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23), 852fc0a509SSean Wang /* AUDIO1 */ 862fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0), 872fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1), 882fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2), 892fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3), 902fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6), 912fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7), 922fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8), 932fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9), 942fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12), 952fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13), 962fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14), 972fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15), 982fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20), 992fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21), 1002fc0a509SSean Wang GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22), 101936ceb12SRyder Lee GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23), 1022fc0a509SSean Wang /* AUDIO2 */ 1032fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0), 1042fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1), 1052fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2), 1062fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3), 1072fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4), 1082fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5), 1092fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6), 1102fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7), 1112fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8), 1122fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9), 1132fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10), 1142fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11), 1152fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12), 1162fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13), 1172fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14), 1182fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15), 1192fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16), 1202fc0a509SSean Wang GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17), 1212fc0a509SSean Wang /* AUDIO3 */ 1222fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2), 1232fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3), 1242fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6), 1252fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7), 1262fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10), 1272fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11), 1282fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12), 1292fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13), 1302fc0a509SSean Wang GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), 1312fc0a509SSean Wang }; 1322fc0a509SSean Wang 1332fc0a509SSean Wang static int clk_mt7622_audiosys_init(struct platform_device *pdev) 1342fc0a509SSean Wang { 1352fc0a509SSean Wang struct clk_onecell_data *clk_data; 1362fc0a509SSean Wang struct device_node *node = pdev->dev.of_node; 1372fc0a509SSean Wang int r; 1382fc0a509SSean Wang 1392fc0a509SSean Wang clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); 1402fc0a509SSean Wang 1412fc0a509SSean Wang mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), 1422fc0a509SSean Wang clk_data); 1432fc0a509SSean Wang 1442fc0a509SSean Wang r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 145037b2113SRyder Lee if (r) { 1462fc0a509SSean Wang dev_err(&pdev->dev, 1472fc0a509SSean Wang "could not register clock provider: %s: %d\n", 1482fc0a509SSean Wang pdev->name, r); 1492fc0a509SSean Wang 150037b2113SRyder Lee goto err_clk_provider; 151037b2113SRyder Lee } 152037b2113SRyder Lee 153037b2113SRyder Lee r = devm_of_platform_populate(&pdev->dev); 154037b2113SRyder Lee if (r) 155037b2113SRyder Lee goto err_plat_populate; 156037b2113SRyder Lee 157037b2113SRyder Lee return 0; 158037b2113SRyder Lee 159037b2113SRyder Lee err_plat_populate: 160037b2113SRyder Lee of_clk_del_provider(node); 161037b2113SRyder Lee err_clk_provider: 1622fc0a509SSean Wang return r; 1632fc0a509SSean Wang } 1642fc0a509SSean Wang 1652fc0a509SSean Wang static const struct of_device_id of_match_clk_mt7622_aud[] = { 1662fc0a509SSean Wang { 1672fc0a509SSean Wang .compatible = "mediatek,mt7622-audsys", 1682fc0a509SSean Wang .data = clk_mt7622_audiosys_init, 1692fc0a509SSean Wang }, { 1702fc0a509SSean Wang /* sentinel */ 1712fc0a509SSean Wang } 1722fc0a509SSean Wang }; 1732fc0a509SSean Wang 1742fc0a509SSean Wang static int clk_mt7622_aud_probe(struct platform_device *pdev) 1752fc0a509SSean Wang { 1762fc0a509SSean Wang int (*clk_init)(struct platform_device *); 1772fc0a509SSean Wang int r; 1782fc0a509SSean Wang 1792fc0a509SSean Wang clk_init = of_device_get_match_data(&pdev->dev); 1802fc0a509SSean Wang if (!clk_init) 1812fc0a509SSean Wang return -EINVAL; 1822fc0a509SSean Wang 1832fc0a509SSean Wang r = clk_init(pdev); 1842fc0a509SSean Wang if (r) 1852fc0a509SSean Wang dev_err(&pdev->dev, 1862fc0a509SSean Wang "could not register clock provider: %s: %d\n", 1872fc0a509SSean Wang pdev->name, r); 1882fc0a509SSean Wang 1892fc0a509SSean Wang return r; 1902fc0a509SSean Wang } 1912fc0a509SSean Wang 1922fc0a509SSean Wang static struct platform_driver clk_mt7622_aud_drv = { 1932fc0a509SSean Wang .probe = clk_mt7622_aud_probe, 1942fc0a509SSean Wang .driver = { 1952fc0a509SSean Wang .name = "clk-mt7622-aud", 1962fc0a509SSean Wang .of_match_table = of_match_clk_mt7622_aud, 1972fc0a509SSean Wang }, 1982fc0a509SSean Wang }; 1992fc0a509SSean Wang 2002fc0a509SSean Wang builtin_platform_driver(clk_mt7622_aud_drv); 201